Forum on Specification & Design Languages

30 September 2005
 FDL '05

IEEE 1850 PSL: Overview and Status 2

 FDL '05
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IEEE 1850 PSL: Overview and Status 3

 FDL '05
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IEEE 1850 PSL: Overview and Status 4

 FDL '05

IEEE 1850 PSL: Overview and Status 5

 FDL '05

• Boolean Expressions
– HDL expressions
– built-in functions rose(), fell(), prev(), ...

• Temporal Operators
– always, never, next, until, before, eventually, abort, ...
– @ ; : { } [* ] [= ] [-> ] && & | -> <->

• Verification Directives
– assert, assume, restrict, cover, ...

• Modeling Constructs
– HDL statements used to model the environment

IEEE 1850 PSL: Overview and Status 6

 FDL '05
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IEEE 1850 PSL: Overview and Status 7

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IEEE 1850 PSL: Overview and Status 8

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IEEE 1850 PSL: Overview and Status 9

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IEEE 1850 PSL: Overview and Status 10

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IEEE 1850 PSL: Overview and Status 11

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IEEE 1850 PSL: Overview and Status 12

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IEEE 1850 PSL: Overview and Status 13
 FDL '05
D #
Interface RTL Implementation High-Level Requirements
Assertions Assertions (Data-
(Data-Integrity Check)

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PCI
Bus

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Assertions
IEEE 1850 PSL: Overview and Status 14
 FDL '05

IEEE 1850 PSL: Overview and Status 15

 FDL '05

FVTC considers:
PSL 1.0
Temporal e
defined
Sugar FVTC ForSpec
based on
created at IBM formed in CBV
Sugar 2.0
Haifa Research Labs Accellera (OVI) Sugar

1994 1998 2001 2002

Branching-time
Syntactic Linear-time
semantics
sugaring of semantics
plus regular
CTL Added to Sugar
expressions

IEEE 1850 PSL: Overview and Status 16

 FDL '05
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PSL 1.0
defined PSL 1.01 PSL 1.1 IEEE 1850
based on Approved Approved PSL
Sugar 2.0 Approved
22 Sep 05

2002 2003 2004 2005

PSL/SVA PSL clarifications

alignment and enhancements

IEEE 1850 PSL: Overview and Status 17

 FDL '05

IEEE 1850 PSL: Overview and Status 18

 FDL '05
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IEEE 1850
PSL Working Group

Issues Extensions LRM

Subcommittee Subcommittee Subcommittee

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IEEE 1850 PSL: Overview and Status 19

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IEEE 1850 PSL: Overview and Status 20

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IEEE 1850 PSL: Overview and Status 21

 FDL '05
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• Clock Context
– Clarification of clock context inheritance
– (New) Optional clock context parameter for built-in functions
• Prev/Stable/Rose/Fell
– Clarification of initial values
• Verification units
– Clarification of how vunits in any flavor can be used with any HDL
– Clarification of verification unit binding semantics
• Other Clarifications
– Simple Subset refinements
– HDL types of endpoints and built-in function results
– Clarification of forall 'replication' semantics

IEEE 1850 PSL: Overview and Status 22

 FDL '05

• Parameterized and/or operators

– generalization of the 'forall' operator (AND of parameterized properties)
– supports both conjunction and disjunction, for both properties and sequences
• Endpoints
– new built-in function 'ended()'
– equivalent to endpoint ended(sequence r) = {r};
• Nondeterminism support
– new built-in nondet() and nondet_vector() functions
– provide more general non-determinism capabilities
• Synchronous Abort
– New operators for explicit synch or asynch abort
• Typed Parameters
– provide ability to use HDL data types for property/sequence parameters
• SystemC flavor of PSL
– extends the language to integrate well with SystemC syntax

IEEE 1850 PSL: Overview and Status 23

 FDL '05

IEEE 1850 PSL: Overview and Status 24

 FDL '05
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IEEE 1850 PSL: Overview and Status 26

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IEEE 1850 PSL: Overview and Status 27

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IEEE 1850 PSL: Overview and Status 28

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IEEE 1850 PSL: Overview and Status 29

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IEEE 1850 PSL: Overview and Status 30
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IEEE 1850 PSL: Overview and Status 31

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IEEE 1850 PSL: Overview and Status 32

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IEEE 1850 PSL: Overview and Status 33

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IEEE 1850 PSL: Overview and Status 34

 FDL '05

IEEE 1850 PSL: Overview and Status 35

 FDL '05

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IEEE 1850 PSL: Overview and Status 36

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