The following simulation is an excerpt from thesis:

REVIEW OF SOLID STATE TRANSFORMERS WITH SIMULATION OF AN

IMPLEMENTATION BASED ON CASCADED H-BRIDGE CONVERTERS
Authored by Ayush Sagar (ayush@ieee.org), Shiveesh Fotedar, Sumit Joshi

5.

THE CASCADED H-BRIDGE CONVERTER BRIDGE BASED SST

Figure 5-1

The proposed 20kVA cascaded H-Bridge multilevel converter based solid state
transformer directly interfaces with 12kV distribution voltage level. The solid state
transformer consists of a cascaded multilevel AC/DC rectifier, Dual Active Bridge (DAB)
converters with high frequency transformers and a DC/AC inverter.
The Solid State Transformer (SST) is the interface device between the distribution
system and the electricity consumers in future smart grid systems. In the electric configuration
of the smart grid system shown in Figure 1.12, low voltage (120V), residential class
Distributed Renewable Energy Resource (DRER), Distributed Energy Storage Device
(DESD), and loads are connected to the distribution bus (12kV) through a solid state
transformer. The solid state transformer is used to enable active management of DRER,
DESD and loads, rather than a 60Hz conventional transformer.
The SST has the features of instantaneous voltage regulation, voltage sag compensation,
fault, isolation, power factor correction, harmonic isolation, dc output.
The SST has a 400V DC port that will facilitate more efficient connection of certain classes of
DRERs and DESDs. Acting very much like an energy router, each SST has bi-directional

26

energy flow control capability allowing it to control active and reactive power flow and to
manage the fault currents on both the low voltage and high voltage sides. Its large control
bandwidth provides the plug-and-play feature for distributed resources to rapidly identify and
respond to changes in the system.
With incorporation of the solid-state technology into the distribution transformer, many new
features can be realized through power electronics control and dc bus energy storage [44]
[45].
1) Voltage sag compensation: When the input source voltage drops for a short period, the
SST can compensate for the deficit and maintain constant output voltage. The total
period of compensation, as a function of the amount of energy storage, can be adapted to
the specific need of the customer.
2) Outage compensation: Similar to voltage sag compensation, the SST can provide full
voltage compensation for the period needed by the built-in energy storage.
3) Instantaneous voltage regulation: If the input source voltage fluctuates due to
power system transient or other load effects, the SST will maintain constant output
voltage because it has the energy buffer.
4) Fault isolation: The SST can act as a circuit breaker to isolate the power grid from load
fault and vice versa.
5) Power factor correction (and reactive power compensation): The SST can
maintain a unity power factor within its power rating. The SST can also generate or
absorb reactive power as required by the system.
6) Harmonic isolation: Nonlinear loads produce harmonic-distorted current that tends to
propagate back to the primary side of the transformer. The SST will maintain a clean
input current with a unity power factor.
7) DC output: In addition to the 120/240V AC voltage, the SST has 400V DC output,
which allows easier connection to distributed energies.
8) Metering or advanced distribution automation: The SST has advanced monitoring
capabilities including instantaneous voltage, current, power factor, harmonic
percentage, kWh and fault current or voltage information as well.
9) Environmental benefit: Unlike the conventional liquid immersed transformer, the
solid state transformer is an oil-free transformer and friendly to environment.

27

6.
6.1

SIMULATION

Circuit Simulation

Circuit simulation was performed using National Instruments Multisim 12.0. The simulated
design is rated 10KVA with 40A IGBT switches. All components used are easily available
and the circuit can be built by hobbyist methods.
6.1.1

Simulation parameters:

For a complex power electronics design like this the standard SPICE settings leads to slow
response and convergence errors. The following settings were used:

Integration method (in transient tab) was chosen to be Gear.

6.1.2

System configuration:

Microsoft Windows 7 64-bit

8 GB Ram

Intel Core i5 2520M

28

6.1.3

Schematics: Main

A hierarchal design methodology is used manage complexity. This is a multilevel design in

which each circuit is represented by a box with its terminals.
The main page contains shows the overall system and also has tools for control and
measurements connected to various blocks through on-page connectors.
The four blocks on the top are the H-bridges. The left-most block is operated as the Primary
side rectifier (1 phase, phase controlled). The 2nd from the left operates as the primary
inverter (1 phase SPWM, 1kHz, 31kHz carrier). The third one is a controlled secondary side
rectifier and here the phase control is necessary to achieve tight voltage regulation. The last
one from the left is the secondary side inverter (1 phase SPWM, 50Hz, 31kHz carrier) and
gives an output of with frequency and phase matching that of the output (or a reference
signal).
To achieve a 1:1 ratio of the overall transformer the transformer ratio of the magnetic
transformer in between was arbitrarily chosen to be 1:2. By using phase control at the
secondary rectifier side, this can be regulated to give out the same Vrms as the input side.
Below the H-Bridges are H-Bridge drivers with provide necessary isolation and driving pulse

29

to the switches and enables the switches to be operated by 5V digital TTL signals.
Like an ordinary transformer, two way power flow can be achieved by simply interchanging
the operating modes of the bridges across the transformer.
For the purpose of simulation a linear transformer is being used, having 100uH leakage
inductance.
6.1.4 Schematics: H-Bridge

H-bridges have identical construction but operating in different ways.

International Rectifier IR4PC40UD2 IGBTs are being used. They feature high speed
switching and internal feedback diodes (not shown in symbol).
6.1.5 Schematics: Bridge Driver
Consider the same bridge circuit:

30

An IGBT is switched on by applying gate pulse Vge on the gate terminal with respect to
emitter. Since the emitters are at 3 different reference levels, isolation is required. This is
provided by bridge driver blocks

The bridge driver contains a Totem-pole driver and Schmitt trigger and an opto-coupler for
each IGBT.

A totem pole driver is a pair of complementary transistors connected in push-pull

31

configuration for driving MOSFETS and IGBTs. It charges and discharges the gate
capacitance of the switch for turning it on or off.

The response of an opto-coupler is slow and noisy at high speeds and therefore a Schmitt
trigger must be used. Also note that 3 isolated 12V DC supplies are used for each bridge.
6.1.6

Schemtics: The Controller

Bridge driver forms an abstraction for the controller such that the transistors can be driven by
TTL 5V signals. The controller has been realized using Opamps and gates for simplicity.

32

There are four controller: two for the primary and secondary rectifiers (at left) and the other
two for the primary and secondary inverters (at right).
6.1.7

Control algorithm: Phase Controlled Rectifiers

A feedback of the AC power to be rectifier is taken from a step down transformer. This
feedback is taken from the input AC supply of the rectifier so that the controller operation is
33

perfectly in sync with the input AC power. A bridge rectifier is then used to convert the sine
wave into pulsed DC

The circuit above converts each sinusoidal pulse into squarewave (not shown) and then into a
sawtooth wave.

This sawtooth wave is compared against a DC reference voltage called Ralpha that
corresponds to a phase angle alpha. 0V Ralpha corresponds to 0 deg phase angle and 5V
Ralpha corresponds to 180 deg phase angle.

34

So if the sawtooth pulse is greater in amplitude than Ralpha at any instant an on-pulse is
generated from the output of the comparator.

Depending on the polarity of the original input AC appropriate IGBT pair is switched on. The
polarity detection is done using a polarity detection circuit which basically consists of a
comparator that compares input AC against a mid-potential made by a resistive voltage
divider between the two lines.
6.1.8

Simulation Results for rectifiers

For Ralpha = 0/5 V and 10 ohm load at output we see the following results:

35

For Ralpha = 1.5/5 V, 10 ohm load:

Ralpha = 3.5/5 V, 10 ohm load:

Ralpha = 3/5 V, 150uF filter, 60 ohm load

36

6.1.9

Control algorithm: SPWM Inverter

The SPWM inverter chosen because of its high frequency harmonics that can be filtered by
lower values of capacitance and inductance. The efficiency of SPWM inverters is also higher
than many other inverter topologies.

37

This also requires a sine wave reference for its operation. This reference usually comes from
an internal source for primary inverter and from external source for secondary inverter. For
secondary inverter it is derived externally in order to synchronize it with either the input AC
power or the grid it might be connected to. So this also acts as a Grid Tied Inverter (GTI).

The important parts of the SPWM controller are:

1) TriWaveGen: A high-frequency triangle wave generator - 31kHz chosen
2) SPWMGen: A comparator with polarity dependent switching logic at output

38

3) Rectifier that converts AC to pulsed DC

The control algorithm is straightforward:

The pulsed DC (red) derived from AC sine wave is compared against triangle wave
(green)

If amplitude of pulsed DC > triangle wave and On Pulse (blue) is generated

Depending on the polarity of the feedback AC appropriate IGBT pairs are turned on.

6.1.10 Simulation Results: Inverter

Output when 340V DC source is used.
31kHz carrier frequency; 1kHz output sine wave frequency; No load

39

31kHz carrier frequency; 1kHz output sine wave frequency; 10 load; 100uH filter

6.1.11 Conclusion
Circuit simulation is computationally expensive. Although each unit has been successfully
simulated independently we are unable to simulate the whole system as it takes around 15-20
minutes to complete 1ms of transient simulation and it could take at least a few seconds for
the system to stabilize and deliver an output. However, the unit wise simulation confirms that
the circuit is operational.
This circuit design we have developed allows one to build their own working prototypes and
to optimize their design.
To perform system level simulation a model based simulation approach will be used.

40

6.2 System Simulation

The circuit simulation is computationally expensive and therefore a discreet unit wise
simulation was done in NI Multisim . Therefore we again simulated the circuit in MATLAB
SIMULINK . The advantage with this software is that we are able to assign various functions
to blocks . When simulation is done , Matlab does not consider the non linarites of the
devices of the system but rather concludes the calculation approximating it around the vales
and behavior set for the particular block . This greatly reduces the simulation time and and
also drops the computational load .
6.2.1 Simulation Parameters
For the solid state transformer system level design the standard powergui configuration
settings leads to slow response and convergence errors. The following settings were used:

41

6.2.2 Simulink Model

This is the equivalent Simulink model of the circuit previously simulated. Built in system
blocks in simPower Systems have been used . For the simulation of the rectifier/ inverter ,
universal bridge is used with IGBT/Diodes as the switching elements .For the firing circuits
Discrete PWM generators are placed in the system . For transformation linear transformer is
used with the N1:N2 ratio of 1:2 .The ratio is set so as to compensate the switching loss. In
order to smoothen the waveforms filters have been used after every stage. Values for these
filters have been assigned arbitrarily.

42

6.2.3 Waveforms: Primary

The above waveform shows the output waveform of the primary side rectifier for the input of
50Hz ac supply . This is the output of the first stage of rectification where a a sine wave is
converted to pure dc. The switching is done by using the phase controlled rectification
technique

The above waveform shows the output waveform of the primary side inverter for the input of

43

rippled dc supply .The output is the pulse width modulation inversion of the dc with
frequency in the order of 1KHz having very little distortions. By using the Sinosidal pulse
width modulation technique we are able to get the desired output of high frequency .The
carrier frequency is kept at 31000 Hz with the modulation index of 5e-6 .The Discreate PWM
generator has an interactive GUI in which one can prompt it to generate the reference signal
on its own .
6.2.4 Waveforms: Secondary

The above waveform shows the output waveform of the secondary side rectifier for the input
of 1KHz ac supply. The input is taken from the secondary of the linear transformer which
provides the input of 1 kHz ac supply. For reducing the frequency we again have to rectify it
, and the same mode is used as used in primary .Appropriate changes have been made in the
firing circuit to make the rectifier give a stable response to such a high frequency input

44

The above waveform shows the output waveform of the secondary side inverter for the input
of rippled dc supply .The output is the pulse width modulation inversion of the dc with
frequency in the order of 50Hz having very little distortions. This is the final output of the
system is used against the RL load for demonstration.
6.2.5 Conclusion
After performing the system level simulation in MATLAB SIMULINK it can be inferred that
the solid state transformer systems response is stable and is operational at system level as
well .The computation load is lighter therefore system response can be analyzed quickly
compared to PSPICE simulation .

45

10

11

12

13

14

B1OUT1

IN1
AC1

B2IN1

DC_E

B2OUT1
DC_C

TOUT1

B3IN1

B3OUT1

AC1

AC1

B4IN1

OUT1

DC_E

DC_C

AC1

IN2

OUT2
AC2

DC_C

DC_E

B1OUT2

AC2

B2IN2

1:1.5

B2OUT2

AC2

TOUT2

DC_C

DC_E

B3IN2

B3OUT2

AC2

B4IN2

AU
BU
AL
BL

AU
BU
AL
BL

AU
BU
AL
BL

AU
BU
AL
BL

Bridge_Control_Bus

Bridge_Control_Bus

Bridge_Control_Bus

OUT2
OUT1L

B4IN2
B4IN1

B3OUT2
B3OUT1

B3IN2
B3IN1

250 Vrms
1kHz
0

R2Alpha+
R2Alpha-

SRecRefP
SRecRefN

B2OUT2
B2OUT1

B3IN1
B3IN2
IN1
IN2

R1A+
R1AR2A+
R2A-

B2IN2
B2IN1

R1Alpha+
R1Alpha-

PInvRef1
PInvRef2

B1OUT2
B1OUT1

PRecRefP
PRecRefN

IN2
IN1

IN1
IN2

F
+

_
A

SInvRef1
SInvRef2

_
A

_
A

_
B

+
Ext Trig

+
Ext Trig

+
Ext Trig

+
Ext Trig

B2IN2

B2OUT2

TOUT2

B3IN2

B3OUT2

340 V
B4_Aux
B4IN2

Ext Trig
+

B1OUT2

6.25
Load

10mF

OUT1L
R1A+

15F

B1OUT2

R2A+

100mH

OUT1

Key = Space

IN2

250 Vrms
1kHz
0
B3_Aux

B4IN1

B3OUT1
OUT1L

TOUT1
TOUT2

Key = L

B3OUT2
I

6.25
Load

Northern India Engineering College

Key = A

Key = R
6.25
Load

340 V
B2_Aux

B3OUT1

Key = A

Key = R
6.25
Load

6.25
Load

B3IN1

Key = R

TOUT1

Key = 4

B2OUT1

Key = R

B2IN1

Key = 3

B1OUT1

Key = 2

250 Vrms
50 Hz
0
Source
IN1

Key = R

External Control, Debugging and Measurements

B1OUT1

Key = Space

B2IN1
B2IN2

R1A1V

New Delhi, IN

R2A-

Title:

1V

Designed by: Ayush Sagar

Sheet title: Main

Checked by:

Date: 5/16/2013

Sold State Transformer using H-bridge converters

Desc.: B.Tech Thesis

J

OUT2

Prof K S Yadav

Sheet
0

10

11

12

13

of 58
14

DC_E
A

THB1

AL-

THB6

AL+

THB3

THB5

THB2

BU+

THB7

BL-

THB4

BL+

_
_

AC2

11k

IRGPC40UD2

AC1

THB5
THB1
THB5
THB2
B

22k

Ext Trig
+

AU+

AU-_BU-

Ext Trig
+

THB7
THB4
THB6
THB3

DC_C

IGBT USED:
Package
Circuit
Switching
Switching Speed
VCES (V)
IC @ 25C (A)
IC @ 100C (A)
VCE(ON)@25C typ (V)
VCE(ON)@25C max (V)
Ets typ (mJ)
Ets max (mJ)
Qrr typ nC 25C
Qrr max nC 25C
Vf typ
PD @25C (W)

IRG40PCUD2
TO-247
Co-Pack
Hard
8-30 kHz
600
40
20
1.72
2.10
1.1
1.5
80
180
1.30
160

AL+

BL+

AU+

BU+

TotemPole

TotemPole

TotemPole

AL-

TotemPole

BL-

AU-_BU-

12 V

12 V

12 V

5V

NOT

NOT

430

4.7k

TIL193

TIL193

NOT

NOT

430
BL

BC547C

430
AL

BC547C

BC547C

TIL193

430

4.7k

4.7k

TIL193

1.0k
7.5k

7.5k

7.5k

4.7k
BC547C

1.0k

1.0k

7.5k

1.0k

AU
5

BU
7

DC_E
A

THB1

AL-

THB6

AL+

THB3

THB5

THB2

BU+

THB7

BL-

THB4

BL+

_
_

AC2

11k

IRGPC40UD2

AC1

THB5
THB1
THB5
THB2
B

22k

Ext Trig
+

AU+

AU-_BU-

Ext Trig
+

THB7
THB4
THB6
THB3

DC_C

IGBT USED:
Package
Circuit
Switching
Switching Speed
VCES (V)
IC @ 25C (A)
IC @ 100C (A)
VCE(ON)@25C typ (V)
VCE(ON)@25C max (V)
Ets typ (mJ)
Ets max (mJ)
Qrr typ nC 25C
Qrr max nC 25C
Vf typ
PD @25C (W)

IRG40PCUD2
TO-247
Co-Pack
Hard
8-30 kHz
600
40
20
1.72
2.10
1.1
1.5
80
180
1.30
160

DC_E
A

THB1

AL-

THB6

AL+

THB3

THB5

THB2

BU+

THB7

BL-

THB4

BL+

_
_

AC2

11k

IRGPC40UD2

AC1

THB5
THB1
THB5
THB2
B

22k

Ext Trig
+

AU+

AU-_BU-

Ext Trig
+

THB7
THB4
THB6
THB3

DC_C

IGBT USED:
Package
Circuit
Switching
Switching Speed
VCES (V)
IC @ 25C (A)
IC @ 100C (A)
VCE(ON)@25C typ (V)
VCE(ON)@25C max (V)
Ets typ (mJ)
Ets max (mJ)
Qrr typ nC 25C
Qrr max nC 25C
Vf typ
PD @25C (W)

IRG40PCUD2
TO-247
Co-Pack
Hard
8-30 kHz
600
40
20
1.72
2.10
1.1
1.5
80
180
1.30
160

DC_E
A

THB1

AL-

THB6

AL+

THB3

THB5

THB2

BU+

THB7

BL-

THB4

BL+

_
_

AC2

11k

IRGPC40UD2

AC1

THB5
THB1
THB5
THB2
B

22k

Ext Trig
+

AU+

AU-_BU-

Ext Trig
+

THB7
THB4
THB6
THB3

DC_C

IGBT USED:
Package
Circuit
Switching
Switching Speed
VCES (V)
IC @ 25C (A)
IC @ 100C (A)
VCE(ON)@25C typ (V)
VCE(ON)@25C max (V)
Ets typ (mJ)
Ets max (mJ)
Qrr typ nC 25C
Qrr max nC 25C
Vf typ
PD @25C (W)

IRG40PCUD2
TO-247
Co-Pack
Hard
8-30 kHz
600
40
20
1.72
2.10
1.1
1.5
80
180
1.30
160

AL+

BL+

AU+

BU+

TotemPole

TotemPole

TotemPole

AL-

TotemPole

BL-

AU-_BU-

12 V

12 V

12 V

5V

NOT

NOT

430

4.7k

TIL193

TIL193

NOT

NOT

430
BL

BC547C

430
AL

BC547C

BC547C

TIL193

430

4.7k

4.7k

TIL193

1.0k
7.5k

7.5k

7.5k

4.7k
BC547C

1.0k

1.0k

7.5k

1.0k

AU
5

BU
7

AL+

BL+

AU+

BU+

TotemPole

TotemPole

TotemPole

AL-

TotemPole

BL-

AU-_BU-

12 V

12 V

12 V

5V

NOT

NOT

430

4.7k

TIL193

TIL193

NOT

NOT

430
BL

BC547C

430
AL

BC547C

BC547C

TIL193

430

4.7k

4.7k

TIL193

1.0k
7.5k

7.5k

7.5k

4.7k
BC547C

1.0k

1.0k

7.5k

1.0k

AU
5

BU
7

AL+

BL+

AU+

BU+

TotemPole

TotemPole

TotemPole

AL-

TotemPole

BL-

AU-_BU-

12 V

12 V

12 V

5V

NOT

NOT

430

4.7k

TIL193

TIL193

NOT

NOT

430
BL

BC547C

430
AL

BC547C

BC547C

TIL193

430

4.7k

4.7k

TIL193

1.0k
7.5k

7.5k

7.5k

4.7k
BC547C

1.0k

1.0k

7.5k

1.0k

AU
5

BU
7

PRAU

PRBL

SRAU

SRBL

C
D

PRBU

R2CTP1
R2CTP2
R2CTP3
R2CTP4

C
T

PRAL

SRAL

PIAU

R1CTP1
R1CTP2
R1CTP3
R1CTP4

PIBU

SRBU

TriWaveGen

PIAL
SPWMGen

PIBL

Rectifier
PInvRef1

R2CTP3

R1CTP3

PInvRef2
1:75

R1CTP4

R2CTP4

R1Alpha+

R2Alpha+

SIAU
R1Alpha-

R2AlphaSIBU
TriWaveGen

Rectifier

SIAL
SPWMGen

47nF

1.0F

R2CTP2

R1CTP2

SIBL

Rectifier
SInvRef1

Rectifier

R2CTP1

R1CTP1
PRecRefP
40:1
0

1:75

SRecRefP

PRecRefN
2

SInvRef2

40:1
3

SRecRefN
4

Vs+

A
Ext Trig
+
_
B

A
+

100

TTP1

TTP2

TTP3

TTP1

TTP2
BD139

IN

OUT
0.47

BD140

TTP3

VsE

Vs+

A
Ext Trig
+
_
B

A
+

100

TTP1

TTP2

TTP3

TTP1

TTP2
BD139

IN

OUT
0.47

BD140

TTP3

VsE

Vs+

A
Ext Trig
+
_
B

A
+

100

TTP1

TTP2

TTP3

TTP1

TTP2
BD139

IN

OUT
0.47

BD140

TTP3

VsE

Vs+

A
Ext Trig
+
_
B

A
+

100

TTP1

TTP2

TTP3

TTP1

TTP2
BD139

IN

OUT
0.47

BD140

TTP3

VsE

A
Ext Trig
+

Vs+

_
B

A
_

TST1

TST2

1k
TST3

BC559AP
OUT

390k
TST1
IN
D

TST2

4.7k

BC549BP
4.7k
10k
TST3

Vs-

A
Ext Trig
+

Vs+

_
B

A
_

TST1

TST2

1k
TST3

BC559AP
OUT

390k
TST1
IN
D

TST2

4.7k

BC549BP
4.7k
10k
TST3

Vs-

A
Ext Trig
+

Vs+

_
B

A
_

TST1

TST2

1k
TST3

BC559AP
OUT

390k
TST1
IN
D

TST2

4.7k

BC549BP
4.7k
10k
TST3

Vs-

A
Ext Trig
+

Vs+

_
B

A
_

TST1

TST2

1k
TST3

BC559AP
OUT

390k
TST1
IN
D

TST2

4.7k

BC549BP
4.7k
10k
TST3

Vs-

Vs+

A
Ext Trig
+
_
B

A
+

100

TTP1

TTP2

TTP3

TTP1

TTP2
BD139

IN

OUT
0.47

BD140

TTP3

VsE

Vs+

A
Ext Trig
+
_
B

A
+

100

TTP1

TTP2

TTP3

TTP1

TTP2
BD139

IN

OUT
0.47

BD140

TTP3

VsE

Vs+

A
Ext Trig
+
_
B

A
+

100

TTP1

TTP2

TTP3

TTP1

TTP2
BD139

IN

OUT
0.47

BD140

TTP3

VsE

Vs+

A
Ext Trig
+
_
B

A
+

100

TTP1

TTP2

TTP3

TTP1

TTP2
BD139

IN

OUT
0.47

BD140

TTP3

VsE

A
Ext Trig
+

Vs+

_
B

A
_

TST1

TST2

1k
TST3

BC559AP
OUT

390k
TST1
IN
D

TST2

4.7k

BC549BP
4.7k
10k
TST3

Vs-

A
Ext Trig
+

Vs+

_
B

A
_

TST1

TST2

1k
TST3

BC559AP
OUT

390k
TST1
IN
D

TST2

4.7k

BC549BP
4.7k
10k
TST3

Vs-

A
Ext Trig
+

Vs+

_
B

A
_

TST1

TST2

1k
TST3

BC559AP
OUT

390k
TST1
IN
D

TST2

4.7k

BC549BP
4.7k
10k
TST3

Vs-

A
Ext Trig
+

Vs+

_
B

A
_

TST1

TST2

1k
TST3

BC559AP
OUT

390k
TST1
IN
D

TST2

4.7k

BC549BP
4.7k
10k
TST3

Vs-

Vs+

A
Ext Trig
+
_
B

A
+

100

TTP1

TTP2

TTP3

TTP1

TTP2
BD139

IN

OUT
0.47

BD140

TTP3

VsE

Vs+

A
Ext Trig
+
_
B

A
+

100

TTP1

TTP2

TTP3

TTP1

TTP2
BD139

IN

OUT
0.47

BD140

TTP3

VsE

Vs+

A
Ext Trig
+
_
B

A
+

100

TTP1

TTP2

TTP3

TTP1

TTP2
BD139

IN

OUT
0.47

BD140

TTP3

VsE

Vs+

A
Ext Trig
+
_
B

A
+

100

TTP1

TTP2

TTP3

TTP1

TTP2
BD139

IN

OUT
0.47

BD140

TTP3

VsE

A
Ext Trig
+

Vs+

_
B

A
_

TST1

TST2

1k
TST3

BC559AP
OUT

390k
TST1
IN
D

TST2

4.7k

BC549BP
4.7k
10k
TST3

Vs-

A
Ext Trig
+

Vs+

_
B

A
_

TST1

TST2

1k
TST3

BC559AP
OUT

390k
TST1
IN
D

TST2

4.7k

BC549BP
4.7k
10k
TST3

Vs-

A
Ext Trig
+

Vs+

_
B

A
_

TST1

TST2

1k
TST3

BC559AP
OUT

390k
TST1
IN
D

TST2

4.7k

BC549BP
4.7k
10k
TST3

Vs-

A
Ext Trig
+

Vs+

_
B

A
_

TST1

TST2

1k
TST3

BC559AP
OUT

390k
TST1
IN
D

TST2

4.7k

BC549BP
4.7k
10k
TST3

Vs-

Vs+

A
Ext Trig
+
_
B

A
+

100

TTP1

TTP2

TTP3

TTP1

TTP2
BD139

IN

OUT
0.47

BD140

TTP3

VsE

Vs+

A
Ext Trig
+
_
B

A
+

100

TTP1

TTP2

TTP3

TTP1

TTP2
BD139

IN

OUT
0.47

BD140

TTP3

VsE

Vs+

A
Ext Trig
+
_
B

A
+

100

TTP1

TTP2

TTP3

TTP1

TTP2
BD139

IN

OUT
0.47

BD140

TTP3

VsE

Vs+

A
Ext Trig
+
_
B

A
+

100

TTP1

TTP2

TTP3

TTP1

TTP2
BD139

IN

OUT
0.47

BD140

TTP3

VsE

A
Ext Trig
+

Vs+

_
B

A
_

TST1

TST2

1k
TST3

BC559AP
OUT

390k
TST1
IN
D

TST2

4.7k

BC549BP
4.7k
10k
TST3

Vs-

A
Ext Trig
+

Vs+

_
B

A
_

TST1

TST2

1k
TST3

BC559AP
OUT

390k
TST1
IN
D

TST2

4.7k

BC549BP
4.7k
10k
TST3

Vs-

A
Ext Trig
+

Vs+

_
B

A
_

TST1

TST2

1k
TST3

BC559AP
OUT

390k
TST1
IN
D

TST2

4.7k

BC549BP
4.7k
10k
TST3

Vs-

A
Ext Trig
+

Vs+

_
B

A
_

TST1

TST2

1k
TST3

BC559AP
OUT

390k
TST1
IN
D

TST2

4.7k

BC549BP
4.7k
10k
TST3

Vs-

923

100k

0.1F

47k

5V

150

OUT
1k

-5V

AU
A

BU

AL

BL
A

G
T
A

TSP3
TSP2
TSP1

5V

TSP3
AC_+ve

VSin
VTri

TSP1

TSP2

-5V

47k

4.7k

1.0k

5V
33k

5V
5V
OUT

1k
C

IN

10k

-5V
D

Tcap1

Tcap2

-5V
5V
10k

2N7000

5V

1.0k
F

IS_+VE

1.0k
B

1.0k
C

N
5V

OUT+

IN2
100k

IN1
OUT-

5V

Ramp
OUT
VRef
C

IS_+VE

1.0k
B

1.0k
C

N
5V

5V
33k

5V
5V
OUT

1k
C

IN

10k

-5V
D

Tcap1

Tcap2

-5V
5V
10k

2N7000

5V

1.0k
F

IS_+VE

1.0k
B

1.0k
C

N
5V

OUT+

IN2
100k

IN1
OUT-

5V

Ramp
OUT
VRef
C

OUT+

IN2
100k

IN1
OUT-

923

100k

0.1F

47k

5V

150

OUT
1k

-5V

AU
A

BU

AL

BL
A

G
T
A

TSP3
TSP2
TSP1

5V

TSP3
AC_+ve

VSin
VTri

TSP1

TSP2

-5V

47k

4.7k

1.0k

IS_+VE

1.0k
B

1.0k
C

N
5V

OUT+

IN2
100k

IN1
OUT-