International Journal of Scientific Research Engineering & Technology (IJSRET), ISSN 2278 0882

Volume 4, Issue 5, May 2015

Analysis and Design of Low-Power Digital Comparator

S.P.Vasumathi1, Mallapu Mohan2, Venati Dinesh Kumar3, P.dass4
1,2,3

UG Student, Department of Electronic and Communication, Saveetha School of Engineering ,Chennai

Assistant Professor, Department of Electronic and Communication, Saveetha School of Engineering, Chennai

ABSTRACT
Design and analysis of Low-power, span effectual and
elevated speed analog-to-digital converters are shoving
in the direction of the use of vibrant comparators, that is
utilized to maximize speed and manipulation efficiency.
In the continuing design, analysis on the stay of the
vibrant comparators will be gave and analytical
expressions are derived. From the analytical expressions,
designers can attain an intuition concerning the main
contributors to the comparator stay and fully discover
the tradeoffs in vibrant comparator design. Instituted on
the gave analysis, a new vibrant comparator is
counseled, whereas the route of a standard double tail
comparator is adjusted for low-power and fast procedure
even in tiny supply voltages. Lacking perplexing the
design and by adding insufficient transistors, the
affirmative feedback across the regeneration is
reinforced, that aftermath in remarkably decreased stay
time. Post-layout simulation aftermath in a 0.18-m
CMOS knowledge confirm the analysis results. It is
shown that in the counseled vibrant comparator both the
manipulation consumption and stay period are
considerably reduced. The maximum timepiece
frequency of the counseled comparator can be increased
to 2.5 and 1.1 GHz at supply voltages of 1.2 and 0.6 V,
as consuming 1.4 mW and 153 W, respectively. The
average deviation of the input-referred offset is 7.8 mV
at 1.2 V supply.
Keywords - Auto tunable, Comparator, Double tail
comparator

I.

INTRODUCTION

In electronics, a comparator is a mechanism that assesses

two voltages or currents and outputs a digital gesture
indicating that is larger. It has two analog input terminals
and one binary digital output . The output is ideally
A comparator consists of a enumerated high-gain
differential amplifier. They are usually utilized in
mechanisms that compute and digitize analog signals,
such as analog-to-digital converters (ADCs), as well as
relaxation oscillators.
The differential voltages have to stay inside
the limits enumerated by the manufacturer. Main

consolidated comparators, like the LM111 relations, and

precise high-speed comparators like the LM119
relations, need differential voltage scopes considerably
lower than the manipulation supply voltages (15 V vs.
36 V). Rail-to-rail comparators permit each differential
voltage inside the manipulation supply range. After ran
from a bipolar (dual rail) supply or, after ran from a
unipolar TTL/CMOS manipulation supply:
Specific rail-to-rail comparators alongside pn-p input transistors, like the LM139 relations, permit
input possible to drop 0.3 volts below the negative
supply rail, but do not permit it to development above
the affirmative rail. Specific ultra-fast comparators, like
the LMH7322, permit input gesture to swing below the
negative rail and above the affirmative rail, even though
by a slim margin of merely 0.2 Differential input voltage
(the voltage amid two inputs) of a present rail-to-rail
comparator is normally manipulated merely by the
maximum swing of manipulation supply.

II.

BLOCK DIAGRAM DESCRIPTION

Early from the timepiece dynamo we are producing

timepiece signals and providing it to disparate modules.
Next in the Double tail comparator portion, it assesses
the reference input and the output from reference
generator. The figure(1) shows the block diagram of the
proposed system
One more portion, auto tunable threshold
comparator we are employing the tunable threshold
benefits and the alike contrasting procedure is gave here.
These two portions (double tail and auto tunable
threshold comparator) outputs are contrasted in the
comparator block.
Here it assesses both outputs and its
efficiency and supplementary factors like kick-back
sound and mismatch. So by employing auto tunable
threshold we accomplish good efficiency and tolerance.
And this comparator output is the final
output. The manipulation supply is nothing but the
supply given to the whole route, arrangement timepiece
is the input timepiece pulses given and hardware reset is
the early reset condition for the commencing of the
hardware.

www.ijsret.org

518

International Journal of Scientific Research Engineering & Technology (IJSRET), ISSN 2278 0882
Volume 4, Issue 5, May 2015

by the period bypassing, the difference amid fn and fp

(Vfn/fp) increases in an exponential manner, managing
to the reduction of latch regeneration time.

FIGURE(1):BLOCK DIAGRAM OF PROPOSED

SYSTEM

III.

DOUBLE TAIL COMPARATOR

The procedure of the counseled comparator is as

follows (see Fig). Across reset period (CLK = 0, Mtail1
and Mtail2 are off, circumventing static power), M3 and
M4 pulls both fn and fp nodes to VDD, hence transistor
Mc1 and Mc2 are cut off. Intermediate period
transistors, MR1 and MR2, reset both latch outputs to
ground. Across decision-making period (CLK = VDD,
Mtail1, and Mtail2 are on), transistors M3 and M4 coil
off. The figure (2) shows the double tail comparator.
Furthermore, at the commencing of this
period, the manipulation transistors are yet off (since fn
and fp are concerning VDD). Thus, fn and fp onset to
drop alongside disparate rates according to the input
voltages. Presume VINP > VINN, therefore fn drops
faster than fp, (since M2 provides extra present than
M1). As long as fn endures plummeting, the
corresponding pMOS manipulation transistor (Mc1 in
this case) starts to coil on, pulling fp node back to the
VDD; so one more manipulation transistor (Mc2) stays
off, permitting fn to be emitted completely. In
supplementary words, unlike standard double-tail vibrant
comparator, in that Vfn/fp is just a purpose of input
transistor trans conductance and input voltage difference,
in the counseled construction as quickly as the
comparator detects that for instance node fn discharges
faster, a pMOS transistor (Mc1) turns on, pulling the
supplementary node fp back to the VDD. Consequently

FIGURE(2): DOUBLE TAIL COMPARATOR

Although the effectiveness of the counseled believed,
one of the points that ought to be believed is that in this
route, after one of the manipulation transistors (e.g.,
Mc1) turns on, a present from VDD is drawn to the earth
via input and tail transistor (e.g., Mc1, M1, and Mtail1),
emerging in static manipulation consumption. To
vanquish this subject, two nMOS switches are utilized
below the input transistors [Msw1 and Msw2 At the
commencing of the decision making period, due to the
fact that both fn and fp nodes have been pre-charged to
VDD (during the reset phase), both switches are closed
and fn and fp onset to drop alongside disparate emitting
rates.
As quickly as the comparator detects that one of the
fn/fp nodes is emitting faster, manipulation transistors
will deed in a method to raise their voltage difference.
Presume that fp is pulling up to the VDD and fn ought to
be emitted completely, hence the switch in the charging
trail of fp will be opened (in order to stop each present
drawn from VDD) but the supplementary switch related
to fn will be closed to permit the finished discharge of fn
node. In supplementary words, the procedure of the
manipulation transistors alongside the switches emulates
the procedure of the latch. The result for this double tail
comparator is shown in this figure(3)

www.ijsret.org

519

International Journal of Scientific Research Engineering & Technology (IJSRET), ISSN 2278 0882
Volume 4, Issue 5, May 2015

V.

In this project, we designed the double tail

comparator which consists of two tails. The clock pulse
is given via this tails. As per proposed system, we
designed auto tunable threshold comparator in which the
input voltage is given and tuned automatically. Thus by
giving different input voltages we analyze the output
nodes and transistors working. It internally consists of
two phases, reset and comparison both are designed.
The on and off condition depends on the input voltages
given. Also we designed the double tail comparator. The
outputs are analyzed and verified using Modelsim
Simulator.

FIGURE (3)

IV.

AUTO TUNABLE
COMPARATOR

CONCLUSION

DOUDLE

TAIL

REFERENCES

This auto tunable double tail comparator has the alike

procedure as that of the double tail comparator. The
input given to the proposed system are clock, reset ,clear
vinp,vinn,clk,mtail1,mtail2,vdd,gnd,m3,m4,mc1,mc2,mr
1,mr2 and the output given are fn and fp when the reset
phase all the transistor will be in off stage and when the
rising edge of clock and the clear function is in off stage
then the input voltage is tunable automatically like
(00,01,10,11) and the input voltage assigned to (00-4,013,10-2,11-1)and this changes the voltages in the fn and
fp.this rising change the following transistor value as
mtail1 and mtail2 will be in on stage m3 and m4 will be
in off stage .when the vinp>vinn it changes fn
accordingly like (4,3,2,1)and make the transistor mc1 in
on stage and fp in on stage but not auto tunable and mc2
will be in off stage . when vinp<vinn then the changes
occur only in fp and the voltage change as(4,3,2,1 ) and
makes the transistor mc2 in on stage and mc1 in off
stage and fn in on stage but not auto tunable. The figure
(4) shows the result of the proposed comparator

FIGURE(4)
www.ijsret.org

1. Sanjay Kumar Jaiswal,

Kumkum Verma,
Gyanendra Singh , Neeraj Pratihar Design of
CMOS 8-BIT Comparator for Low Power
Application2012
Fourth
International
Conference on Computational Intelligence and
Communication Networks
2. Samaneh Babayan-Mashhadi, Reza Lot
Analysis and Design of a Low-Voltage LowPower
Double-Tail
Comparator
IEEE
Transactions On Very Large Scale Integration
(Vlsi) Systems
3.

Xu bai, Michitaka kameyama low power

multi-valued source coupled logic circuits using
dual supply voltage reconfigurable VLSI 2013
IEEE 43rd International Symposium on
Multiple-Valued

520