SEQUENTIAL CIRCUITS

Sequential circuits are digital circuits in which the outputs depend not only on the current
inputs, but also on the previous state of the inputs.

Sequential circuits are basically combinational circuits with the additional property of memory
(to remember past inputs). The combinational part of the circuit receives two sets of input
signals: primary (coming from the circuit environment) and secondary (coming from the
memory). The particular combination of secondary input variables at a given time is called the
present state of the circuit; the secondary input variables are also known as state variables. If
there are m secondary input variables in a sequential circuit, then the circuit can be in anyone of
different present states.

The outputs of the combinational part of the circuit are divided into two sets.
-

Primary outputs - available to control operations in the circuit environment,

Secondary outputs - used to specify the next state to be assumed by the memory.

The number of secondary output variables, often called the excitation variables, depends on the
type of memory element used.

CLASSIFICATION OF SEQUENTIAL CIRCUITS

1- According to mode of operation, sequential logic circuits can be categorized into two
classes:
a). Synchronous or clocked sequential circuits - In synchronous circuits internal states
change at discrete instants of time under the control of a synchronizing pulse, called the
clock.

CLOCK: The clock is generally some form of square wave that works in tow states being, the
on-time defined as the time the wave is in the 1 state and the off-time defined as the time the
wave is in the 0 state.
-

The duty cycle is defined as:

STATE TRANSITIONS IN SYNCHRONOUS SEQUENTIAL CIRCUITS

State transitions in synchronous sequential circuits are made to take place at times when the
clock is making a transition from 0 to l or from 1 to 0.
-

The 0-to-1 transition is called the positive edge or the rising edge of the clock signal.

The 1-to-0 transition is called the negative edge or the falling edge of the clock signal

Note: Between successive clock pulses there is no change in the information stored in memory.
Synchronous sequential circuits are also known as.

b). Asynchronous sequential circuits - In asynchronous sequential circuits the transition

from one state to another is initiated by the change in the primary inputs; there is no external
synchronization.

Since state transitions do not have to occur at specific instants of time, asynchronous circuits can
operate at their own speed. The memory portion of asynchronous circuits is usually implemented
by feedback among logic gates. Thus asynchronous circuits can be regarded as combinational
circuits with feedback.

Because of the difference in the delays through various signal paths, such circuits can give rise to
transient conditions during the change of inputs or state variables. So, such circuits have to be
designed in a special way in order to ensure that their operations are not affected by transient
conditions.

2- According to the structure sequential circuits are divided in three types namely:
a. Moore sequential circuits In which the present outputs are a function of only the
previous inputs. In Moore model, the next state depends on the present state and the
inputs, but the output depends only on the present state.

Figure 1: Moore type sequential circuit

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b. Mealy sequential circuit where the present outputs are the function of both the
present and previous inputs. In mealy model, the output at any time depends on the
present state and the input. These also determine the next state.

Figure 2: Mealy type sequential circuit

c. Mixed type circuits These are circuits which have both Moore and Mealy type
outputs.

Figure 3: Mixed type sequential circuit

Categories of Sequential Circuits

The basic sequential circuit elements are divided into two categories which are:
I.

Level-Sensitive/Triggered (Latches) that are also subdivide in two:

-

High-level sensitive

Low-level sensitive

II.

Edge-Triggered (Flip-flops) again subdivided into three:

-

Rising (positive) edge triggered

Falling (negative) edge triggered

Dual-edge triggered

LATCHES
A latch is a logic circuit with two outputs, which are the complement of each other. A basic latch
can be constructed by cross coupling two NOR gates or NAND gates. The Set/Reset latch is the
most basic unit of sequential digital circuits. It has two inputs Set (S) and Reset (R) and two outputs Q
and Q. The two outputs must always be complementary, i.e. if Q is 0 then Q must be 1, and vice-versa.
The S input sets the Q output to logic 1. The R input resets the Q output to logic 0.
In NAND RS Latch when both inputs S and R are 0, both the outputs Q and Q are logic 1 which is
illegal because they violates the rule that Q and Q must always be complementary . But if they are both
1 the outputs become Undefined.

NAND RS Latch circuit diagram

NAND RS Latch circuit diagram

FUNCTION
Illegal
Set
Reset
Undefined

INPUTS
A
B
0
0
0
1
1
0
1
1

OUTPUTS

Q
1
1
0
0
1
U
U

Figure 4: RS NAND Latch logic circuit and its truth table.

The characteristic equation of a basic RS latch is given by:

which by applying de Morgans theorem becomes

. Hence the AND-gate basic RS Latch is an active low, meaning it is

triggered by applying logic 0 to the inputs.
In NOR RS Latch when both inputs S and R are 0, the outputs Q and Q become Undefined.
When they are both 1 the outputs Q and Q are logic 0 which is also illegal because they
violate the rule that Q and Q must always be complementary .

NOR RS Latch circuit diagram

NOR RS Latch truth table

FUNCTION
Undefined
Set
Reset
Illegal

INPUTS
A
B
0
0
1
0
0
1
1
1

OUTPUTS

Q
U
U
1
0
0
1
0
0

Figure 5: RS NOR Latch logic circuit and its truth table.

Note: The basic RS latch is the one that constitutes the basic memory cell for sequential circuits
and is used as the basic building block for latches and flip-flops by including a combinational
circuit.

The Gated Set/Reset (SR) Latch

To be able to control when the S and R inputs of the RS latch can be applied to the latch and thus
change the outputs, an extra input is used. This input is called the Enable. If the Enable is 0 then
the S and R inputs have no effect on the outputs of the SR latch. If the Enable is 1 then the Gated
SR latch behaves as a normal SR latch.
Gated RS Latch circuit diagram

Figure 6: The Gated RS Latch block diagram

This circuit consists of:
a) An input combinational circuit CC,
b) The basic memory RS-latch.
c) A set of primary inputs A,
d) An Enable (E) or Clock (CK) input (E/CK),
e) Feedbacks from the outputs Q and Q' to the combinational circuit CC.
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Truth table of RS latch

The RS (Transparent) Latch

Function
Hold
Hold
Set
Reset
Illegal

EN
0
1
1
1
1

Set
X
0
1
0
1

Reset
X
0
0
1
1

Q
Q
Q
1
0
1

0
1
1

Figure 7: The NAND RS Transparent Latch and its Truth table

RS (Transparent) Latch Timing diagram

Block diagram of RS latch

Figure 8: The NAND RS Transparent latch Timing diagram and the block diagram of RS latch
In the timing diagram, the SET condition is followed by an ILLEGAL (I) condition, a RACE (C)
condition and then a BAD INPUT SEQUENCE condition. The observations and conclusions
from the timing diagram are:
a) the outputs do not change when the ENABLE (E) is INACTIVE (in this case LOW) even if
the inputs change,
b) the outputs change when the ENABLE is ACTIVE (in this case HIGH),
c) if the inputs change when the ENABLE is ACTIVE, the outputs also change, and this
constitutes a BAD INPUT SEQUENCE,
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d) if both inputs are high when the ENABLE is high that constitutes an ILLEGAL INPUT
COMBINATION and that leads to an ILLEGAL OUTPUT condition because both outputs
attain logic 1,
e) if the ENABLE goes INACTIVE when there is an ILLEGAL condition, a RACE condition
occurs.

Requirements in designing RS latch

From these observations we can draw the requirements for the proper operation of the RS latch.
a) the inputs for a required output should be applied when the ENABLE is INACTIVE,
b) the inputs should remain stable and should not change when the ENABLE is ACTIVE,
c) an ILLEGAL INPUT COMBINATION should be avoided as this may lead to a RACE
condition.

The D-Latch
A problem with the SR latch is that the S and R inputs cannot be at logic 1 at the same time. To
ensure that this cannot happen, the S and R inputs can be connected through an inverter. In this
case the Q output is always the same as the input, and the latch is called the Data or D latch. The
D latch is used in Registers and memory devices.

Data/D-Latch circuit diagram

D-latch Truth table

Function
Hold
Hold
Set

EN
0
1
1

D
X
0
1

Q
Q
0
1

Figure 9: The D-Latch circuit diagram and its truth table

D-latch block diagram

Note: The D latch is devoid of ILLEGAL and RACE

conditions.
Generally, Latches are also called transparent or level
triggered flip flops, because the change on the outputs
will follow the changes of the inputs as long as the
Enable input is set.
Figure 10: Block diagram of a D-Latch