New Optimal Pulsewidth Modulation for Single

DC-Link Dual Inverter fed Open-end Stator

Winding Induction Motor Drives
Amarendra Edpuganti , Student Member IEEE, Akshay K. Rathore , Senior Member IEEE and
Joachim Holtz , Life Fellow IEEE
Department

of Electrical and Computer Engineering

National University of Singapore
117576 Singapore
Email: amarendra@nus.edu.sg; akshayrathore@nus.edu.sg
University of Wuppertal
42285 Wuppertal, Germany
Email:j.holtz@ieee.org

AbstractThe multilevel topologies of dual inverters feeding

an open-end stator winding induction motor has been introduced
around two decades ago. However, these topologies require
common-mode inductor in series with motor windings to suppress
zero-sequence or common-mode currents. In medium-voltage
high power drives, low device switching frequencies are preferred
to improve the overall efficiency of drive system. On the other
hand, low device switching frequencies leads to higher total
harmonic distortion (THD) of stator currents. Therefore, the
objective of our study was to propose a new optimal pulsewidth
modulation to eliminate zero-sequence currents and minimize
harmonic distortion of stator currents, while operating power
semiconductor devices at low device switching frequencies. The
main idea is to select switching patterns such that all zerosequence components are eliminated and then, perform optimization for every steady-state operating point to minimize the THD
of stator currents. The proposed modulation has been validated
on dual two-level and dual three-level inverters fed 1.5-kW openend stator winding Induction motor drive.

I. I NTRODUCTION
Multilevel converters (MLC) are now a mature and well established technology for medium-voltage (MV) high power applications [1][3]. The popular multilevel converter topologies
are neutral-point or diode-clamped converters (NPC), flyingcapacitor converters (FC) and cascaded H-Bridge converters
(CHB) [4]. The concept of dual two-level (D2L) inverter fed
open-end stator winding induction motor drive was introduced
by Stemmler and Guggenbach [5]. This topology requires
only half of the dc-link voltage and has no neutral-point
fluctuations compared to 3L-NPC topology. In addition, the
voltage amplitude required to produce the air-gap flux in the
machine gets divided among the two dc sources. Subsequently,
dual inverter topologies have been proposed to achieve fivelevel (5L), seven-level (7L) and nine-level (9L) multilevel
waveforms across stator windings [6][9]. The main drawback of these topologies are requirement of a common-mode

978-1-4799-5776-7/14/$31.00 2014 IEEE

inductor in series with stator windings to suppress the zerosequence or common-mode currents.
The energy efficiency in MV high power drives is improved
significantly by reducing the device switching frequencies,
which brings down the dominating switching losses. However,
total harmonic distortion (THD) of machine stator currents
increases at lower device switching frequencies. Also, it is
desirable to eliminate or minimize the zero-sequence current components in dual inverter fed induction motor drives.
Therefore, the challenge is to minimize or eliminate zerosequence current components as well as minimize THD of
machine stator currents, while operating MLCs at low device switching frequencies. In literature, several space vector
modulation (SVM) based techniques have been proposed to
eliminate zero-sequence currents as well as common-mode
voltages which leads to bearing and leakage currents [10]
[14]. However, all these modulation techniques require device
switching frequencies around 1 kHz and hence, not preferred
for MV high power applications.
Synchronous optimal pulsewidth modulation (SOP) is an
emerging control technique to operate MLCs at low device
switching frequencies with minimal harmonic distortion of
machine stator currents [15]. The SOP technique has been
demonstrated for dual 3-level (D3L) inverter fed open-end
stator winding induction motor drives with maximum device
switching frequencies limited to 200 Hz [16]. Later, this
SOP technique has been improved to minimize the zerosequence currents by using additional constraint (VoltSecT)
in the optimization [17]. However, requirement of commonmode inductor still remains and its kVA-rating depends on
the common-mode voltages at six-step operation. Therefore,
the objective of our study was to propose a new SOP technique to eliminate zero-sequence currents as well as minimize
harmonic distortion of stator currents, while operating power
semiconductor devices at low device switching frequencies.

3865

(a)
(a)

(b)

Fig. 2. Output potential waveforms of (a) 2L inverter (b) 3L-NPC inverter

(b)
Fig. 1. Single dc-link dual inverter fed open-end stator winding induction
motor drive. (a) D2L topology (b) D3L topology

The main idea is to impose a constraint on switching patterns

such that zero-sequence voltage components are eliminated
and then, perform optimization to determine switching patterns
that minimize the THD of stator currents.
The topologies of D2L and D3L inverters feeding an
open-end stator winding induction motor drive are shown in
Fig. 1(a)-(b), respectively. In case of D2L topology shown
in Fig. 1(a), two voltage levels (Vdc , 0) are obtained between mid-point of each leg and negative terminal of dclink capacitor O and thus three voltage levels (Vdc , 0, Vdc )
are obtained across each stator winding. Similarly, for D3L
topology shown in Fig. 1(b), each 3L-NPC leg generates
three voltage levels (Vdc , 0, Vdc ) with respect to neutralpoint of dc-link capacitors N and thus five voltage levels
(2Vdc , Vdc , 0, Vdc , 2Vdc ) are obtained across each stator
winding.
The rest of the contents are organized as follows: the details
of proposed SOP technique are presented in Section II, and the
experimental results are demonstrated in Section III to validate
the proposed technique.
II. N EW S YNCHRONOUS O PTIMAL P ULSEWIDTH
M ODULATION
SOP technique generates switching patterns by using offline optimization technique for ( fv ) control of induction motor
drive. The goal of optimization is to minimize the THD of
stator currents. The word synchronous refers to fact that
device switching frequency fs is always made an integer multiple of fundamental frequency of inverter output voltage f1 .
In low device switching frequency applications, synchronized
pulsewidth modulation (PWM) results in a small number of
switching instants and thus optimization based techniques are
suggested to pre-determine switching angles [18]. All even
order harmonic components are eliminated by using half-wave
and quarter-wave symmetry in the switching patterns. Then,

it is sufficient to consider total switching instants in a quarter

period known as pulse number N .
The goal of SOP technique is to operate D2L inverter and
D3L inverters with maximum device switching frequencies
fs,max limited to 400 Hz and 200 Hz, respectively. The
1
, where f1R denotes the
modulation index m is defined as ff1R
rated fundamental frequency of the induction motor drive (50
Hz). The steady-state operating points are denoted by (m, N ).
The first step in SOP would be to compute the pulse number
N for a given m such that fs is limited to fs,max . Then,
pulse patterns are selected such that zero-sequence voltages in
three-phase windings are eliminated and finally, optimization
is performed to determine switching angles that minimize the
THD of machine currents for each operating point (m, N ).
A. Computation of pulse number N
The phase output voltages of 2L and 3L-NPC inverters are
shown in Fig. 2(a)-(b) and their respective pulse numbers are
denoted as N2L and N3L , respectively. The pulse number for
output voltages of D2L and D3L inverters ND2L , ND3L is
equal to 2N2L and 2N3L , respectively. It can be shown that,
the device switching frequencies fs of the 2L and 3L-NPC
inverters are equal to (2N2L + 1)f1 and N3L f1 , respectively.
If maximum device switching frequency fs,max is fixed, then
the values of N2L and N3L are obtained as,


fs,max f1
2f1


fs,max
= f loor
f1

N2L = f loor

(1)

N3L

(2)

The values of ND2L , ND3L , and fs for any given m can

be determined from (1) and (2), as shown in Table I (a)-(b),
respectively. The device switching frequencies fs of D2L and
D3L inverters versus fundamental frequency of operation f1
are shown in Fig. 3 (a)-(b), respectively. As shown in Table
I and Fig. 3, fs,max for D2L and D3L inverters are limited
to 400 Hz and 200 Hz, respectively. After determining the
values of ND2L and ND3L for a given m, the next step would
be to determine optimal switching patterns for all steady-state
operating points.
B. Derivation of Objective Function
The distortion factor d is used as an objective function for
optimization, which is independent of machine parameters.

3866

Table I: Pulse number N and device switching frequencies fs for a given m. (a) D2L inverter (b) D3L inverter

0.889
0.728
0.616
0.534
0.471
0.422
0.382
0.349
0.321
0.297

m
f1 (Hz) N2L1 N2L2 ND2L
fs (Hz)
- 1.000 44.49 - 50.00 3
3
6 311.46 - 350
- 0.888 36.41 - 44.44 4
4
8 327.73 - 400
- 0.727 30.82 - 40.00 5
5
10 339.01 - 400
- 0.615 26.72 - 30.77 6
6
12 347.32 - 400
- 0.533 23.58 - 26.67 7
7
14 353.69 - 400
- 0.470 21.10 - 23.53 8
8
16 358.75 - 400
- 0.421 19.09 - 21.05 9
9
18 362.85 - 400
- 0.381 17.44 - 19.04 10 10
20 366.27 - 400
- 0.348 16.05 - 17.39 11 11
22 369.15 - 400
- 0.320 14.86 - 16.00 12 12
24 371.62 - 400

0.801
0.667
0.572
0.501
0.445
0.401
0.364
0.334
0.308
0.286

m
f1 (Hz) N3L1 N3L2 ND3L
fs (Hz)
- 1.000 40.05 - 50.00 4
4
8 160.20 - 200
- 0.800 33.38 - 40.00 5
5
10 166.90 - 200
- 0.667 28.62 - 33.33 6
6
12 171.73 - 200
- 0.571 25.05 - 28.57 7
7
14 175.35 - 200
- 0.500 22.27 - 25.00 8
8
16 178.17 - 200
- 0.444 20.05 - 22.22 9
9
18 180.45 - 200
- 0.400 18.23 - 20.00 10 10
20 182.32 - 200
- 0.363 16.71 - 18.18 11 11
22 183.88 - 200
- 0.333 15.43 - 16.67 12 12
24 185.21 - 200
- 0.307 14.33 - 15.38 13 13
26 186.36 - 200

(a)

(b)

transitions at switching angles i . The value of s(i) is equal

to -1 for transition to lower potential and s(i) is equal to 1 for
transition to higher potential. Assuming that stator currents are
determined by leakage inductances, the final expressions for
dD2L is obtained as [20],
pP
2
k ikD2L
dD2L = qP
2
k ikD2L,sixstep
q
P ukD2L
2
1

(a)

1
l

q
P

q1 P

1 l

ukD2L,sixstep
2
k

PND2L

1
k ( k4 )(

i=1

s(i)cos(ki ))2

qP

(6)

1
k ( k4 )

(b)
Fig. 3. Device switching frequency fs versus fundamental frequency of
operation f1 . (a) D2L inverter (b) D3L inverter

The expression of d is given by [19],

ih
d=
ih,sixstep

(3)

where, ih , ih,sixstep represents the harmonic rms current during normal operation and six-step operation (m=1 or f1 =f1R )
of the multilevel inverter, respectively.
The stator winding voltages consists of 3L waveforms in
case of D2L inverter fed induction motor drive. By utilizing
Fourier series analysis, the harmonic components of stator
winding voltages vj1j2 (j=A,B,C) for normal and six-step
operation are obtained as,
ukD2L =

ND2L
4Vdc X
s(i)cos(ki )
k i=1

(4)

4Vdc
(5)
k
where, k corresponds to k th order harmonic component
(k=1,3,5,7,9,11...), s(i) represents the slopes of switching
ukD2L,sixstep =

The voltages across stator windings consist of 5L waveforms in case of D3L inverter fed induction motor drives.
By using Fourier series analysis, harmonic components of
machine phase voltages vj1j2 (j=A,B,C) for normal and sixstep operation are obtained as,
ukD3L =
ukD3L,sixstep =

ND3L
4Vdc X
s(i)cos(ki )
k i=1

(7)

8Vdc
k

(8)

Assuming that stator currents are determined by leakage

inductances, the final expressions for dD3L is obtained as [20],
qP
PND3L
1
2
k ( k4 )(
i=1 s(i)cos(ki ))
qP
dD3L =
(9)
1
2
k ( k4 )
It can be observed that expressions for distortion factor
dD2L , dD3L depends only on the switching patterns (s(i), i
and pulse number N ). As the induction motor is operated in
constant ( fv ) control mode, the constraint on switching angles
to set the fundamental frequency of inverter output voltage to

3867

f1 is obtained as,
f1
u1
=
f1R
u1,sixstep
NX
D2L
mD2L =
s(i) cos(i )
mD3L =

i=1
NX
D3L

1
2

(10)
Fig. 4. Distortion factor d versus modulation index m for D2L and D3L
inverters with fs,max = 400 Hz and 200 Hz, respectively.

s(i) cos(i )

(11)

i=1

where, mD2L and mD3L denotes the modulation index value

of D2L and D3L inverters, respectively.
C. Optimization of Switching Patterns
For the optimization problem, it is sufficient to consider
a single-phase switching pattern in a quarter period. The
complete single-phase switching pattern (0 to 360 ) can be
obtained by using half-wave and quarter-wave symmetry. Finally, the three-phase switching pattern is obtained by shifting
the single-phase switching pattern by 0 , 120 , and 240 ,
respectively.
In the optimization, the first step is to determine the value
of pulse number N for a given m based on (1) or (2). Next,
generate 0.5*N initial angles ang1 randomly for one inverter
and initial angles ang2 for second inverter are obtained by
shifting ang1 by 120 . Then, obtain the initial angles ang for
stator winding voltages from ang1 and ang2. Thus, all the
zero-sequence voltage components in stator winding voltages
are eliminated due to 120 phase shift between inverter output
voltages. Next, the possible structures st of stator winding
voltages are determined. The structure represents a unique
sequence of voltage levels, which is usually represented in
terms of switching transitions s(i) at each switching angle.
For example, there exists only possible structure for 2L and
3L waveforms as shown in Fig. 2(a)-(b), respectively. Then, all
the possible switching patterns for D2L and D3L inverters are
obtained by combining ang and st. For each switching pattern,
optimization is performed to determine switching angles that
minimize the objective function value (dD2L or dD3L ), for
all steady-state operating point (m,N ). The optimal switching
patterns are stored in a FPGA controller for all operating points
(m,N ). After optimization, there might be large discontinuities
in switching angles for consecutive operating points with same
N . Thus, post-optimization is performed if switching angles
for consecutive values of m with same N differ by more than
5 degrees [21].
The proposed SOP algorithm was implemented using MATLAB programming for D2L and D3L inverters with fs,max
equal to 400 Hz and 200 Hz, respectively. The values of d for
D2L and D3L inverters for various values of m, are shown in
Fig. 4. It can be observed that performance of D3L inverter is
always better than D2L inverter, which is due to increase in
number of voltage levels. As the value of m becomes close
to unity, operation of the inverter will be similar to six-step
operation and hence results in higher THD. The SOP offers
best performance in the range from m = 0.30 to 0.94.

(a)

(b)

(c)
Fig. 5. (a) Experimental results for (m=0.9333, N =6). X-axis:10 ms/div.
(1) Stator winding voltage (Y-axis:50 V/div). (2) Stator current (Y-axis:4
A/div). (3) Zero-sequence current (Y-axis:1 A/div). (b) Experimental results
for (m=0.7255, N =10). X-axis:10 ms/div. (1) Stator winding voltage (Yaxis:50 V/div). (2) Stator current (Y-axis:4 A/div). (3) Zero-sequence current
(Y-axis:1 A/div). (c) Experimental results for (m=0.502, N =14). X-axis:10
ms/div. (1) Stator winding voltage (Y-axis:50 V/div). (2) Stator current (Yaxis:4 A/div). (3) Zero-sequence current (Y-axis:1 A/div)

3868

III. E XPERIMENTAL R ESULTS

The proposed SOP technique was implemented to control
D2L and D3L inverters feeding 1.5-kW open-end stator winding induction motor drive. The inverters were prepared using
six-pack modules FS30R06W1E3 (VCE =600 V, ICnom =30
A) and 3L-NPC modules F3L30R06W1E3 B11 (VCE =600
V, ICnom =30 A) from Infineon and for driving IGBTs, SKHI
61R (VCE =900 V, fmax =50 kHz) from Semikron was used.
At the inverter output terminals, LC filter was not used in
order to get better understanding of the significant harmonics
in stator currents.

(a)

A. D2L inverter
The optimal switching angles were generated for three
operating points (m=0.9333, f1 =46.67 Hz, N=6), (m=0.7255,
f1 =36.275 Hz, N=10) and (m=0.5020, f1 =25.1 Hz, N=14).
The D2L inverter was supplied with DC input voltage of
70 V. The stator winding voltage, stator current, and zerosequence current for three operating points are shown in Fig.
5 (a)-(c), respectively. It can be observed that, stator voltages
consists of 3L waveforms and the stator currents are nearly
sinusoidal with device switching frequencies limited to 400
Hz. The zero-sequence components are obtained by using the
relation (ia +i3b +ic ) and it can be observed that they are almost
eliminated.
The space vector trajectories of stator currents for the three
operating points are shown in Fig. 6 (a)-(c), respectively.
The nearly circular trajectories demonstrate lower harmonic
distortion, although the device switching frequencies were
limited to 400 Hz. The stator currents are recorded into a PC
by using data acquisition system and it is further analyzed
to estimate the harmonic distortion of stator currents. The
current harmonic spectrum for three operating points are
shown in 7 (a)-(c), respectively. The THD of stator currents
for three operating points were obtained as 4.1%, 9.25%
and 13.2%, respectively. It can be observed that harmonic
distortion increases at lower values of modulation index. For
operating point (m=0.7255, N =10), there was one significant
harmonic (19th ) of magnitude equal to 7.5% of fundamental.
Similarly, for operating point (m=0.502, N =14), there were
two significant harmonics (29th and 31st) with magnitude
equal to 7% and 8.9% of fundamental. However, these higher
order dominant harmonics can be attentuated signficantly by
using LC filter at the inverter output terminals.

(a)

(b)

(c)

Fig. 6. Stator current space vector trajectories (a) (m=0.9333, N =6) (b)
(m=0.7255, N =10) (c) (m=0.5020, N =14)

(b)

(c)
Fig. 7. Harmonic spectrum of stator currents (enlarged view to show the
dominant harmonic components). X-axis: Frequency (Hz). Y-axis: IIh . (a)
1
(m=0.9333, N =6) (b) (m=0.7255, N =10) (c) (m=0.502, N =14)

B. D3L inverter
The optimal switching patterns were generated for three
operating points (m=0.9294, f1 =46.47 Hz, N=8), (m=0.6667,
f1 =33.33 Hz, N =12) and (m=0.5098, f1 =25.49 Hz, N=14).
The DC input voltage to D3L inverter was maintained at 60 V.
The stator winding voltages, stator current, and zero-sequence
current for each operating points are shown in Fig. 8 (a)-(c),
respectively. The stator winding voltages of machine consists
of 5L waveforms. The stator currents are nearly sinusoidal
although device switching frequencies are limited to 200 Hz.
The improvement in THD of stator currents compared to
D2L inverter can be observed. The zero-sequence current
components are almost eliminated. It should be noted that,
there exist small zero-sequence currents as the stator currents
in each phase might differ due to unequal winding resistances
and inductance values.
The space vector trajectories of stator currents for three
operating points (m=0.9294, N=8), (m=0.6667, N =12) and
(m=0.5098, N=14), are shown in Fig. 9 (a)-(c), respectively.
The nearly circular trajectories demonstrate low THD with
device switching frequencies limited to 200 Hz. In addition,
data acquisition system was used to record stator currents into
a PC to perform FFT analysis. The THD of stator currents for
three operating points were equal to 2.63%, 6.11% and 5.64%,
respectively, as shown in Fig. 10(a)-(c). It can be conlcuded
that better quality of stator current waveforms are acheived
with D3L inverter compared to D2L inverter, which is due to
5L waveforms across stator windings.

3869

(a)

(a)

(b)

(c)
Fig. 10. Harmonic spectrum of stator currents (enlarged view to show the
dominant harmonic components). X-axis: Frequency (Hz). Y-axis: IIh . (a)
1
(m=0.9294, N =8) (b) (m=0.667, N =12) (c) (m=0.5098, N =14)

(b)

IV. S UMMARY AND C ONCLUSION

(c)
Fig. 8. (a) Experimental results for (m=0.9294, N =8). X-axis:10 ms/div.
(1) Stator winding voltage (Y-axis:50 V/div). (2) Stator current (Y-axis:4
A/div). (3) Zero-sequence current (Y-axis:1 A/div). (b) Experimental results
for (m=0.6667, N =12). X-axis:10 ms/div. (1) Stator winding voltage (Yaxis:50 V/div). (2) Stator current (Y-axis:4 A/div). (3) Zero-sequence current
(Y-axis:1 A/div). (c) Experimental results for (m=0.5098, N =14). X-axis:10
ms/div. (1) Stator winding voltage (Y-axis:50 V/div). (2) Stator current (Yaxis:4 A/div). (3) Zero-sequence current (Y-axis:1 A/div)

(a)

(b)

(c)

Fig. 9. Stator current space vector trajectories (a) (m=0.9294, N =8) (b)
(m=0.667, N =12) (c) (m=0.5098, N =14)

The requirements in dual inverter fed medium-voltage highpower drives are low device switching frequencies, low harmonic distortion of machine stator currents and elimination
or minimization of zero-sequence current components. A new
SOP technique has been proposed to satisfy all these three
requirements. The main idea is to generate 120 phase shift
between switching patterns and then optimize the switching
patterns to minimize the harmonic distortion of stator currents.
The proposed technique has been demonstrated on D2L and
D3L inverters feeding an open-end stator winding induction
motor drive. The maximum device switching frequencies
fs,max were limited to 400 Hz and 200 Hz, respectively.
In case of D2L inverter fed induction motor drive, the zerosequence components are almost eliminated with THD of machine stator currents in the range from 4% to 13%. Moreover,
significant harmonics in current waveforms are of higher order,
which can be further attenuated by using LC filter at the
inverter output terminals. On the other hand, the harmonic
distortion of stator currents was further reduced by using the
D3L inverter. The THD of stator currents was in the range
of 3% to 7% and the zero-sequence current components are
almost eliminated. The improvement is qualiy of stator current
waveforms with D3L inverter is due to 5-level waveforms
across stator windings. It can be concluded that, the proposed
SOP technique was able to eliminate zero-sequence currents as
well as minimize the THD of stator currents, while operating
MLCs at low device switching frequencies.

3870

R EFERENCES
[1] H. Abu-Rub, J. Holtz, J. Rodriguez, and G. Baoming, Medium-Voltage
Multilevel Converters -State of the Art, Challenges, and Requirements
in Industrial Applications, IEEE Trans. Ind. Electron., vol. 57, no. 8,
pp. 2581 2596, aug. 2010.
[2] S. Kouro, M. Malinowski, K. Gopakumar, J. Pou, L. Franquelo, B. Wu,
J. Rodriguez, M. P
erez, and J. Leon, Recent Advances and Industrial
Applications of Multilevel Converters, IEEE Trans. Ind. Electron.,
vol. 57, no. 8, pp. 2553 2580, aug. 2010.
[3] L. Franquelo, J. Rodriguez, J. Leon, S. Kouro, R. Portillo, and M. Prats,
The age of multilevel converters arrives, IEEE Ind. Electron. Mag.,
vol. 2, no. 2, pp. 28 39, june 2008.
[4] J. Rodriguez, J.-S. Lai, and F. Z. Peng, Multilevel inverters: a survey
of topologies, controls, and applications, IEEE Trans. Ind. Electron.,
vol. 49, no. 4, pp. 724 738, aug 2002.
[5] H. Stemmler and P. Guggenbach, Configurations of high-power voltage
source inverter drives, in Fifth European Conf. Power Electron. and
Appl., 1993.,, 1993, pp. 714 vol.5.
[6] M. Janen, Pulsewidth modulated control of a dual-three-level inverter
to feed high-power induction motors with high dynamic requirement,
Ph.D. dissertation, Bochum University, Bochum,Germany, 2000.
[7] V. Somasekhar, K. Gopakumar, M. R. Baiju, K. Mohapatra, and
L. Umanand, A multilevel inverter system for an induction motor with
open-end windings, IEEE Trans. Ind. Electron., vol. 52, no. 3, pp. 824
836, June 2005.
[8] G. Mondal, K. Sivakumar, R. Ramchand, K. Gopakumar, and E. Levi, A
Dual Seven-Level Inverter Supply for an Open-End Winding Induction
Motor Drive, IEEE Trans. Ind. Electron., vol. 56, no. 5, pp. 16651673,
May 2009.
[9] P. Rajeevan, K. Sivakumar, K. Gopakumar, C. Patel, and H. Abu-Rub,
A Nine-Level Inverter Topology for Medium-Voltage Induction Motor
Drive With Open-End Stator Winding, IEEE Trans. Ind. Electron.,
vol. 60, no. 9, pp. 36273636, 2013.
[10] V. T. Somasekhar, K. Gopakumar, E. Sivakumar, and S. Sinha, A space
vector modulation scheme for a dual two level inverter fed open-end
winding induction motor drive for the elimination of zero sequence
currents, EPE Journal, vol. 12, no. 2, pp. 2636, 2002.

[11] M. R. Baiju, K. Mohapatra, R. S. Kanchan, and K. Gopakumar, A dual

two-level inverter scheme with common mode voltage elimination for
an induction motor drive, IEEE Trans. Power Electron., vol. 19, no. 3,
pp. 794805, 2004.
[12] P. N. Tekwani, R. S. Kanchan, and K. Gopakumar, A Dual FiveLevel Inverter-Fed Induction Motor Drive With Common-Mode Voltage
Elimination and DC-Link Capacitor Voltage Balancing Using Only
the Switching-State Redundancy Part I, IEEE Trans. Ind. Electron.,
vol. 54, no. 5, pp. 26002608, 2007.
[13] , A Dual Five-Level Inverter-Fed Induction Motor Drive With
Common-Mode Voltage Elimination and DC-Link Capacitor Voltage
Balancing Using Only the Switching-State Redundancy Part II, IEEE
Trans. Ind. Electron., vol. 54, no. 5, pp. 26092617, 2007.
[14] G. Mondal, K. Gopakumar, P. N. Tekwani, and E. Levi, A reducedswitch-count five-level inverter with common-mode voltage elimination
for an open-end winding induction motor drive, IEEE Trans. Ind.
Electron., vol. 54, no. 4, pp. 23442351, Aug 2007.
[15] J. Holtz and X. Qi, Optimal Control of Medium-Voltage Drives An
Overview, IEEE Trans. Ind. Electron., vol. 60, no. 12, pp. 54725481,
Dec 2013.
[16] J. Holtz and N. Oikonomou, Optimal Control of a Dual Three-Level
Inverter System for Medium-Voltage Drives, IEEE Trans. Ind. Appl.,
vol. 46, no. 3, pp. 1034 1041, may-june 2010.
[17] T. Boller, J. Holtz, and A. Rathore, Optimal Pulsewidth Modulation of
a Dual Three-Level Inverter System Operated From a Single DC Link,
IEEE Trans. Ind. Appl., vol. 48, no. 5, pp. 16101615, Sept 2012.
[18] G. S. Buja, Optimum Output Waveforms in PWM Inverters, IEEE
Trans. Ind. Appl., vol. IA-16, no. 6, pp. 830 836, nov. 1980.
[19] J. Holtz, Pulsewidth modulation for electronic power conversion,
Proceedings of the IEEE, vol. 82, no. 8, pp. 1194 1214, aug 1994.
[20] A. Rathore, J. Holtz, and T. Boller, Synchronous Optimal Pulsewidth
Modulation for Low-Switching-Frequency Control of Medium-Voltage
Multilevel Inverters, IEEE Trans. Ind. Electron., vol. 57, no. 7, pp. 2374
2381, july 2010.
[21] A. Rathore, H. Holtz, and T. Boller, Generalized Optimal Pulsewidth
Modulation of Multilevel Inverters for Low-Switching-Frequency Control of Medium-Voltage High-Power Industrial AC Drives, IEEE Trans.
Ind. Electron., vol. 60, no. 10, pp. 42154224, Oct 2013.

3871