i.e.

if

3 Differential Amplifiers

V1 = Vx + Vpickup
V2 = Vy + Vpickup
where Vpickup is a signal common to both, then
V0 = Ad (V1 V2 ) = Ad (Vx Vy )

3.1 Differential Amplifiers

[ref: Art of Electronics, by Horowitz & Hill]

Figure 3.2:

Figure 3.1:

DC amplifiers (one can ground one input e.g. V2 = 0) then

Vout = Ad (V1 V2) = Ad (V1 0) = Ad V1

Differential amplifiers are amplifiers which are designed to amplify the

difference between two input signals i.e.
Vout = Ad (V1 V2 )
where Ad is the differential voltage gain. Ad is a positive number, and thus
if V1 is greater than V2 then the output with be a positive with respect to
the circuit ground.
Applications of differential amplifiers include:
Amplifying a weak signal carried by a pair of wires, where both wires
are not at ground potential (being the ground of the amplifier). Signals
common to both wires (e.g. pickup of 50 Hz) cancel in the subtraction,

3-1

Balanced transmission lines (used sometimes for audio applications and

for RF applications).
The type of amplifier known as the operational amplifier or opamp is
a specially designed differential amplifier with very high gain (>105).
Opamps can be used to implement a variety of analogue signal processing and conditioning circuits including: addition, subtraction, inversion, active filters, integration, differentiation, logarithms, peak detectors, gyrators (an inductor built using opamp and a capacitor),
active rectifiers, etc.
In linear signal processing applications (filtering, amplification), opamp
circuits usually employ negative feedback which reduces the gain, but

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provides some very desirable properties such as improved linearity, independence of fluctuations in Ad as a result of temperature).
Opamp circuits usually operate in the kHz frequency range, but some
of the faster opamps can be used in the MHz region.
3.1.1 Terminology
The input terminal labelled V1 or + is known as the non-inverting input
(if V2 = 0 then V0 = Ad V1 ).
The input terminal labelled V2 or - is known as the inverting input (if
V1 = 0 then V0 = Ad V2).
A differential change1 at the inputs refers to a change in Vd = (V1 V2 ).
A common-mode change refers to a change in voltage which is common to
both inputs.
Ideally a differential amplifier should respond only to differential changes at
the inputs. In practical circuit implementations the output is also sensitive
to common-mode changes. For example if we tie both inputs together and
connect the inputs to a signal generator, the output will responds to some
degree.
To characterise the behaviour, it is useful to define two voltage gains:

where Vc is a change common to both inputs. i.e. V1 and V2 change

V1 V1 + Vc
V2 V2 + Vc
A good differential amplifier will have a differential gain which is high compared to its common-mode gain, i.e
Ad Ac

Common-mode Rejection Ratio (CMRR)

Another parameter which characterises an amplifier is the ratio,

CMRR =

Ad
Ac

which is sometimes expressed in dB, being

 
 Ad 
20 log  
Ac

Example
Differential gain

The commercially available OP-77 opamp has a CMRR of 120 dB (stated

in the data sheets). From this we can conclude that
 
 Ad 
120
|CMRR| =   = 10 20 = 106
Ac

Vout
Ad =
Vd
where Vd is an incremental change in the difference voltage, i.e.
Vd = (V1 V2 ) V1 V2 + Vd

as a ratio. Although the quantity Ad is positive, the common mode gain Ac

may be positive or negative depending on the circuit implementation. All
we can say from the dB CMRR alone is that |Ac | = 106 Ad .

Common-mode gain

Ac =
1

Vout
Vc

A differential change is also sometimes called a normal mode change.

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3.2 Transistor implementation of a differential amplifier

A differential amplifier can be constructed using a pair of matched transistors. The configuration shown in Figure 3.3 is known as the emitter coupled
pair (because the emitters are coupled together (via the RE s) at the node
marked A). This configuration is also known as the long tail pair, because
of transistors attached to a tail resistor R. It may be implemented using
BJT transistors (NPN or PNP) or FETs.

in the tail resistor R. In our analysis we shall assume a large , say

> 100, such that IC IE holds.
Because of the symmetry, if the two inputs are tied together (i.e. V1 =
V2 ), then I1 = I2, assuming identical transistors.
The output is taken at the collector of transistor Q2 .
3.2.1 Differential Gain Analysis
Consider, initially, the sitation where both inputs are grounded, i.e. V1 =
V2 = 0.
The voltage at node A will be a volt or two below zero (depending on the
value of RE and the operating current).
The collector currents I1 and I2 both flow through the same tail resistor
R, and since we are ignoring base currents, IEE = I1 + I2. Thus, from the
symmetry, we have
IEE
I1 = I2 =
2
The output voltage is taken from the collector of Q2, being
Vout = VCC I2RC

Figure 3.3: Differential amplifier implemented using a long tail pair.

In order for the emitter coupled pair to function well as a differential

amplifier, the transistors should be accurately matched (near identical
characteristics), ideally manufactured on the same piece of silicon.
The inputs are at the bases of the transistors, marked V1 (non-inverting
input) and V2 (inverting input).
The supply rails are marked VCC and VEE . Typical values could be
VCC = 15 V and VEE = 15 V.

The output voltage is typically arranged to sit at half the supply (VC =
1
V ) for the case when both inputs are grounded.
2 CC
Now consider what happens if a small differential voltage V = V1 V2 (say
less than 100 mV) is created between the input terminals, by increasing V1
V
by V
2 and decreasing V2 by 2 such that V1 V2 = V . The differential
voltage is created in such a way to avoid introducing a common-mode component at the input (i.e. the average voltage is still zero).
The emitter voltages will follow with approximately the same increments,
and so by symmetry, the voltage at node A will not change significantly
(VA V ). Thus we consider VA = 0.

The transistors carry currents I1 and I2 which sum together at the

coupling point marked A in the sketch. A current IEE I1 + I2 flows

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Since the voltage at A is fixed, the collector current I1 will increase by

an amount
V /2
V1
=
I1 =
re + RE
re + RE
where re = 25 mV/I1.
I2 will decrease by the same amount:
I2 =

RC
V /2
V
RC =
re + RE
2 (re + RE )

I2
50mV

50mV

100mV

Alternative explanation of the differential voltage gain

RC
Vout
=
V
2 (re + RE )

(being half of the gain derived for a single ended common emitter AC amplifier).
Figure 3.4 shows a plot of the currents I1 and I2 as a function of the differential input voltage V . As V increases from zero, the currents I1 and
I2 are initially fairly linear functions of V but eventually flatten as |V |
increases. For larger values of V (a few volts), Q2 will switch off completely, and IEE = I1 (V1 0.6)/(RE + R), rising beyond the operating
value as V1 continues to increase (this plot does not extend that far).

3-7

IEE
2

Figure 3.4: Plot of the collector currents I1 and I2 as a function of the differential input
voltage V .

Thus the differential voltage gain is

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I1

100mV

This causes the output voltage to rise by

Ad =

IEE

V /2
= I1
re + RE

Vout = I2RC =

IC IE

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From our previous analysis of a single transistor AC amplifier, it should be

obvious that if V2 decreases by V /2 and the voltage at node A is fixed,
then
Vout
Vout
Rc
=
=
V2
V /2 re + RE
Thus
Rc
Vout
=
Ad =
V
2 (re + RE )

3.2.2 Common Mode Gain Analysis

The common-mode gain is determined by tying both inputs and injecting
a voltage common to both. The analysis may be simplified by splitting the
circuit into two parts as illustrated in Figure 3.5. The tail resistor is split
into two resistors each of value 2R carrying currents I1 = I2 = IEE /2.

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3.2.3 The CMRR

Substituting the expression for Ad and Ac into the definition of common
mode rejection ratio, we get
CMRR

RC
RC
Ad
/
=
Ac
2(re + RE ) re + RE + 2R

CMRR =

re + RE + 2R
2 (re + RE )

Note To achieve a high CMRR, one should choose R re + RE for

which the following approximation can be made:
CMRR

R
re + RE

3.2.4 Practical Circuit

Figure 3.5:

If both inputs are tied together and change by an amount V = V1 =

V2, then (as in the standard analysis of a single transistor AC amplifier)
Vout = I2RC =

RC
V2
RC =
V2
re + RE + 2R
re + RE + 2R

and

Vout
RC
=
V2
re + RE + 2R
Thus the common mode gain is
Ac =

RC
Vout
=
V
re + RE + 2R

Figure 3.6:

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 The components are chosen such that Vout 12 VCC when V1 = V2 = 0.

One can omit the resistor RC from Q1 , saving one resistor. This will
have no influence on the circuit as I1 is not a function of the collector
resistance of Q1.

To improve the CMRR, one can replace the tail resistor R by a current
source which has very high impedance. Observe that as R , Ac 0
and |CMRR| . A practical circuit can achieve a CMRR of 106, with a
well designed current source.

Quiescent current at Vout = 12 VCC is designed to be 100A.

The voltage at node A is
VA = V1 VBE1 I1RE 0 0.6 0.1 = 0.7 V
The intrinsic emitter resistance is
re

25
= 250
0.1

The differential gain is

RC
2 (re + RE )
75000
30
=
2 (250 + 1000)

Ad =

Figure 3.7:

The common mode gain

If one ties V1 and V2 together, then I1 = I2 = IEE /2 (always), independent

of the base voltage. Thus the use of a current source in the tail eliminates
common-mode gain, and the CMRR is theoretically infinite.
A practical circuit is shown in Figure 3.8. The emitter current

RC
RC
75
Ac =

=
0.5
(re + RE + 2R)
2R
2 72
Thus
CMRR =

30
= 60
(0.5)

IEE = IC3 IE3 =

3.2.5 Improved CMRR Performance using current source

The common mode gain and the common mode rejection ratio are functions
of the tail resistance R, i.e.

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The emitter voltage is biased to a couple of volts above the negative rail.
This ensures that small changes in VBE2 do not significantly affect the current IE3.
The output impedance2 of the current source is about 4 M, which implies
2

RC
re + RE + 2R
R
CMRR
re + RE
Ac =

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VE3 VEE
VB 0.6
=
RX
RX

The output impedance of this BJT current source implementation (with the base at a fixed voltage)
can be shown to be R0 = r0 (1 + (re k RE )/(re k r0 )) r0 (1 + RE /(re + RE )) where RE is the
emitter resistor, r0 is the collector emitter resistor in the small signal model. For a collector current
IC , r0 = VA /IC where VA is the so called Early voltage, specified in data sheets. For a discrete BJT
transistor like the 2N2222A, 100 < VA < 500, and so for a collector current of 2 mA, this would predict
50 k < r0 < 250 k. For r0 = 100 k, RE = 1000 , = 100, re = 25/2 = 12.5 , R0 4.5 M.

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3.3 DC Amplifier

a CMRR of 4E6/(25 + 100) = 32400 or 90 dB.

Figure 3.8: Current source in the tail.

Figure 3.9:

A non-inverting DC amplifier can be created from a differential amplifier by grounding one input V2 = 0, and feeding the input signal at
V1 .
The output can not swing below the base voltage of Q2, which is zero.
Thus for the case of Vin = V1 = 0, the output is typically designed to
sit at Vout = 12 VCC (by the choice of RC ). A subsequent level shift stage
may be used to remove the 12 VCC offset at the output.
The use of a differential amplifier (with one input grounded) for DC
amplification essentially removes the problem of the 0.6 volt VBE offset present in a single transistor amplifier shown in Figure 3.10, and
compensates for dependence on temperature.
For a fixed collector current, VBE decreases by 2.1 mV/C increase
in temperature. If the temperature increases, the reduction in VBE
forces the collector current (Figure 3.10) to increase, and hence the
output voltage decreases.

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 The differential amplifier inherently compensates for temperature drifts

because the VBE voltages of well matched transistors change by same
amount. The identical changes in VBE will not be amplified by Ad , but
by the common-mode gain Ac, which is small (usually <1) compared
to Ad .
If V2 = 0, Vin = V1 , then the common-mode change is Vc = (V1 +
V2 )/2 = Vin /2, and so the output is
Vout = Ad Vin + Ac
Ad Vin +

Vin VCC
+
2
2

VCC
2

since Ad Ac .

Figure 3.11:

First, we examine how VA changes if V1 is increased by V1.

For incremental changes about the bias point, from nodal analysis, considering incremental changes in current into node A
V1 VA V2 VA VEE VA
= 0
+
+
re + RE
re + RE
R
Figure 3.10: Use of a single stage transistor as a DC amplifier suffers from the input offset
as well as temperature dependence.

Since V2 = 0 (constant), V2 = 0. Since VEE is a fixed voltage, VEE = 0.

Substituting and grouping terms, we get
V1
2VA
VA
=0

re + RE re + RE
R

3.3.1 Gain Analysis of the DC Amplifier

Consider the DC amplifier configuration below.
Note that I1 + I2 I and
I1
I2

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and solving for VA

+ I
2
I
I

3-15

VA

1
2
+
re + RE R
VA =

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V1
re + RE

V1
E
2 + re +R
R

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Since R re + RE (by design)

3.3.2 Input Impedance of DC Amplifier

VA

V1
2

Take note that an increase in V1 of V1 will cause VA to rise by VA

V1
2 .

Next, we try to express Vout in terms of V1.

The incremental output voltage
Vout = I2RC
but

VBE2
VA
=
re + RE
re + RE
Substituting our expression for VA ,
I2 =

I2 =
Thus
Vout
The gain is thus

2+

V1


(re + RE )

re +RE
R

Figure 3.12:

RC


= V1
re +RE
(re + RE )
2+ R

Vout
=
V1
2+

If V2 = 0, the input impedance is times the effective impedance looking

into the base of Q1 considering the impedance paths to ground, i.e.

RC


(re + RE )

Zin = [(re1 + RE1 ) + R|| (re2 + RE2 )]

re +RE
R

If R re + RE (by design of a good high impedance current source) then

gain of the DC amplifier is
Gain =

Vout
RC
=
V1
2 (re + RE )

Figure 3.13: Inpedance paths to ground seen looking into the base.

For matched components RE1 = RE2 = RE and re1 = re21 = re , so

Zin = [(re + RE ) + R|| (re + RE )]

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3.4 Audio Pre-Amplifier with Load

If R (re + RE ), which is usually true in practice, then

Zin 2 (re + RE )
Example: For I = 200 A, = 100, in Figure 3.12,
25
= 250
0.1
= 1000

re =
RE

Zin = 250 k
Note Very much higher input impedance can be achieved using FET transistors. FET input stages are often used in opamps (although FET input
stages have higher voltage noise than BJT input stages).
Input impedance of DC amplifier (by derivation)

Zin =
Since

I1 = I2 =
and Vin V1 , thus
Zin

Figure 3.14:

Vin
Vin
Vin
=
=
Iin
I1/
I1

Voltage Gain

re + RE
= 2+
R
2 (re + RE )

RC ||RL


re +RE
(re
R

Vo
=
Vin

V1


re +RE
2+ R
(re + RE )

2+
Rc ||RL

2 (re + RE )

+ RE )

Input Impedance

(re + RE )

Rin = R1 || [(re + RE ) + R|| (re + RE )]

Rin R1 ||2 (re + RE )

since R re + RE for a high impedance current source.

Input HPF breakpoint

1 =

1
R1 C1

Output HPF breakpoint

1
(RC + RL )C0
(Can you see why? Hint, think of the Thevening equivalent of the output
stage)
2 =

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3.5 Single Ended Differential Amplifier

3.6 Double Ended Differential Amplifier

A single ended differential amplifier is one which has one output.

A double ended differential amplifier has two anti-phase outputs

Used for transmitting signals over a balanced pair (audio & telecom
applications)

Figure 3.15:

One can ground either the + or the - input of a differential amplifier

to create either an inverting or a non-inverting DC amplifier.

Figure 3.17:

Double Ended Gain

Vout1 Vout2
V1 V2
Note The double ended gain is twice the single ended gain. i.e.
(double ended) A =

(double ended) A = 2
Figure 3.16:

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RC
RC
=
2 (re + RE ) re + RE

If we ground one input (say V2 = 0) then drive V1 with a small wiggle,

then we observe the following waveforms at the outputs:

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Figure 3.20:

Figure 3.18:

Recall Faradays law, which states that the induced voltage equals (minus) the rate of change of flux cutting a loop, i.e. Vind = ddtm adds in
series with the driving source.

3.6.1 Application of double ended amplifier

With a twisted pair, the net fluxzero. (flux contributions to adjacent

twists will cancel)

Figure 3.19:

A twisted pair transmission line is much less sensitive to pickup from

changing magnetic fields, compared to a parallel wire transmission line

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