Implementation of a 1.

5GHz-bandwidth radar with digital signal synthesis

and processing for probing in Arctic area.
S. A. Ermushev,
CEO of Klastek OOO, LLC
124498 Moscow, Zelenograd, proezd 4806, b.5
Russia
tel.: +79299016954
e-mail: klastek@list.ru

Abstract: An implementation of an on-board radar with digital synthesis and processing of

1.5GHz bandwidth signals for relief probing, subsurface probing and radiometry in Arctic
area is presented. The paper contains review and analysis of modern radar architecture
based on fast analog to digital converter (ADC), digital to analog converter (DAC) and field
programmable grid array (FPGA). These digital devices form a processing kernel of the
compact radar architecture and completed with analogous up- and down-converters,
amplifiers and antennas. Three different radar techniques are used in the proposed system
conventional active probing of the surface with the signal at 10-11.5GHz band, subsurface
active probing by video pulses with the band of 0-1.5GHz and passive radiometry scanning
with the band of 10-11.5GHz. Processing kernel of proposed system made from off-the-shelf
components and its performance evaluated on various algorithms of signal synthesis and
processing. Parallel processing by using programmable logic and dedicated algorithms for
correlation analysis provide a way to obtain all three types of data using only one on-board
radar system with universal processing kernel. Possible ways to joint processing and analysis
as well as a visual representation of the data are presented.
Key words: multisensory probing, probing in Arctic area, programmable logic, parallel processing.

INTRODUCTION
In recent years, an increasing role of digital techniques in signal processing as well as the
overwhelming replacement of analog components and circuits by digital signal processing (DSP)
systems have become a commonplace in the radar hardware development as it allows for a
significant increase in density and reproducibility of results (see [1] and references therein).
Against this background, the boundary between analog and digital domains in radar systems is
shifting toward the antenna subsystem. The use of digital approaches in radar can significantly
facilitate the system development, improve its performance and broaden the scope of its
capabilities. Double (sometimes even triple) digital down-conversion in the receive channel
dramatically increases performance of coherent systems. Digitized and heterodyned intermediate
frequency (IF) samples undergo further digital processing using pulse compression techniques
and correlation analysis, which enhances stability and dynamic range of radar systems. In the
transmit channel, DSP techniques are also widely applied since direct digital synthesis and
digital up-conversion have become available. The ultimate implementation of the described trend
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is the direct digital synthesis of phase and amplitude distribution in the so-called digital antenna
arrays.
Modern radars are rather complex systems performing a great number of operations and
processing a lot of information to solve a wide range of applied problems [2-4]. Although the
fundamental principle behind radiolocation is the same, there is a variety of different radars:
Doppler, synthetic aperture, multistatic, MIMO, etc. All of them have different structure and
require specific approaches to their implementation. Development of complex architecture
systems such as radio detectors raises a significant problem of universality and adaptation of
signal processing techniques. As mentioned above, radars can differ in a great number of
parameters (bandwidth, frequency range, scanning and aperture synthesis algorithms, number of
transceivers, etc.). Nevertheless, the majority of their operation principles remain the same. This
fact makes sensible the development of a universal architecture for realization of a wide range of
signal processing functions encountered in radar systems, the architecture elements being easily
connected and interchangeable for reasons of universality.
The implementation of the described approach will take the development of a concept
radar system to identify a universal set of required reconfigurable blocks. It is also necessary to
develop a set of universal buses for wideband data communication adapted to radar applications
(with strict requirements to determinacy and throughput) as well as a set of universal subsystem
control algorithms.
RVIEW AND ANALYSIS
The literature has many examples of the use of digital techniques to perform such functions
as frequency conversion, mixing, correlation processing and filtering of radar signals (see [5] and
references therein). The advantages of digital techniques bring about the need to digitally
implementation of common algorithms of frequency compensation, discrete Fourier transforms
spectral estimates, matched filtering, time domain convolution, etc. The main requirement to the
algorithms and their firmware and hardware implementation, in terms of resolution enhancement
of radar systems, generally comes down to the enhancement of signal bandwidth. At the same
time, most of radar applications require primary and secondary signal processing and online data
presentation. In case of wideband radars (e.g. using linear frequency modulation), the data flow
incoming to the digital subsystem will be quite high, which dictates the significant computational
power for the development of fully digital systems. For radars working with bandwidths close to
100 MHz, general-purpose processor (GPP) based systems for signal synthesis and processing
are not enough due to their low concurrency level. Fortunately, most of low-level algorithms,
which are necessary for radar operation, adapt very well to the parallel processing and can be
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implemented on massive parallel computers. Such massive parallel computers can either be
application-specific integrated circuits (ASIC) or field-programmable gate arrays (FPGA) [6,7].
The latter is preferable because the unit cost of ASIC development only becomes reasonable with
high volumes of manufacturing, and the number of currently manufactured wideband radars is
not as high as to justify the need for ASIC. Therefore, it is resource-intensive FPGA to be used as
a computing subsystem of the described architecture as it provides both parallel processing and
high throughput.
A general approach to building radar digital signal processing systems involves the
soonest-possible digitization of the signal and its processing in digital computers. For the ranging
signal synthesis, a reverse operation has to be performed the computed signal is converted back
to the analog domain using digital-analog converters (DAC). In radio engineering, it can be
implemented as a system with digital modulators and demodulators operating with a set of IF in
the analog domain, a system with direct conversion or even with direct sampling of radar signal.
In that case, DACs/ADCs are connected directly to the antenna (sometimes via the intermediate
amplifier) and sample the RF signal. Then frequency conversions are performed with digital
devices. However, in radar applications, the frequency range varies significantly from a few GHz
to hundreds of GHz according to the penetration capability requirements, propagation
environment and jamming situation, which dictates the need for direct analog conversion with
minimum IFs. For reasons of universality, the described architecture employs a pair of highspeed DAC and ADC to provide the IF bandwidth of 1.5 GHz and the schemes of analog
quadrature modulation/demodulation for direct up-conversion of transmitted and received signals
up to the required level.
Figure 1 shows a diagram of a radar system using a digital signal processing subsystem
based on the described architecture and supplemented by analog frequency converters
(quadrature modulator/demodulator), amplifier and filter blocks (in the receive and transmit
channels), and a phased antenna array. To ensure synchronization and coherent signal synthesis
and processing the system should also include a block with a very stable common oscillator and
a set of phase-lock digital and analog loopbacks to provide the required clock signals for the
compute kernel, ADC, DAC, quadrature modulator and demodulator.
Such a division ensures a highly independent tuning of the main radar parameters:
bandwidth, emission frequency, emission modes, angular resolution, dynamic range, etc. It
should also be noted that, thanks to the reconfigurability of the FPGA architecture, by means of
mere repetition the number of receive and transmit channels can be changed according to the
radar application irrespective of a given realization of the channels at the hardware level, and of
the synthesis and processing algorithms at the firmware level.
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Figure 2 shows a diagram of the proposed DSP blocks implemented on FPGA. The
architecture

blocks

are

implemented

as

interchangeable,

connected

and

scalable

hardware/firmware modules. The modules are designed in such a way that their coherent
operation is guaranteed irrespective of the parameters they are initialized with.
A bottleneck of the digital part is the raw signal synthesis and processing as well as its
serialization before the signal is transmitted to DAC and ADC. Parallel digital synthesizers based
on look-up tables provide the signal synthesis. The generated signal is then put into a specialized
buffer with the parallel access controller whereof it is extracted with serializers and sent at the
DAC input. At the physical level, Low-Voltage Differential Signal (LVDS) interface is used,
which provides the required noise-immunity and prevents to a certain degree the waveform
distortion.
In the receive channel, deserializers fill up the input buffer, after which the signal is
processed with the cascade pipelined frequency compensation algorithm. Then the spectral
conversion buffers are formed and the window function is applied. The spectral estimation is
then performed and the data are sent to the correlator that defines the echo-signal parameters and
generates raw information about targets and terrain.
The received data can be sent to the aperture synthesizer, which, in the simplest case, can
perform interferometric measurement, or directly to the identification logic of the compressed
signals (compressive sensing, sparse sampling), which builds a regularized model of the
detection object (target) based on the a priori information. After that, the information is
transferred to the module that converts them to an interpretable form. This module is also
responsible for the control of radar systems and electronic beam steering or amplitude and phase
distribution in multistatic systems.
The described architecture fully covers the functionality of radar or its parts, which
demonstrates the integrity of the system. The main feature of the architecture is a combination of
the system integrity with the capability of highly independent adjustment of key parameters to
any particular application. Radar systems to be developed using this architecture show to a full
extent the property of isomorphism of laws and connections, which makes it possible to talk
about the architectures universality. In the digital domain, FPGA reconfigurability allows for the
development of a library of interchangeable and scalable algorithms whose different
configurations enable necessary primary and secondary processing as well as interaction with
external memory and databases according to the specific task for the radar. The capability of
highly parallel execution of most of the signal processing algorithms as well as methods of
serialization and deserialization of data flows enables the use of the digital system for online
processing of data flows of different scale.
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Below are the main reconfiguration options for the parameters of a radar system built
according to the described architecture:
1) bandwidth, which defines the radar resolution, can be controlled by using highspeed or low-speed DAC and ADC;
2) dynamic range of the signals is defined by DAC and ADC bit capacity and can also
be controlled by using DAC and ADC with more or less bits;
3) frequency and power of the radar emission, as well as the emission bandwidth, are
defined by active analog components and have to be matched to passive filtering
and emitting circuits;
4) direct digital synthesis together with the use of controlled solid-state analog
elements enables pulse and continuous wave modes (online processing can be
implemented both for pulse and continuous wave radars using techniques of
orthogonal division in time or frequency domain);
5) different radar architectures such as multistatic, passive or monopulse can be
implemented by using an appropriate number of transmit and receive channels and
their independent tuning;
6) in case of multistatic systems, digital synthesis and processing not only allow for
detection, but also for communication functions;
7) primarily processed data conversion algorithms can contain radar functions based
on holographic techniques (synthesized aperture, interferometry) or compressed
pulse processing techniques;
8) requirements to external display and control interfaces are set according to the
specific realization of radar working place, its position, functions of operator or
external automated control system.
Finally, Figure 3 shows the processing kernel of the described architecture made from
off-the-shelf components and completed with antennas, up- and down-converters. This prototype
serves for testing various algorithms and DSP architectures implemented in FPGA. For example,
Figure 4 contains results of synthesis and processing of compressed pulse and presented as cross
correlation function of transmitted and received signals. Binary pseudorandom phase-coded
pulse with bandwidth of 1.5GHz was used in this example and the resulting resolution of the
measurement was found to be about 0.5m. To generate pseudorandom binary sequence linear
feedback shift register was implemented in FPGA core and configured to generate 10 streams in
parallel as described in [8]. Convolution of transmitted and received signals was performed in
frequency domain using fast Fourier transform algorithm. Summary of performance might be
done as follows: time of one pulse processing 320 s, number of used logic elements of FPGA
32.8k (18%), number of used memory blocks of FPGA 4.6M (32%).
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Due-to universality of the described architecture and reconfiguration ability of FPGA

such prototype may also serves as testing device for active probing with video pulses, passive
radiometry and moreover communication applications, that is planned for the future works.
IMPLEMENTATION IN AIRBORNE RADAR
Implementation issues of the described architecture into a radar prototype are illustrated
with an airborne active-passive system for terrain sensing and characterization in degraded visual
environments. A good example of practical application of such a system can be the enhancement
of situational awareness of the helicopter pilot during operations in the Arctic regions. In this
application, the radar can provide such functions as terrain imaging, ice situation monitoring,
snow and ice see-through capability that facilitate landing in poor visual environment such as
whiteout.
Specific character of the system application determines both the requirement for high
spatial resolution, that is high bandwidth, and for high penetration capability, that is low carrier
frequency, of the transmit signal. In this respect, a combination of X band (812 GHz) and baseband (01.5 GHz) radar is used. Another feature of the system is a combination of active and
passive regimes in X band. Hence, the proposed example uses two transmit and three receive
channels. Table 1 shows the parameters of the system.
Solid-state GaAs components are used as analog hardware components to ensure
frequency conversion in X band and signal power enhancement up to 30 W. Passive components
of the analog part are realized as microstrip structures on organic substrate including antenna
array elements implemented as rectangular patches.
Key elements of the digital domain hardware are FPGA, ADC and DAC, which enable the
implementation of advantages of the scalable and reconfigurable architecture. Table 2 shows the
main characteristics of the digital part components.
In the transmit radio and base-band channels, DAC is used to synthesize complex signals
that are computed in the FPGA kernel. The waveform can be changed depending on the flight
altitude and the required sensing range, e.g. for ranges over 1 km it is desirable to use a pulsed
mode with binary phase-coded signals based on pseudorandom sequences, for ranges of
hundreds of meters it is preferable to use a pulsed mode with binary phase-coded signals based
on shorter codes to minimize the sidelobes, while the only option for landing is continuous
waveform with linear frequency modulated (chirp) or phase-coded signals based on perfect
sequences that give minimum possible sibelobes [9]. The DAC sampling rate can be up to 1.5
GHz with a capacity of 14 bits, which requires the use of advantages of parallel signal processing
on FPGA since the FPGA clock frequency is several times lower. The existing methods of
parallel computation of pseudorandom sequences or chirp signal phases can be implemented on
6

FPGA and, if necessary, repeated separately for radio and base-band channels. Furthermore, a
uniformity of physical implementation of the channels allows to use only one DAC in the radar,
switching on and off in the transmit channel the frequency converter based on analog mixers, the
filter and the corresponding frequency amplifier. In the receive radio and base-band channels as
well as in the passive channel, ADC is used to digitize the input signals for their further
processing. Analogous to DAC, physical universality of the receive channels allows for using
only one ADC in the radar, which is consistent with a combined view of DAC, ADC and FPGA
as a single digital kernel for radar signal processing.
The maximum flow of the raw data in the device in question is defined by the signal
bandwidth and the number of ADC bits. ADC sampling frequency can be up to 1.6 GHz, and its
bit capacity up to 12. Moreover, the ADC is dual-channel that enables dual sampling of the clock
signal or synphased sampling in two analog channels. The described case uses synphased
digitization in cosine and sine analog channels. As a result, the rate of the data flow coming from
the ADC amounts to 12 1.6 109 40 Gbps. Such a rate of the measurement data from
ADC to FPGA is achieved by using two parallel LVDS buses: one bus is used to send samples
through the forward channel, and the other one to send samples through the quadrature channel.
A digital radar signal processing system should include external memory (usually SDRAM
DDR2/DDR3) to store the measurement data. In this case, the processing algorithm is designed
in such a way that the input samples from FPGA transceiver are sent to external dynamic RAM;
after that, as the measurement algorithm is being executed, these data are extracted from the
external memory block. Therefore, the 12-bit measurement recording rate to external memory is
about 40 Gbps. The clock frequency of FPGAexternal memory exchange is 2-3 times lower
than the input transceivers clock frequency. Therefore, to ensure the recording of all
measurement data into the external RAM one needs either to increase the number of external
memory blocks and then demultiplex the input samples in series, or to form and code a memory
write 24-36 sample word. The most acceptable alternative to build the interface between the
system and the control computer is the PCIe protocol, which is a scalable high-speed serial
input-output bus.
Terrain sensing in the proposed system is realized with an electronically scanned phased
antenna array. Because of the relatively low signal frequency and the antenna size limitation due
to the airborne application, there is a need for specialized secondary processing algorithms to
achieve a high angular resolution. The approach used to enable radar sensing and terrain
characterization with high angular resolution is based on compression of the sensing signal. It
implies the building of a regularized model of the terrain and expected echo signals based on the

a priori information. After comparison with the real measurement results, the parameters are
optimized to provide maximum adequacy of the received response to the expected echo-signal.
Depending on the particular radar configuration, the phased antenna array with electronic
beam-steering and algorithms of high angular resolution reconstruction are used for both active
and passive radio channels in a wide-band sensing range. At the same time, a high spatial
resolution base-band antenna array has a much larger size, so instead of it a wideband horn
antenna can be used which looks at nadir and gives relevant information only in close proximity
to the surface. Nevertheless, in the case of landing on snow or ice, even base-band signals,
acquired with the horn antenna, have a significant information about the surface thickness and
stratigraphy, which, combined with the passive channel data, can help the pilot to decide whether
the landing at this particular spot is safe or not.
Therefore, different channels independently provide different radar sensing data: the active
radio channel gives information about the terrain and the objects on the terrain surface; the
passive radio channel enables the measurement of terrain physical properties (density, water
content, etc.); the base-band channel provides a see-through capability into the terrain surface.
All these results should be analyzed together with regard to mutual correlations, that is building
and calibration of a regularized model of one channel data should imply using as an a priori
information the raw data from one or both other channels. For example, one can use correlations
between the ice layer thickness and the height of hummocks on the ice surface, stratigraphy data
and the effective layer density, terrain features such as hills and cavities and the layer water
content. Another way of combining the information can be the use of image fusion algorithms,
which is particularly effective with uniform sensing at different frequency ranges. The
information from different channels can be shown on the pilots display independently at
different modes or combined together, as shown in Figure 5. In this case, the information is
displayed as two images corresponding to the vertical and horizontal projections. The vertical
projection shows the terrain and the possible targets on its surface, while the horizontal
projection shows the surface stratigraphy and physical properties in the vertical containing the
helicopters construction line.

CONCLUSION
A scalable and reconfigurable architecture for 1.5 GHz bandwidth signal processing and
synthesis has been studied to build universal systems for wideband radar digital signal synthesis
and processing.
Analysis of the described architecture demonstrates a full coverage of functional
characteristics of the radar and its parts and a combination of the system integrity with the
8

capability of highly independent adjustment of key parameters to any particular application. The
radar systems developed using this architecture show to a full extent the isomorphism of laws
and connections, which defines the architectures universality.
An architecture-based airborne radar system has been demonstrated for terrain sensing and
characterization in degraded visual environments with 1.5 GHz bandwidth of synthesized and
processed signals.
ACKNOWLEDGEMENTS
The research has been done through the financial support of the Ministry of Education and
Science of the Russian Federation in the framework of the Federal Target Program Research
and development in the priority fields of Russias research and technology industry 2014-2020;
project ID RFMEFI57614X0041.

Table 1. Radar system parameters.

Parameter
Operating range

Value
1000 m

Frequency range

8-12 GHz

Signal bandwidth
Average radiated power
Field of view
Terrain evaluation precision (RMS)
View interval

1500 MHz
30 W
500500 m
0.2 m
1s

Table 2. Main characteristics of the processing kernel components.

DAC

ADC

Sampling rate 1.425 GHz

Sampling rate

1.6 GHz

Bit capacity

Bit capacity

12 bit

14 bit

Noise density -157

Noise

(850 MHz)

(maximum)

dBm/Hz

Interface

LVDS

Power

1.3 W

Power

10

elements
Memory
units

228 K
17133 K
1288

multipliers

(18x18

58.2 dB

I/O blocks

bit)
744

3.5 W

PLL

dBm/Hz

(498 MHz)

Logical

Internal

density -154.6

SNR

FPGA

Figure 1. Diagram of a radar system.

Figure 2. Diagram of a DSP blocks.
Figure 3. Prototype of the system (off-the-shelf components).
Figure 4. Results of convolution of pseudorandom binary phase-coded signal.
Figure 5. Visual representation of the radar data (top horizontal view, bottom vertical view,
red line axis of a vertical section plane).

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Biography: S. A. Ermushev was born in Kishinev, Moldova, in 1965. He received his M.D. in
engineering in 1990. In 2005, he found an innovative company for signal processing and data
analysis OOO Klasteck, LLC. His current research interests include radar signal processing,
HDL programming, databases and big-data analysis.

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Figure 1

Figure 2

Figure 3

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Figure 4

Figure 5

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