PD - 96902C

IRFB4410
IRFS4410
IRFSL4410
Applications
l High Efficiency Synchronous Rectification in SMPS
l Uninterruptible Power Supply
l High Speed Power Switching
l Hard Switched and High Frequency Circuits

HEXFET Power MOSFET

D

Benefits
l Improved Gate, Avalanche and Dynamic dV/dt
Ruggedness
l Fully Characterized Capacitance and Avalanche
SOA
l Enhanced body diode dV/dt and dI/dt Capability

VDSS
RDS(on) typ.
max.
ID

100V
8.0m:
10m:
96A

D
S
D
G

S
D
G

D2Pak
IRFS4410

TO-220AB
IRFB4410

TO-262
IRFSL4410

Absolute Maximum Ratings

Symbol
ID @ TC = 25C
ID @ TC = 100C
IDM
PD @TC = 25C
VGS

Parameter

Pulsed Drain Current

Maximum Power Dissipation
Linear Derating Factor
Gate-to-Source Voltage
Peak Diode Recovery
Operating Junction and
Storage Temperature Range
Soldering Temperature, for 10 seconds
(1.6mm from case)
Mounting torque, 6-32 or M3 screw

dv/dt
TJ
TSTG

Avalanche Characteristics
EAS (Thermally limited)
IAR
EAR

Single Pulse Avalanche Energy

Avalanche Current
Repetitive Avalanche Energy

c

Max.

Units

96
68
380
250
1.6
20
19
-55 to + 175

c
c

Continuous Drain Current, VGS @ 10V

Continuous Drain Current, VGS @ 10V

W
W/C
V
V/ns
C

300

10lb in (1.1N m)

220
See Fig. 14, 15, 16a, 16b

mJ
A
mJ

Thermal Resistance
Symbol
RJC
RCS
RJA
RJA

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Parameter

Junction-to-Case
Case-to-Sink, Flat Greased Surface , TO-220
Junction-to-Ambient, TO-220

Junction-to-Ambient (PCB Mount) , D2Pak

jk

Typ.

Max.

0.50

0.61

62
40

Units
C/W

1
05/02/07

IRFB4410/IRFS4410/IRFSL4410

Static @ TJ = 25C (unless otherwise specified)

Symbol

Parameter

V(BR)DSS
V(BR)DSS/TJ
RDS(on)
VGS(th)
IDSS

Drain-to-Source Breakdown Voltage

Breakdown Voltage Temp. Coefficient
Static Drain-to-Source On-Resistance
Gate Threshold Voltage
Drain-to-Source Leakage Current

IGSS

Gate-to-Source Forward Leakage

Gate-to-Source Reverse Leakage
Gate Input Resistance

RG

Min. Typ. Max. Units

100

2.0

0.094
8.0
10

4.0

20
250
200
-200
1.5

Conditions

V VGS = 0V, ID = 250A

V/C Reference to 25C, ID = 1mA
m VGS = 10V, ID = 58A
V VDS = VGS, ID = 150A
A VDS = 100V, VGS = 0V
VDS = 100V, VGS = 0V, TJ = 125C
nA VGS = 20V
VGS = -20V
f = 1MHz, open drain

Dynamic @ TJ = 25C (unless otherwise specified)

Symbol
gfs
Qg
Qgs
Qgd
td(on)
tr
td(off)
tf
Ciss
Coss
Crss
Coss eff. (ER)
Coss eff. (TR)

Parameter

Min. Typ. Max. Units

Forward Transconductance
Total Gate Charge
Gate-to-Source Charge
Gate-to-Drain ("Miller") Charge
Turn-On Delay Time
Rise Time
Turn-Off Delay Time
Fall Time
Input Capacitance
Output Capacitance
Reverse Transfer Capacitance

120

Effective Output Capacitance (Energy Related)

Effective Output Capacitance (Time Related)

120
31
44
24
80
55
50
5150
360
190
420
500

180

S
nC

ns

pF

Conditions
VDS = 50V, ID = 58A
ID = 58A
VDS = 80V
VGS = 10V
VDD = 65V
ID = 58A
RG = 4.1
VGS = 10V
VGS = 0V
VDS = 50V
= 1.0MHz
VGS = 0V, VDS = 0V to 80V
VGS = 0V, VDS = 0V to 80V

g
g

i, See Fig.11
h, See Fig. 5

Diode Characteristics
Symbol
IS

Parameter

Min. Typ. Max. Units

Continuous Source Current

VSD
trr

(Body Diode)
Pulsed Source Current
(Body Diode)
Diode Forward Voltage
Reverse Recovery Time

Qrr

Reverse Recovery Charge

IRRM
ton

Reverse Recovery Current

Forward Turn-On Time

ISM

d

96

MOSFET symbol

380

showing the
integral reverse

S
p-n junction diode.

1.3
V TJ = 25C, IS = 58A, VGS = 0V
VR = 85V,

38
56
ns TJ = 25C
T
=
125C
I

51
77
J
F = 58A
di/dt
= 100A/s

61
92
nC TJ = 25C
TJ = 125C
110 170

2.8

A TJ = 25C
Intrinsic turn-on time is negligible (turn-on is dominated by LS+LD)

Notes:
Calculated continuous current based on maximum allowable junction
temperature. Package limitation current is 75A.
Repetitive rating; pulse width limited by max. junction
temperature.
Limited by TJmax, starting TJ = 25C, L = 0.14mH
RG = 25, IAS = 58A, VGS =10V. Part not recommended for use
above this value.
ISD 58A, di/dt 650A/s, VDD V(BR)DSS, TJ 175C.
Pulse width 400s; duty cycle 2%.

Conditions

Coss eff. (TR) is a fixed capacitance that gives the same charging time
as Coss while VDS is rising from 0 to 80% VDSS .

Coss eff. (ER) is a fixed capacitance that gives the same energy as
Coss while VDS is rising from 0 to 80% VDSS .

When mounted on 1" square PCB (FR-4 or G-10 Material). For recommended
footprint and soldering techniques refer to application note #AN-994.

R is measured at TJ approximately 90C.

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IRFB4410/IRFS4410/IRFSL4410
1000

1000

ID, Drain-to-Source Current (A)

TOP

100
BOTTOM

10

1
4.5V

TOP

ID, Drain-to-Source Current (A)

VGS
15V
10V
8.0V
6.0V
5.5V
5.0V
4.8V
4.5V

100
BOTTOM

4.5V

10

60s PULSE WIDTH

60s PULSE WIDTH

Tj = 175C

Tj = 25C

0.1
0.1

10

1
100

1000

0.1

V DS, Drain-to-Source Voltage (V)

10

100

1000

Fig 2. Typical Output Characteristics

1000

3.0

RDS(on) , Drain-to-Source On Resistance

(Normalized)

ID, Drain-to-Source Current ()

V DS, Drain-to-Source Voltage (V)

Fig 1. Typical Output Characteristics

100
T J = 175C
10
T J = 25C
1
VDS = 25V
60s PULSE WIDTH
0.1

ID = 58A
VGS = 10V

2.5

2.0

1.5

1.0

0.5

10

-60 -40 -20 0

Fig 4. Normalized On-Resistance vs. Temperature

Fig 3. Typical Transfer Characteristics

100000

12.0

VGS = 0V,
f = 1 MHZ
C iss = C gs + C gd, C ds SHORTED
C rss = C gd

VGS, Gate-to-Source Voltage (V)

ID= 58A

C oss = C ds + C gd

10000
Ciss

1000

20 40 60 80 100 120 140 160 180

T J , Junction Temperature (C)

VGS, Gate-to-Source Voltage (V)

C, Capacitance(pF)

VGS
15V
10V
8.0V
6.0V
5.5V
5.0V
4.8V
4.5V

Coss
Crss

100

VDS= 80V
VDS= 50V
VDS= 20V

10.0
8.0
6.0
4.0
2.0
0.0

10

100

VDS, Drain-to-Source Voltage (V)

Fig 5. Typical Capacitance vs. Drain-to-Source Voltage

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20

40

60

80

100

120

QG Total Gate Charge (nC)

Fig 6. Typical Gate Charge vs. Gate-to-Source Voltage

IRFB4410/IRFS4410/IRFSL4410
1000

ID, Drain-to-Source Current (A)

ISD, Reverse Drain Current (A)

1000

100

OPERATION IN THIS AREA

LIMITED BY R DS(on)
100sec

100

T J = 175C

T J = 25C

10

1msec

10msec
10

DC
Tc = 25C
Tj = 175C
Single Pulse

VGS = 0V
1

1
0.0 0.2 0.4 0.6 0.8 1.0 1.2 1.4 1.6 1.8

VSD, Source-to-Drain Voltage (V)

Limited By Package

80
ID, Drain Current (A)

70
60
50
40
30
20
10
0
25

50

75

100

125

150

175

V(BR)DSS , Drain-to-Source Breakdown Voltage (V)

90

1000

125

120

115

110

105

100
-60 -40 -20 0

20 40 60 80 100 120 140 160 180

T J , Temperature ( C )

Fig 10. Drain-to-Source Breakdown Voltage

Fig 9. Maximum Drain Current vs. Case Temperature

2.0

EAS , Single Pulse Avalanche Energy (mJ)

900

1.5

Energy (J)

100

130

T C , Case Temperature (C)

1.0

0.5

0.0

ID
6.7A
9.7A
BOTTOM 58A

800

TOP

700
600
500
400
300
200
100
0

20

40

60

80

100

120

VDS, Drain-to-Source Voltage (V)

10

Fig 8. Maximum Safe Operating Area

Fig 7. Typical Source-Drain Diode Forward Voltage

100

VDS, Drain-to-Source Voltage (V)

Fig 11. Typical COSS Stored Energy

25

50

75

100

125

150

175

Starting T J , Junction Temperature (C)

Fig 12. Maximum Avalanche Energy vs. DrainCurrent

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IRFB4410/IRFS4410/IRFSL4410
1

Thermal Response ( Z thJC )

D = 0.50
0.20

0.1

0.10
0.05
0.02
0.01

0.01

J
1

R2
R2
C
2

Ri (C/W) i (sec)
0.2736 0.000376
0.3376

0.004143

Ci= i/Ri
Ci i/Ri

SINGLE PULSE
( THERMAL RESPONSE )

0.001

R1
R1

Notes:
1. Duty Factor D = t1/t2
2. Peak Tj = P dm x Zthjc + Tc

0.0001
1E-006

1E-005

0.0001

0.001

0.01

0.1

t1 , Rectangular Pulse Duration (sec)

Fig 13. Maximum Effective Transient Thermal Impedance, Junction-to-Case

1000

Allowed avalanche Current vs avalanche

pulsewidth, tav, assuming Tj = 150C and
Tstart =25C (Single Pulse)

Avalanche Current (A)

Duty Cycle = Single Pulse

100

0.01
10

0.05
0.10

Allowed avalanche Current vs avalanche

pulsewidth, tav, assuming j = 25C and
Tstart = 150C.

0.1
1.0E-06

1.0E-05

1.0E-04

1.0E-03

1.0E-02

1.0E-01

tav (sec)

Fig 14. Typical Avalanche Current vs.Pulsewidth

EAR , Avalanche Energy (mJ)

250

Notes on Repetitive Avalanche Curves , Figures 14, 15:

(For further info, see AN-1005 at www.irf.com)
1. Avalanche failures assumption:
Purely a thermal phenomenon and failure occurs at a temperature far in
excess of Tjmax. This is validated for every part type.
2. Safe operation in Avalanche is allowed as long as neither Tjmax nor
Iav (max) is exceeded.
3. Equation below based on circuit and waveforms shown in Figures 16a, 16b.
4. PD (ave) = Average power dissipation per single avalanche pulse.
5. BV = Rated breakdown voltage (1.3 factor accounts for voltage increase
during avalanche).
6. Iav = Allowable avalanche current.
7. T = Allowable rise in junction temperature, not to exceed Tjmax (assumed as
25C in Figure 14, 15).
tav = Average time in avalanche.
D = Duty cycle in avalanche = tav f
ZthJC(D, tav) = Transient thermal resistance, see Figures 13)

TOP
Single Pulse
BOTTOM 1% Duty Cycle
ID = 58A

200

150

100

50

0
25

50

75

100

125

150

175

Starting T J , Junction Temperature (C)

Fig 15. Maximum Avalanche Energy vs. Temperature

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PD (ave) = 1/2 ( 1.3BVIav) = DT/ ZthJC

Iav = 2DT/ [1.3BVZth]
EAS (AR) = PD (ave)tav

IRFB4410/IRFS4410/IRFSL4410
20

5.0

VGS(th) Gate threshold Voltage (V)

4.5

15

4.0

IRRM (A)

3.5
3.0
2.5
2.0

ID = 150A
ID = 250A
ID = 1.0mA
ID = 1.0A

10

IF = 19A
VR = 85V

T = 25C _____
J
T = 125C ---------J

1.5
1.0
-75 -50 -25

25

50

75 100 125 150 175 200

100 200 300 400 500 600 700 800 900 1000

T J , Temperature ( C )

dif/dt (A/s)

Fig. 17 - Typical Recovery Current vs. dif/dt

Fig 16. Threshold Voltage vs. Temperature

400

20

350
300

15

Qrr (nC)

IRRM (A)

250

10

200
150

IF = 38A
V = 85V
R
T = 25C _____
J
TJ = 125C ----------

IF = 19A
VR = 85V

100

T = 25C _____
J
T = 125C ---------J

50
0

0
100 200 300 400 500 600 700 800 900 1000

100 200 300 400 500 600 700 800 900 1000

dif/dt (A/s)

dif/dt (A/s)

Fig. 19 - Typical Stored Charge vs. dif/dt

Fig. 18 - Typical Recovery Current vs. dif/dt

400
350
300

Qrr (nC)

250
200
150
I = 38A
F
V = 85V
R
TJ = 25C _____

100
50

TJ = 125C ----------

0
100 200 300 400 500 600 700 800 900 1000
dif/dt (A/s)

Fig. 20 - Typical Stored Charge vs. dif/dt

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IRFB4410/IRFS4410/IRFSL4410
D.U.T

Driver Gate Drive

D.U.T. ISD Waveform

Reverse
Recovery
Current

RG

dv/dt controlled by RG
Driver same type as D.U.T.
I SD controlled by Duty Factor "D"
D.U.T. - Device Under Test

VDD

P.W.
Period
VGS=10V

Circuit Layout Considerations

Low Stray Inductance
Ground Plane
Low Leakage Inductance
Current Transformer

D=

Period

P.W.

+
-

Body Diode Forward

Current
di/dt
D.U.T. VDS Waveform
Diode Recovery
dv/dt

Re-Applied
Voltage

Body Diode

VDD

Forward Drop

Inductor
Current
Inductor Curent
ISD

Ripple 5%

* VGS = 5V for Logic Level Devices

Fig 20. Peak Diode Recovery dv/dt Test Circuit for N-Channel
HEXFET Power MOSFETs
V(BR)DSS
15V

D.U.T

RG
VGS
20V

DRIVER

VDS

tp

+
V
- DD

IAS
tp

0.01

I AS

Fig 21a. Unclamped Inductive Test Circuit

LD

Fig 21b. Unclamped Inductive Waveforms

VDS

VDS

90%

+
VDD -

10%

D.U.T

VGS

VGS
Pulse Width < 1s
Duty Factor < 0.1%

td(on)

Fig 22a. Switching Time Test Circuit

tr

td(off)

tf

Fig 22b. Switching Time Waveforms

Id
Vds
Vgs

L
DUT

VCC
Vgs(th)

1K

Qgs1 Qgs2

Fig 23a. Gate Charge Test Circuit

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Qgd

Qgodr

Fig 23b. Gate Charge Waveform

IRFB4410/IRFS4410/IRFSL4410
TO-220AB Package Outline

Dimensions are shown in millimeters (inches)

TO-220AB Part Marking Information

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TO-220AB packages are not recommended for Surface Mount Application.

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IRFB4410/IRFS4410/IRFSL4410
TO-262 Package Outline
Dimensions are shown in millimeters (inches)

TO-262 Part Marking Information

(;$03/( 7+,6,6$1,5//
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3$57180%(5

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IRFB4410/IRFS4410/IRFSL4410
D2Pak (TO-263AB) Package Outline
Dimensions are shown in millimeters (inches)

D2Pak (TO-263AB) Part Marking Information

7+,6,6$1,5)6:,7+
/27&2'(
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www.irf.com

IRFB4410/IRFS4410/IRFSL4410
D2Pak (TO-263AB) Tape & Reel Information
TRR
1.60 (.063)
1.50 (.059)
4.10 (.161)
3.90 (.153)

FEED DIRECTION 1.85 (.073)

1.65 (.065)

1.60 (.063)
1.50 (.059)

11.60 (.457)
11.40 (.449)

0.368 (.0145)
0.342 (.0135)

15.42 (.609)
15.22 (.601)

24.30 (.957)
23.90 (.941)

TRL
10.90 (.429)
10.70 (.421)

1.75 (.069)
1.25 (.049)

4.72 (.136)
4.52 (.178)

16.10 (.634)
15.90 (.626)

FEED DIRECTION

13.50 (.532)
12.80 (.504)

27.40 (1.079)
23.90 (.941)
4

330.00
(14.173)
MAX.

NOTES :
1. COMFORMS TO EIA-418.
2. CONTROLLING DIMENSION: MILLIMETER.
3. DIMENSION MEASURED @ HUB.
4. INCLUDES FLANGE DISTORTION @ OUTER EDGE.

60.00 (2.362)
MIN.

26.40 (1.039)
24.40 (.961)
3

30.40 (1.197)
MAX.
4

Data and specifications subject to change without notice.

This product has been designed and qualified for the Industrial market.
Qualification Standards can be found on IRs Web site.

IR WORLD HEADQUARTERS: 233 Kansas St., El Segundo, California 90245, USA Tel: (310) 252-7105
TAC Fax: (310) 252-7903
Visit us at www.irf.com for sales contact information. 05/07

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11

Note: For the most current drawings please refer to the IR website at:
http://www.irf.com/package/