* A microprocessor unit is generally referred as MPU.

* MPU is designed with ALU, control unit and some count of processing
registers and these registers are used to store the data temporarily during
programme execution.
* Generally different MPUs available are specified like 8 bit, 16 bit, 32 bit
and so on.
* Bit capacity of MPU is defined as the no of bits it can process at a time in
parallel i.e. an 8 bit MPU can perform all 8 bit operations at a time.
* In general, the internal architecture of the microprocessor depends on
the bit capacity of the microprocessor.
* Thu system bus of MPU consist of 3 types of buses known as address
bus, data bus and control bus
* Address signals arc generated by MPU and sent to identify the address of
the memory through address bus and it is unidirectional bus.
* Data bus is used to transfer the data in between memory and MPU.
* Control signals arc generated by MPU and these signals are transferred
in between memory and MPU and used to provide timing for various
operations.
* Control signals are used to perform the required operations.
* MPU can primarily perform 4 operations Memory Read, Memory write, I/0
Read and I/O write and for each operation it generates the appropriate
control signals.
8085 Microprocessor
* It is a 40 pin IC with operating voltage 5 volts
* It is designed with 2 MB and 3.07 MHz frequencies
* Max clock frequency of 8085 is 3.07 MHz (3MHZ)
* Crystal frequency is double to its clock
* 8085 MPU is designed with on chip clock generator i.e. no external
oscillator is required
* 8085 MPU has 74 basic instructions and 246 opcodes
* 8085 supports 5 no. of hardware interrupts and 8 no of software
interrupts

* Hardware interrupts are Trap RST 7.5, RST 6.5, RST 5.5 and INTR
* Trap has the highest priority among all
*But trap has lower priority than DMAC during DMA
* Trap is also known as RST 4.5
* INTR has the lowest priority
* No. of software interrupts for 8085 are 8, and range from RST '0 to RST
7
* Opcode length varies from 1 byte to 3 byte
* Instructions, having the 16 bit address in the given instruction known as
3 byte instructions
Ex: Call 2500H
* Instructions, having the 8 bit data or port address in given instruction is
2 byte instruction
Ex: MVI A, 35H
* Instruction with neither 16 bit address nor 8 bit data is known as 1 byte
instruction
Ex: MOV A, B
* In 8085 MPU, 5 No. of flags are available and these flags are also known
as status flags, known as carry (cy) ; Auxiliary carry (Ac) ; Sign (s) ; parity
(P) and zero (z)
* 8085 MPU has 2 no of 16 bits registers known as program counter (PC)
and stack pointer (SP)
* PC always holds the address of the next instruction to be executed
* SP always holds the address of the top of the stack
* 8085 MPU has 8 bit accumulator and 8 bit flag register, and this
combination is known as
PSW (Program status word)
* 8085 MPU is designed with 6 no. Of general purpose registers along A
and F, these registers are known as B, C; DE and H, L
* These 8 bit general purpose register can be used as 3 no. of 16 bit
Register Pairs when required like BC, DE and HL pairs,

* 8085 MPU has 16 no of address lines and 8 no. of data lines

* Memory size of any MPU depends on the no. of address lines
* Total no. of Memory locations that can be accessed by 8085 MPU is 216 =
64 K = 65536
* In Hex code, the memory ranges from 0000 H to FFFFH
* The lower 8 no of address lines are multiplexed with 8 data lines and
specified as AD0 to AD7
* Multiplexing of address and data lines is used to reduce the hardware
size of MPU
* The no. of Machine cycles required to execute an 8085 MPU instruction
varies from one of five
* Max no of T states for executing instruction are 18 and minimum no of
T states required for executing an instruction are 4
* Max no. of machine cycles required are 5 and minimum one
* T state value depends on the clock frequency
* Group of 'T' states is known as machine cycle
* Group of machine cycles is known as execution cycle

8085 A Microprocessor Functional Diagram

* Total no. of signal pins (40) are divided in to 6 groups

1) Power supply and frequency
2) Serial I/O ports
3) Address Bus
4) Data bus
5) Interrupts and externally initiated signals
6) Status, control and Acknowledge signals
* SID and SOD signals are used for serial communication
* SIM and RIM instructions are used for serial I/O communication
* A.L.E. is used to generate the lower order address lines (A AO)
* S1, S0 and I0/ M signals are called status signals
* RD and WR signals are control signals
* HOLD and HLDA are used for DMA operation

* READY signal is used by the MPU to communicate with slow operating

peripherals
* RESETIN is active low signal to chip Reset
* RESET out signal is used to connect to RESETIN of other inter facing
circuits used in microprocessor based system
* CLOCKOUT of 8085 will be connected to CLOCKIN of other interfacing
ckts used in microprocessor based system to synchronise the operation
with 8085
* S0 and S1 signals are used to indicate the current status of the processor

* The process of getting/reading the opcode from memory to C.P.U is

known as opcode fetch
* By combining the status signals I0/ M with control signals RD and WR we
can generate the following operations. MEMR, MEMW, IOR and I0W

* All software interrupts are vectored interrupts

* Hardware interrupts are of 2 types a) vectored interrupts b) Non vectored interrupts
* RST 7.5, RST 6.5. RST 5.5 and RST 4.5 are called Hardware vectored
interrupts
* INTR is called Hardware non vectored interrupt
* Interrupts vectored address
* TRAP is a non-maskable interrupt and always in enable condition
* RST 7.5, 6.5, 5.5 and INTR are maskable and these interrupts can be
enabled / disabled by El and DI instructions respectively
* RST 7.5, RST 6.5, and RST 5.5 interrupts can be masked unmasked by
using SIM instruction
* RST 7.5 is edge triggered interrupt
* RST 6.5, RST 5.5 and INTR are level triggered interrupts
* TRAP is both level triggered and edge triggered interrupt

* SIM instruction is used for serial output data operation as well as to

mask or unmask different maskable interrupts
* RIM instructions is used for serial input data operations as well as to
read the status of different maskable interrupts
* 8085 MPU has an 8 bit flag Register
* In flag Register; Out of 8 bits, 5 bits are used to represent valid flags and
remaining 3 bits are don't cares
* These flags are set / Reset according to the data conditions in the
accumulator and other Registers
* Flags are affected by the arithmetic and logical operations in the ALU.
* Flags are used to reflect the data conditions in the ALU
* Position of different flags in flag Register
* MSB in the flag Register is used to indicate the sign of the result for
signed data during arithmetical operations and remaining 7 bits are used
to represent the magnitude of the number
* After execution, if sign flag is set it indicate the result is negative, the
result is positive when it is reset
* If zero flag is set, then ALU operation result is zero
* Auxiliary carry flag is used during BCD addition
* AC flag is set when there is a carry from lower nibble to higher nibble
* Parity flag will be set, when the result has an even no. of ones
* Carry flag is also considered as Borrow flag during subtraction operation
* During addition the carry flag is 1 when the result has 9 bits during 8 bit
addition
* Borrow flag is ' 1 ' when the subtraction operation is performed in
between lower value and Higher value
Instruction set:
Instruction set of 8085 MPU can be classified on their operation as the
following Groups
a) Data transfer b) Arithmetical c) Logical d) Branch
e) Machine control

Data transfer instructions:

* These are used to transfer the data in between Register to Register or
from Register to Memory
* No flags will be affected
* Different Mnemonics are M0V, MVI, LXI, LDA, STA. LHLD, SHLD, LDAX,
STAX, XCHG, AND PCHL
Arithmetical Instructions:
* In 8085 the possible operations are Addition, subtraction, increment and
decrement
* 8085 MPU does not support multiplication and divisions operations
* Ac flag is used during the execution of DAA
* For INX and DCX instructions, no flags will be affected
* For INR and DCR, carry flag is not affected
* For DAD operation only carry flags may be affected
* Different Arithmetic mnemonics are ADD, ADI, ADC, SUB, SUI, SBB, SBI,
INR, INX, DCR, DCX, DAD and DAA
Logical instructions:
* During execution flags may be modified
* Carry flag = 0 during AND,'OR, XOR execution
* Only carry flag may be modified during the execution of RLC, RRC, RAL,
STC, CMC,
* Different mnemonics are ORA, ORI, ANA, AID I, XRA, XRI, CMP, CPI, CMA,
AMC, STC, RLC, RAL, RRC, RAR
Branch Instruction:
* These are also called as program control instructions
* These are divided into conditional unconditional
* No flags will be affected
* For executing the conditional Branch instructions it is compulsory to
check the condition of respective flag, assigned in the instruction

* All jump and CALL instructions have 16 bit address

* No address is required for RET instruction
* PCHL is one byte and equivalent of 3 byte Jump instruction
* RST n is one byte and equivalent of 3 byte call instruction
* Un conditional Branch instructions : JMP, CALL, RET, RSTn, (n = 0 to 7)
and PCHL
* Conditional Branch Instructions JZ, JNZ, JC, JNC, JP, JM, JPO, JPE, CZ, CNZ,
JC, CMC, CP, CM, CPO, CPE, RZ, RNZ, RC, RNC, RP, RM, RPO and RPE
Machine control Instructions:
* EI, DI, SIM, RIM, NOP, HLT, OUT and IN; PUSH PSW; POP PSW; LXI SP,
SPHL, XTHL, and STC
* IN and OUT instructions have 8 bit port address
* When PUSH instruction is executed, SP Register content is decremented
by 2
* When POP instruction is executed SP Register content is incremented by
2
* When CALL instruction or RST instruction is executed, SP Register
content is decremented by 2, because current content of PC will be
pushed automatically on the top two locations of the stack.
* When RET instruction is executed, SP register content is incremented by
2, because microprocessor retrieves address from top two locations of the
stack and loaded in to P.C
* Comparison of PUSH and POP instructions with CALL and RET
instructions
ADDRESSING MODES
* It is the process of way locating the operand (data) S
* 8085 MPU supports 5 addressing modes
Implied Addressing mode:
It is also known as implicit or Absolute addressing mode
This addressing mode is used to perform the given operation on the
content of Accumulator

Ex: CMA STC, RRC, RLC, RAR, etc.

Register Addressing mode:
In this the operands are in the general purpose Register
The opcode specifies the address of the Register in addition to the
operation to be performed
Ex: MOV A, B ; ADD B ; SUB C
Immediate Addressing mode:
In this mode the operand is specified in the instruction itself.
Ex: MVI, ADI, ORI, LXI, SBI, SUI, ANT, XRI
Direct Addressing mode:
In this mode; the address of the operand is given in the given instruction
Ex : STA, LDA, SHLD, LHLD, IN, OUT etc
Indirect addressing mode:
In this addressing mode the address of the operand is specified by a
Register Pair.
Ex: STAX, LDAX, ADDM, DCRM
* In indirect addressing mode; HL pair is used as memory pointer
EXECUTION DESCRIPTION
* For executing any instruction fetch machine cycle is compulsory
* For FETCH; most of the instructions require four 'T.' states and some
require 6' T states
* For performing any one operation of memory Read, memory write I/O
Read and I/ write ; Three T states are required
* The following instructions require six T states for Opcode fetch
a) All CALL instructions
b) All conditional R ET instructions
c) INX Rp
d) DCX Rp

e) PCHL
f) SPHL
g) PUSH Rp
h) All Restart instructions
Note: POP and RET (unconditional) require only four T states for fetching
* During the execution of RST instructions, P.C. is modified with the
address which is available in page and allotted for separate address for
each RST type instruction.
* Different types of machine cycles of 8085 are opcode fetch, memory
Read, Memory write; I/0 Read, I/O write, Interrupt Acknowledgement, and
Bus idle cycles
* The first machine cycle of every instruction cycle is always Fetching
* ALE signal is generated during T1 state of each machine cycle
* ALE signal is generated during `T1' state of each Machine cycle
* Machine cycle format is given below

* In the above diagram M stands for machine cycle and 'T' stands for 'T'
states and M is for fetching with the maximum length of-'6' T states
Mapping: Assigning address to I / O devices or memory locations is called
mapping
Memory mapping: Assigning the address of memory locations is called
memory mapping
* Memory mapping can be changed by changing the hardware logic used
for chip selection
* To inter face a memory the 8085, necessary lower order address lines of
8085 address bus are
connected to the address lines of the memory chip and higher order
address lines are decoded to
generated CS (chip select) signal to enable the chip

* Absolute decoding: In this decoding all the address lines which are not
used for memory chip to identify a memory Register must be decoded
thus chip select can be asserted by only one address
* Linear Decoding: In this technic; one address line is used for chip select
(CS), and other are left dont cares; this technic reduces hardware but
generates multiple addresses resulting in fold back memory space.
I/O devices can be connected to microprocessor in two different
techniques:
1) Memory mapped I/O techniques
2) I/O mapped I/O technic
Memory mapped I/O technique:
* In this, the I/O devices are also treated as memory locations under that
assumption they will be given 16 bit address
* In this data bytes are transferred by using memory related data transfer
Instructions
Ex: LDA, STA, MOV A, M; MOV M,A
* In this the input device is connected (key board) instead of memory and
the input device will have the 16 bit address specified by LDA instruction
(When the device is monitor SI A instructions is used)
* In memory mapped I/O MEMR and MEMW control signals are used to
activate I/O devices
* In memory mapped I / O, the entire memory map shared by memory
locations and I/0 devices and
* One address can be used only once
* This technic is used in a system where the no. of I/O devices are more
* The max no. of I/O devices that can be connected to microprocessor in
this technic are 216 = 65536
I/O mapped I/O technique:
* In this; I/O devices are identified by the processor with separate 8 bit
port address

* This technic uses separate control signals (IOR and IOW) to activate I/O
devices and separate instructions (IN and OUT) to communicate with I/0
devices.
* In this, the data bytes are transferred using IN and OUT instructions
* Each IN and Out instructions followed by an 8 bit address of the device
(00H to FFH)
* In this only IN and Out instructions are used.
* In this, I/O mapping is independent of memory mapping and same
address can be used to identify input device and output device
* This technic is used in a system where the no. of I/O devices are less
* By using this method a maximum no. of 256 input devices and 256
output devices can be connected to the processor (total no. of devices to
be connected = 512)
INTERFACING
* It is the process of designing Hardware circuit and writing software
instructions to enable microprocessor to communicate with the peripheral
devices
* There are two basic types of interfacing devices are available
a) Non programmable interfacing devices
b) Programmable inter facing devices
Non programmable inter facing devices: Once the microprocessor system
is designed; it is not possible to program this type of devices.
Example a) 8212 Non programmable I/O port
b) 74 LS 245 bidirectional buffers
c) 74 LS 373 Trans parent Latches
Programmable interfacing devices:
These can be programmed by loading specific binary word known as
control word according to the internal logic.
Different Programmable devices
a) 8155: Programmable interfacing devices with 256 bytes RAM and 16 bit
timer / counter

It is a general purpose interfacing device i.e. it can be used to

interface devices to interface variety of I/O devices to the microprocessor
b) 8255: It has 3 no of ports known as port A, port B, port C
c) 8253: Programmable interval timer and it can work in 6 different modes
Mode 0: Interrupt on terminal count
Mode 1: Programmable one shot
Mode 2: Rate- generator
Mode 3: Square wave generator
Mode 4: Software triggered strobe
Mode 5: Hard ware triggered strobe
d) 8251: Programmable communication interfacing unit. It is called as
USART
e) 8257: Programmable DMA
DMA transfer is an I/O technic used commonly for high speed
data transfer
It has 4 no. of DMA channels
f) 8259: Programmable interrupt controller (PIC)
It is an equivalent to provide 8 INTR control pins on 8085
microprocessor
For connecting 64 I/O devices, no. Of PICs required are 9(one for
master and 8 for slaves)
g) 8272: programmable floppy- disk controller
h) 8275: Programmable CRT controller
i) 8279: programmable Key board and display interfacing circuit
By using this, it is possible to connect 16 seven segment
displays and 64 keys (8 x 8 matrix) to the microprocessor
PERIPHERALS
Programmable Interrupt controller (8259):

* 8086 MPU can Handle the interrupt operation when there is a single I/O
device because it has only one INTR pin
* For connecting multiple I/O devices, an interfacing device is needed
whose function is to determine the priority to handle the multiple interrupt
operations
* This interfacing device is 8259
* One 8259 can handed 8 I/O devices
* For connecting more than 8 I/0 devices, more no. of 8259 s are required
and these are connected in cascading order
Description of 8259:
* IRR is an interrupt Request Register used to store the interrupt request
from the I/O devices connected to the IR input lines
* These IR input lines range from IR0 to IR7
* Priority resolver is a logic circuit used to determine the priority of the IR
input line
* ISR is an 8 bit register used to handle the IR levels having highest
priority i.e. it stores the IR level which is currently under the service
* Control unit controls the entire interrupt operation by providing INT and
INTA signals.
Data bus buffer: It's function is to transfer the data to or from the CPU
Read write logic: It controls the write or Read operation
Cascade buffer: It is used in multiple 8259 system and it's function is to
cascade multiple 8259's
* To perform the operation of 8259 words, it is needed to fill the two types
of command they are
a) initialization command words (ICWS)
b) Operation command words (OCWS)
* ICWS are used to initialize the 8259
* OCWS are used to perform the required operation

DMA CONTROLLER (8257)

* It is used to perform DMA operation in between main memory and I/O
devices
* When faster rate of data transfer is required DMAC is used
* During DMA all the buses are under the control of DMAC instead of MPU
Internal Architecture of DMAC is shown below

* Each DMAC has 4 channels knows as CH0 to CH3

* Each channel has 2 types of signals DMA Request (DREQ) and DMA
Acknowledgement (DACK)
* It is possible connect 4 no. Of I/O devices for each DMA
* There are 2 types of priorities (a) fixed and (b) rotating
* In fixed priority CH0 has the highest priority among all and CH3 has the
lowest priority

* In rotating priority, all channels have equal priorities

* Priority Resolver decides the required priority
* Data bus buffer is used to transfer the data in between MPU and DMAC
* Read write control logic is used to control the required operation to be
performed
* Mode control unit provides the various control signals like HRQ (HOLD),
HLDA, ADSTB, (Address strobe), AEN (Address enable)
* When DMAC is communicating with MPU, then DMAC is said 4 to be in
slave position
* When DMAC is communicating I/0 devices it is said to be in master
position
Different Registers in 8257:
* It has 2 no. of 16 bit channels for each channel namely address register
and terminal count Register
* It has 2 no of 8 bit Registers common for all ; known as mode set
Register and status Register
* 16 bit Register are used for DMA operation
* 8 bit Registers are used for programming the 8257
* Address Register function is to store the starting 16 bit effective address
of the memory from where the data is to be accessed
* Terminal count Register is used to store the Byte number (word length)
i.e. size of the data Block to be accessed from the memory and TC
Register content is decremented by one after completing the one byte
data access.
* When the content in the Terminal count Register reaches to zero i.e. the
data from the memory has been accessed
* When Do to D3 bits any one is set; the corresponding channel is used, it
0' means it is not using
* When D4 bit is enabled, rotating priority is enabled
* When D5 bit is enabled, extended write operation is enabled
* When D6 bit is enabled, Terminal count is enabled

* When D7 bit is enabled, auto load is enabled

Status register format is shown below:
* When any bit from Do to D3 id enabled, the corresponding channel TC has
reached otherwise it has not yet reached
* When D4 is set, CH2 address Register and Terminal count Register
contents are copied to CH3 Address Register and IC Register
USART (8251) (universal synchronous Asynchronous Receiver and
Transmitter):
Its internal Architecture is shown below

Transmitter Buffer: It's functions is to transmit the data to the I/O device
through the Tx0 pin & this includes data bus buffer Register and
Transmitter shift Register
Transmitter control: Its function is to control the data transmitter to the
I/O devices using different control signals like TXRDY TXE & TXC etc.
Receiver buffer: This unit is used to receive data from I/O devices using
different control signals like RXRDY, RYE and RXC etc.

* Data bus buffer function is to transfer the data to/from the CPU though
the data lines Do to D7
* Read/ Write control unit function is to control the Read/ Write operation
during Read/write operation during the serial communications
* MODEM control unit is to control the serial communication by means of
different hand shaking signals like DTR, DSR, RTS and CTS
DTR: Data terminal Ready
DSR: Data set Ready
RTS: Request to send
CTS: Clean to send
Different Registers in 8251:
* It had 4 no. Of registers and each capacity 8 bit
* Different registers are mode register, command register, status register
and synchronous register
* Synchronous register is used to hold the sync character and remaining 3
registers are used for programming 8251
Mode Register Format:
* B1 B0 combination is used to specify the baud rate as shown below
* L1 L0 used to specify the character length as shown below
L 1 L0

Character length

0 -

5 bit

1 -

6 bit

0 -

7 bit

1 -

8 bit

* S1 S0 combination is used to specify the stop bits length

S1 S0

No of stop bits

0 -

invalid

1 -

1 bit

0 -

11/2 bit

1 -

2 bit

* D4 is used to enable the parity

* D3 is used to enable the even parity

Command Register Format:

* Do is used to enable transmission
* D1 is used to enable Data terminal Ready pin
* D2 is used to enable Receiption
* If D3 is set then it forces TXD low
* When D4 is Set it resets all Error flags
* D5 is used to enable Request to send pin
* In D6 is used for internal Reset
* D7 is set for searching the synchronous character
Status register: Its format is shown below
* Do is set when it is ready to accept the data character from the CPL
* When D1 = 1, then indicates that 8251 has received a data from I/O and
is ready to transfer to CPU
* When D2 = 1, then indicates that transmitter buffer is empty
* When D3 is set, then parity error occurs
* When D4 is set, then an over run error occurred
* When D5 is set, then framing error occurred
* When D6 is set, that indicates; sync character has been received
* When DSR is set, that indicates that data set is ready
PROGRAM11ABLE PERIPHERAL INTERFACE (PPI)
8255
* It is used for Parallel communication
* It is used between CPU and peripheral to avoid speed mismatching

Internal Diagram of 8255 is shown below

* It has 3 ports namely port A (PA), port B(PB) and port C (PC)
* These ports are used mainly for data transfer between I/O devices and
CPU
* In some cases PC is used to provide the control signals so, this port is
called as control port
* Again these 3 ports are divided in to 2 Groups namely Group A (GR-A)
and Group B (GR- B)
* Group A known as port A and PC upper (PC7 = PC4) and Group B is known
as port B and PC lower (PC3 PC0)
* These PA and PB and Pc are 8 bit ports and used for I/O operation
* Group A control unit is used to control the operation of Gr - A i.e. port A
and PCH
* Group B control unit is used to control the operation of port B and PCL
* Data bus buffer unit is used to transfer the data to / from the CPU

* Read / Write control logic unit is used to control the entire I/O operation
between the CPU and I/0 devices also Read/write operations.
Operational modes of 8255:
* It can be operated in 2 no. Of modes known as BSR(Bit set and Rest
mode) and I/O mode (input and output mode)
* However, the operation mode of 8255 is determined by control register,
which is an 8 bit register
* Control Register can be programmed as per the requirement
* When MSB in the control Register is 0' it indicates, 8255 is operating in
BSR mode ; then the data in the control Register ranges from 00H to 7FH
* When MSB in the control Register is '1 then it indicates 8255 is
operating in I/O mode
BSR mode operation
* This mode is used to program only Pc
* It is used to set/Reset the required bit port c
Control Register for mat for BSR mode

* Do is used to set i Reset respective bit

* D3, D2, D1 are used to specify the required bit in port C as shown below
D3 D2 DI

bit to be set / Reset

0 0 0

PCo

0 0 1

PC1

* D7 is used to indicate the operation mode

* Do, and D4 don't cares
I/O mode operation
* In this mode; 8255 is used for I/O operation

* In this mode any port can be programmed

* It has again 3 modes known as mode 0, model and mode 2
Control Register format in I/O mode is shown below

Mode 0 operation:
* In this all ports are I/O ports
* No hand shaking signals
* In this PA PB and PC can be operated independently
Mode 1 operation:
* In this only PA and PB are used as I/O ports
* PC is used for generating control signals
* In this PCH is used provides the control signals for PA and PCL is used for
providing the control signals for PB
Mode 2 operation:
* In this mode only PA is used for I/O operation hence it is bidirectional port
* PB cannot be operated in this mode
* In this PCH is used for providing control signals for port A
PROGRAMMABLE TIMER/COUNTER:
* It is used to generate accurate time delays
* 8253/8254 known as programmable timer/counter
* Each one contains 3 no of 16 bit counters
* Clock frequency range is 8 Hz to 10 MHZ for 8254
Description about 8254:

* It has an 8 bit data bus for interfacing with CPU data lines
* CS input which will be asserted by an address decoder when the device
is addressed
* It has 2 no. of address inputs known as A and Ao allow to address one of
the 3 counters or the control \vord Register in the device as follows
A1 Ao

Selects

Counter 0

Counter 1

Counter 2

C. W. R

* Each counter has 3 types of signals known as CLK GATE and OUT
* GATE input on each counter allows you to start or stop the counter with
an external Hardware signals
* The required clock signals is applied to the clock input for the specified
counter
* The output signal from each counter appears on its OUT pin
* All counters are down courtiers, i.e. the number in the counter will be
decremented by each clock pulse
* RD and WR used for perform the required Read or write operation
* 8254 has an 8 bit control Register (CWR) and it is used to program the
counter as per our requirement
* CWR accepts only writing operation and it is not possible to read the
CWR
* Each counter in 8253/54 works independently
* Each of three counters of 8253/54 can be operated in one of the
following six modes of operation
a) Mode 0 (Interrupt on terminal count) a ;
b) Mode 1 (Programmable mono shot)
c) Mode 2 (Rate Generator)
d) Mode 3 (square wave Generator)

e) Mode 4 (software triggered strobe)

f) Mode 5 (Hardware triggered strobe)
Control Word Register for mat
* SC1 and SC0 used to select the required counter as follows

* RL1 and RL0 programming is followed

* M2 M1 and M0 are used to specify the mode selection

Mode '0' (interrupt on Terminal count):

* Initially the OUT signal is low
* Once a count is loaded in the Register, the counter is decremented for
every clock cycle and when the count reaches to zero, the output goes
high and this can be used as interrupt
* The OUT remains high until a new count or command word is loaded
MODE 1 (programmable mono shot):
* In this mode; the OUT is initially High
* When the GATE is triggered the OUT goes low and at the end of the
count the OUT goes high again, thus generating a one shot pulse
MODE 2 (Rate Generator):
* This mode is used to generate a pulse equal to the clock period at a
given interval.
* When a count is loaded; the OUT stays high until the count reaches 1,
and then the OUT goes low for one clock period
* The count is reloaded automatically, and the pulse is generated
continuously
* The count = 1 is illegal in this mode
MODE 3 (Square wave Generator):
* When a count is loaded, the OUT is high

* The count is decremented by two at every clock cycle and when it

reaches zero, the OUT goes low and the count is reloaded again
* This is repeated continuously, thus a continuous square wave with
period equal to the period of the count is generated
* In other words; the frequency of square wave is equal to the frequency
of the clock divided by the count
Mode 4 (Software triggered strobe):
* In this mode, the OUT is initially high; it goes low for one clock period at
the end of the count
* The count must be reloaded for subsequent outputs
MODE 5(Hard ware triggered strobe):
* It is similar to mode 4, except that is triggered by the raising pulse at the
gate
* Initially the OUT is low, and when the GATE pulse is triggered from low to
high, the count begins
* At the end of the count, the OUT goes low for one clock period.
8155
Features:
* 2K bits static RAM 256x8
* 2 programmable 8 bit I/O ports
* 1 programmable 6 bit I/0 ports
* 1 programmable 14 bit binary counter/timer
* Internal address latch to demux ADO-AD7, using ALE line

* DO, D1: mode for PA and PB, 0=i/p, 1=o/p

* D2, D3: mode for PC
* D4, D5: interrupt enable for PA and PB, 0=disable 1=enable
* D6, D7: Timer command: o
00: No effect

01: Stop if running else no effect

10: Stop after terminal count (TC) if running, else no effect
11: Start if not running, reload at TC if running.
Port C bits (D2, D3):

D6: Timer Latched high when TC is reached, low when status reg is read or
reset is done

M2, M1: Mode bits:

* 00: single square of wavelength TC/2 (TC/2, TC/2 if TC even; [TC + 1/2],
[TC-1/2] if TC odd)
* 01: square waves of wavelength TC (TC/2, TC/2 if TC even; [TC+1/2], [TC1/2] if TC odd)
* 10: single pulse on the TC th clock pulse
* 11: single pulse on every Cth clock pulse
Mode 0: single square wave

Mode 1: Continuous square wave

Programmable Keyboard/Display interface - 8279

* A programmable keyboard and display interfacing chip. Scans and
encodes up to a 64-key keyboard. Controls up to a 16-digit numerical
display. Keyboard section has a build in FIFO 8 character buffer. The
display is controlled from an internal 16x8 RAM, that stores the coded
display information.
Pinout Definition 8279
AO: Selects data (0) or control/status (1) for reads and writes between
micro and 8279.
BD: Output that blanks the displays.
CLK: Used internally for timing. Max is 3 MHz.

CN/ST: Control/strobe, connected to the control key on the keyboard.

CS: Chip select that enables programming, reading the keyboard, etc.
DB7-DBO: Consists of bidirectional pins that connect to data bus on micro
IRQ: Interrupt request, becomes I when a key is pressed, data is available.
OUT A3-AO/B3-BO: Outputs that sends data to the most significant/least
significant nibble of display.
RD (WR): Connects to micro's TORD or RD signal, reads data status
registers.
RESET: Connects to system RESET.
RL7-RLO: Return lines are inputs used to sense key depression in the
keyboard matrix.
Shift: Shift connects to Shift key on keyboard.
SL3-SLO: Scan line outputs scan both the keyboard and displays.

* The Keyboard matrix can be any size from 2x2 to 8x8

* Pins SL2-SLO sequentially scan each column through a counting
operation. The 74LS138 drives O's on one line at a time. The 8279 scans
RL pins synchronously with the scan. RL pins incorporate internal pull-ups,
no need for external resistor pull ups

First three bits given below select one of 8 control registers (opcode).
* 000DDMMM
Mode set: Opcode 000.
DD sets displays mode.
MMM sets keyboard mode.
DD field selects either:
(i) 8 or 16 display position.

ii) Whether new data are entered to the rightmost or leftmost display
position

Encoded: SL outputs are active-high, follow binary bit pattern 0-7 or 0-15.
Decoded: SL outputs are active-low (only one low at any time). Pattern
output: 1110, 1101, 1011, 0111.
Strobed: An active high pulse on the CN/ST input pin strobes data from
the RL pins into an internal FIFO for reading by micro later.
2-key lockout/N- key rollover: Prevents 2 keys from being recognized if
pressed simultaneously/Accepts all keys pressed from first to Last.
ADC 0808
* 8 bit ADC
* Interfaces micro-controller ports or processor DO-D7, RD WR ALE (built
in latch) for channel select through AD2- AD1-ADO inputs
* Start of conversion (SOC ) using WR
* SOC input very short duration (ns) pulse using a NOT-NAND combination
* Output enable for converted bits on DO-D7 using RD
* EOC output for end of conversion to facilitate interrupt (INTR) driven IO
* Separate analog and digital grounds to separate digital transitions noise
by direct connection of A-GND to supply GND
* Clock frequency input

DAC 0800
* To convert digital values to analog voltages
* Performs inverse operation of the Analog to Digital Converter (ADC)

The DAC0800 series are monolithic 8-bit high-speed current-output digitalto-analog converters (DAC) featuring typical settling times of 100 ns.
When used as a multiplying DAC, monotonic performance over a 40 to 1
reference current range is possible.

The DAC0800 series also features high compliance complementary current

outputs to allow differential output voltages of 20 Vp-p with simple resistor
loads as shown in Figure 1
The reference-to-full-scale current matching of better than + LSB
eliminates the need for full-scale trims in most applications while the
nonlinearities of better than + 1% over temperature minimizes system
error accumulations.
The noise immune inputs of the DAC0800 series will accept TTL levels with
the logic threshold pin, VLC, grounded.
Changing the VLC potential will allow direct interface to other logic
families.
The performance and characteristics of the device are essentially
unchanged over the full 4.5V to 18V power supply range; power
dissipation is only 33 mW with 5V supplies and is independent of the
logic input states.
The DAC0800, DAC0802, DAC0800C and DAC0802C are a direct
replacement for the DAC-08, DAC-08A, DAC-08C, and DAC-081-1,
respectively.
Features:
* Fast settling output current 100ns
* Full scale error: 1 LSB
* Nonlinearity over temperature 0.1%
* Full scale current drift: 10 ppm/0C
* High output compliance: -10V to +18V
* Complementary current outputs
* Interface directly with TTL, CMOS, PMTS and others
* 2 quadrant wide range multiplying capability
* Wide power supply range: +4.5V to 18V
* Low power consumption: 33 mW at 5V
* Low cost
MICROPROCESSOR - 8086

8086 Microprocessor internal Architecture:

* It is a 16 bit processor and designed with 20 address lines
* Operating voltage is 5 volts
* Three versions of clocks 5 MHz, 8 MHz and 10 MHz,
* As no. of address lines = 20; its memory space = 1 MB i.e. each one
memory location can store 1 byte data
* During memory operations if the first byte of a word is at even address,
the MPU read the entire word in one operation (cycle)
* During memory operations; if the first byte of a word is at odd address;
the MPU can read the entire word in 2 operations (cycle)
* The internal Architecture is divided into 2 parts a) Bus interface unit
(BIU) and execution unit (EU)
* The 8086 MPU has Register as follows (each with 16 bit)
4 no of segment registers(CS, DS, SS, ES)
4 no of general purpose Register (AX, BX, CX, DX)
3 no. of pointing Registers (IP, BP, SP)
2 no. of Index Registers and (SI, DI) and a Flag Register
* Flag Register is also known as program status word PSW
Bus interface unit (BIU):
The BIU sends out the address, fetches the instructions from memory,
Read and write data in to memory and ports
The Queue:
*To perform any operation, the BIU first sends out address and fetches the
instruction from memory and during this time the EU remains idle
* This queue register is used to pre fetch the instruction to speed up the
execution
Execution unit: It is used decode the Instruction and executes the same
* During execution; the 2 buses (address and data buses) will remain idle
* So, at any given time either BIU or EU is Function

* In 8086 MPU, the maximum length of opcode is 6 byte so, queue register
is maintained at 6 bytes
* Fetching the next instruction while the current instruction being
executed is known as pipelining and it is used to increase the execution
speed
* In 8086, the segment Registers are used to store the higher order 16 bit
address in given 20 bit address
* 20 bit address is also known as physical address
* lower 16 bit address is known as offset address
* The Registers used for storing the offset address is known as offset
Registers
* Different offset Registers are SI, DI, IP, BP, SP and BX
* Segment Registers are also known as base Registers
* 1MB memory that can be accessed by 8086 MPU is divided into 16
logical segments with each segment capacity of 64k i.e. only 16 address
lines are sufficient to access one logical segment e
* The segments can be located anywhere of the memory
* What ever the no. of segments the 8086 MPU can operate only on 4
segments at a time ; these segment are CS, DS, SS and ES
Code segment (CS): This part of the memory is used for storing the
program (opcode)
Data segment: This Part of the memory is used for storing the operand
(data)
Extra segment: This part of the memory is used during the execution of
string instructions.
Stack segment: This part of the memory is used for storing the address
and data while a sub program is executing
Instruction pointer (IP): It used to store the address of the opcode,
when the program address is 20 bit CS, IP Register Pair is used for storing
the same
Control system: It is used to generate necessary timing and control
signals for various internal operations.

Instruction Decoder: It decodes the instruction fetched from memory in

to series of ions which the execution unit will carry out
Arithmetic and logic unit (ALU):
* Its capacity is 16 bit
* It is used to perform different arithmetical and logical operation like
addition subtraction multiplication division AND. OR & NOT
Flag Register:
* It is also known as PSW
* It is the group of different flags with 16 bit capacity
* Valid flags are 9 and remaining 7 are don't cares
* These valid flags are divided in to 2 Groups a) Conditional flags - 6 b)
Machine control flags- 3
* Conditional flags are carry (cy0) Auxiliary carry, parity, sign, zero and
over flow
* Machine control flags are Trap flag, Interrupt flag and Direction flag
* Conditional flags reflect the result of any arithmetical or logical
operation
* Machine control flags are used by the programmer to control the MPU
* Carry flag may set during addition operation when the result has one
more bit
* Carry flag is treated as borrow flag : it sets when the subtraction
operation is perfonned in between lower value and higher value
* Zero flags sets when the entire operation value is zero otherwise it
resets
* Parity flag is set when the 8 bit result has even no. of ones count other
wise resets
* Sign flag sets when the MSB is '1' during signed data operations
* Auxiliary carry (AC) flag sets when there is a carry from lower nibble to
Higher nibble and it is used during BCD addition
* Over flow flag : It will be set if the result of a signed operation is too
large to fit in to be numbers of bits available to represent it

* control flags are set or Reset by the user

* Direction flag is used in string operation ; if it is set the address of SI and
DI is decremented ; when it is reset ; the same SI and DI Register are
incremented by one
* Interrupt flag is used to either recognize the interrupts recognized by the
CPU or the all interrupts
* When interrupt flag is Reset all the interrupts are ignored, Trap flag is
used in single stepping execution and this flag is used when the program
is voted in Debug mode
* Bit position of different flags in PSW

General Purpose Registers:

* There are 4 no. of 16 bit Register and these are divided in to 8 no. of 8
bit Register as follow

X stands for 16 bit width

* 'AX' is known as accumulator Register and it is compulsory used during
the execution of some instructions like MUL and DIV
* 'BX' Register is known as Base Register in most cases BX Register can be
used as data Register and in some cases it can be used as address
Register
* 'CX' Register is also known as count Register and it is automatically
decremented by one when loop instructions is executed once
* 'DX' Register is known as data Register and it is used to bold the higher
order data during multiplication and division operations when the result is
more than 16 bit.
* DX register is also used to hold the I/O address during inter facing
* SP is a 16 bit Register used to hold the offset address of the stack (stack
is a group of memory locations defined by the user)