Professional Documents
Culture Documents
Forsmark Event
Forsmark Event
Loss of secured power in NPP Forsmark on 25. July 2006
Asymmetrical voltage drop in AC supply of rectifiers for about 300ms followed by an overshoot of about 20 % caused a
high DC voltage condition which tripped the connected inverters
Forsmark Event
Thyristor Rectifier topology
Conducted thyristors cannot be switched off instantaneously (only at zero crossings)
Mains voltage quality detection is normally slow and insensitive
Internal DC power storage capacity (capacitors) is limited
Connected batteries do not help for fast transients
+
0o
Mains
30o
+
To
Inverter
-
Forsmark Event
How to manage / prevent DC overshoots ?
Apply a good rectifier mains quality detection scheme
Secure selectivity between rectifier- and inverter high-DC shutdown levels
high
hi h DC
C level
l
l inverter
i
> 1.1 x high
hi h DC
C level
l
l rectifier
ifi
Allow enough design headroom for associated DC components
Make sure that auxiliary circuits (internal power supply units) withstand the
elevated DC levels
Control
C
t l and
d Manage
M
the High-DC Event
Bypass Input
Rectifier Module
DC SSecured
Load
d Bus
Rectifiier Input
- Max. 280VDC
Inverter Module
Inverter
Battery
Delay:
- Voltage error: typ. 100ms with 50% drop
- Missing phase: typ. 100ms
- Frequency: 100ms fixed
- Sync. error: 3ms fixed
Restart:
R
t t
Automatic if back in tolerance
Static Switch
Circuit Type:
yp Analogue
g comparator
p
with
programmable reference voltage.
Loads
Action: DC
Shutdown
of Inverter
Delay: 3ms fixed
Restart: Manual (if bypass unavailable)
Programming range: up to 340VDC
Recommended Setting for 220VDC:
Auto-Transformer
10
11
12