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ISSCC97 I SESSION 4 I DRAM I PAPER TP 4.5

TP 4.5: A 256Mb SDRAM Using a Register-Controlled
Digital DLL
Atsushi Hatakeyama,Hirohiko Mochizuki, Tadao Aikawa, Masato Takita,
Yuki Ishii, Hironobu Tsuboi, Shin-ya Fujioka, Shusaku Yamaguchi,
Makoto Koga, Yuji Serizawa, Koichi Nishimura, Kuninori Kawabata,
Yoshinori Okajima, Michiari Kawano, Hideyuki Kojima, KazuhiroMizutani,
Toru Anezaki, Masatomo Hasegawa, Masao Taguchi
Fujitsu Limited, Kawasaki, Japan
This 256Mb synchronous DRAM with I n s clock access is stable
against temperature, voltage, and process variation by use of an
innovative register-controlled delay locked loop (RDLL). Unlike
most conventional high-density DRAMs, the bit-lines are placed
above the storage capacitors in this DRAM t o relax design rules
of the core area. The noise issues are analyzed and resolved to help
implement the technology in mass production of 0.28 t o 0.24pm
200MHz DRAMs.
Figure 1shows the block diagram of a n RDLL. The configuration
consists of a variable-delay generator (delay line) with a logic-gate
chain, a shift register for indicating the optimal tap point in the
chain, a phase comparator for comparing the internal clock and
the external clock phase that differ by one cycle, and a set of
replica circuits for simulating a delay in the internal clock path.
The replica circuits include a n output buffer with a dummy
capacitance and a loop circuit that automatically tracks the
external clock. Therefore, data output coincides with the rising
edge ofthe external clock and is independent of ambient temperature and process parameters, etc. Similar results are achieved
with a synchronous mirror delay [l]. However, the timing resolution is much higher with RDLL because the fan-out of the delay
unit in the logic-gate chain is made one, minimizing quantization
errors. The tap point on the delay line is indicated by a highlogic
state in the corresponding shift register controlled by the phase
comparator (Figure 2a). The frequency of the external clock is
divided into eighths and logically configured to match the internal
clock, designated as Ain the figure. In the phase comparator
block, comparator 1logically compares the states of the external
clock and the internal clock, and comparator 2 compares the
external clock and the one-unit-delayed internal clock controlling
the shift register to position external clock Amidway between
clocks B and C (Figure 2b). A drawback of this scheme is the
comparatively long lock-on time (100 cycles after the power-on
sequence) needed to adjust the delay tap. This, however, poses no
serious problem in terms of system operation.
Figure 3 shows the Schmoo plot of access time (tAC) versus cycle
time (tCLK). The magnified section shows that the quantization
error is r100ps. The RDLL block has its own regulated power
supply and the substrate is grounded so the error is independent
of both internal and external noises. Waveforms in 167MHz
operation indicate that the clock access time is I n s (Figure 4).
Other timing schemes are also possible, for example, shifting the
data-out signal by 180 relative t o the external clock by the
addition of a phase shifter composed of a similar RDLL. The area
required to accommodate the RDLL is about 0.1% of chip. The
power is only 3mAx 3.3V a t room temperature because the entire
RDLL circuit is digital. RDLL is designed to shut down in powerdown mode.

The chip internal voltage is regulated to 2.5V to accommodate the

0.24pm process. For adequate margin for low-supply voltage
operation, low-threshold transistors, in a triple-well with zeroback bias, are used for sense-amplifiers and the related circuitry.
Peripheral logic circuits are assembled from transistors built in a
conventional p-well to attain a higher-threshold voltage. Lowthreshold transistors are also used for column-selecting gates to
compensate for the decrease in channel conductivity at increased
source voltages. In addition, the transistors share a common
diffusion area (source/drain) with a sense-amplifier transistor
(Figure 5). This eliminates the voltage loss caused by contact
resistance when transistors are separated and interconnected.
This also helps maintain the operating voltage margin and so
improves memory yield.
The bit-lines are wired above the storage capacitors to make cell
design rules more tolerant (Figure 6 ) . A self-aligned contact
process is used to build cell in 8F-square (Fis the minimum design
rule). Bit-contacting pillars are formed simultaneously with storage electrodes using a poly-2 layer. This elevated contact region
allows bit-lines to connect cells to achieve high-memory yield. The
storage-electrode region here, however, is small compared to its
counterpart in the capacitor over bit-line (COB) approach. To
keep the storage capacitance at the 22fF minimum obtainable
with the SiN film technology, the height of the cylinder electrode
is increased to 2pm, although the surface of the chip is polished
by chemical mechanical polish (CMP) to allow precision lithography. The resistance of the contact region thus formed is 4kR,
which is completely acceptable for cell operation. Inter-bit line
coupling noise is the biggest concern with this cell structure
because the bit lines are not shielded by a cell plate as they are in
other structures. Transposing bit-lines several times in the core
area may completely suppress noise, but the accompanying area
penalty would create another problem [21. 200nm pure tungsten
bit lines reduce coupling capacitance without area penalty.
Figure 6 is a chip micrograph with the RDLL structure shown in
a white frame.With 0.28pm design rules, the chip fits in a 1st
generation 256Mb, 16-wide JEDEC standard TSOP package.
The operation cycle is 6ns. Table 1 summarizes chip features.
RDLL in parallel with the mass-producable cell is the key to the
future quarter-micron high-speed memory technology.
References:
[I] Saeki, T., et al., A 2.511s Clock Access 250MHz 256Mb SDRAM with
a SynchronousMirror Delay, ISSCC Digest of Technical Papers, pp. 374-

375, Feb., 1996.

[2] Hidaka,H., et al., TwistedBit-lineArchitectures for Multi-Megabit

DRAMS,IEEE J.Solid-stateCircuits,vol. 24, no. 1,pp. 21-27, Feb., 1989.

[3] Okajima,Y.,et al., DigitalDelayLockedLoop and DesignTechnique

for High-speed SynchronousInterface,IEICE Trans. Electron., vol. E79C, no. 6, pp. 798-807,June, 1996.

72

1997 IEEE International Solid-state Circuits Conference

0-7803-3721-2 I 97 1 $5.00 IO IEEE

ISSCC97 / February 6,1997 / Salon 8 / 3:45 PM

Replica circuits,
.............................................................

VCC=3,3V,(Vint=ZSV), Z S t , SSTL

M,

> ............................................................................

I .6

Clock

.....................................

.......

1.4

Figure 1: Block diagram of register-controlledDLL.

1.2

Voltage5

09
2.4

1.4
0.4

10

30

20

40

Time (ns)

c<

1 (b)

(4

s$,&t

1-

Figure 4: Clock and data-outwaveforms.

<
+J-

Adjusted

slow
Shift-right

Figure 2: Core circuit operation in RDLL.

(a) Delay line, (b) Phase comparator
Pch,SlA
0.ONS
I.OHS
2.ONS
.......+>
> t------P-PPPPPPPPPPPP
>.
PPPPPPPPPPPPP
>.
PPPPPPPPPPPppp
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PPPPPPPPPPPP
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>.
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P PPPPPPPPPPP

. .+. .(t.. . . . . .

tCLK= IO. OOHS

tCLK= 9.900HS
1CLK= 9. SOOHS
1Ct.K. 9 . 7 m
tCLK= 9. MONS
1CLK= g.5lONS
tCLK= 9.40011s
tCLK= 9.3OowS
tCLK= 9.20011s
1CLK= 9. IOONS

tCLK= 8.MloNS > .

1CLK=

8.MO11s

>.
> t-----P
>.
>.
>.
>.

1CLK= '1.500Hs

>

1CLK. 7.20011s >

LCLK. 7. IOONS >

.
.

1CLK= 1.4OONS
lCLK= 7.300Hs

1CLK= 6.800NS > .

tCLK= 6.100NS > .

1CLK= 6.MlONS > .

tCLK= 6.5QONS > .

tCLK= 6.400NS > ,

1CLK- 6.30ONS > .
K L K = 6.2OONS > .

+,

. . . . . . . . . t (t
. . ..
..
..
.
O.ONS

I.ONS
tAC

0."

2 ONS

BIB

(~--------.,--...--.-i)

PPPPPPPPPPPPPPPP

>.
>.

LCLK- 6. LOONS > .

LCLK- 6.OOONS > t----

0 . 4 ~ ~0 . ~ 1 s

> t..... ....PP.PPPPPPPP

6.980NS ) .
PPPPPPPP
. PPPPPPPPP
6.960NS ) .
6.940NS > .
PPPPPPP
6. 920NS > .
PPPpb PPPPPPPPP
6 . 9 0 0 ~ ~> .
PPPPP
6. WINS > . PPPPPpbPPPPPPPPPP
6. W
NS > .
PPPPPPPPPPPPPP
6.B40NS > .
PP PPPPPPPPPPPP
6. m i s > .
PPPPPPPPPPPP
6. BOONS
....)..t
.P P.PPPPPPPPP
6.i60NS > .
P PPPPPPPPPPP
P PPPPPPPPP
6.760NS > .
6.740~~
>.
. PPPPPPPP
6.720HS > .
P PPPPPP
6.100NS ) .
P P PPP PPPPPPPP
6.680NS > .
P PPP P P PPPPP
6. WNS ) .
P PPPPPPPPPPPP
6.MONS
.
P.PPPPPPPPPP
6.620NS ) .
PPPPPPPPPPP
6.600NS > t........
.tPPPPPPPPPP
6.jSONS > .
P PPPPPPPP
6.DONS > .
. PPPPPPPPP
6. S O N S ) .
PPPPPPPPPPPPPPP
6.jZONS > .
PPPPPPP
6. m s > . P
6.480NS > .
PPPPPPPPPPPPPPPP
6.4"s
>.
PPPPPPPPPPPPPPP
6 . 4 4 0 ~ ~> .
PPPPPPPPPPPPP
6.42ONS > . P
PPPPPPPPPPPP
6.4OONS
......> .t
PPtPPPPPPPPPP
6.NlONS > .
. PPPPPPPPP
6.260NS > .
PPPPPPP
6.340NS > .
PPPPGPPPPPPPPPP
6. ~
N > S. PPPPPPPPPPPPPPPPP
6.300NS > .
PPPPPPPPPPPPPP
6.280NS > .
P PPPPPPPPPPPP
6.260NS ) .
P PPPPPPPPPPPP
6 240~s .
PPPPPPPPPPPPP
.PPPPPPPPPP
6.220NS ) .
6. ZOONS > t.....t..
PPPPPPP
i.OOONS

Ppppppppp
PPPPPwP

1CLK= 8. loot6
tCLK= 8. OOONS
tCLK= 1,90011s
tCLK= 7.800NS
tCLK= 7.7OONS
tCLK= 1.60ONS

(t .........t.........

0.4NS

0.6NS

t>

0.8HS

mm
SLI

5LI

Nch SIA

Figure 5: Layout of sense amplifiers and column gates.

Figure 6: See page 433.

Process technology
Chip size
Cell size
Configurations
CAS access time
RAS access time
CAS latency
Supply voltage
Refresh cycle
Redundancy

0.28pm
3-poly, 3-metal(2W, 1 4 - C u )
triple-we11
14.91x22.01mmz
0.564x1.128mmz
x4, x8, x16, x32 (bonding options)
18ns
36ns
2,3,4
3.3V (external) 12.5V (internal)
8k I 64ms
16 Row / 32Mb, 4 Column 18Mb

Table 1: 256Mb synchronousDRAM features.

Figure 3: Schmoo plot of access time vs. cycle time.

DIGEST OF TECHNICAL PAPERS

73

TP 4.5: A 256Mb SDRAM Using a Register-ControlledDigital DLL

(Continued from page 73)

Figure 6 Chip micrograph.

TP 4.6: A 4-Level Storage 4Gb DRAM

(Continued from page 75)

Pads and Peripheral Circuits

1Gb
MACRO

Figure 5: Chip micrograph and layout.

DIGEST OF TECHNICAL PAPERS

433