LATEX ASSIGNMENT FILE

T APOORVA SINGH.
ICE-2nd Yr
30210401014

List of Figures
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Circuit Diagram for RC Phase Shift Oscillator .

Graph for RC phase shift oscillator . . . . . . .
Circuit Diagram for Eagle RC Circuit . . . . . .
Eagle RC Circuit PCB . . . . . . . . . . . . . .
Circuit Diagram for Narrow Band Pass Filter .
Graph for Narrow Band Pass Filter . . . . . . .
Circuit Diagram for Eagle Narrow Circuit . . .
Eagle Narrow PCB Design . . . . . . . . . . . .
Circuit Diagram for Narrow Band Notch Filter .
Graph for Narrow Band Notch Filter . . . . . .
Eagle Diagram Narrow Band Notch Filter . . .
Narrow Band Notch Filter PCB . . . . . . . . .
Circuit Diagram for 2-to-4 line decoder . . . . .
Graph for 2-to-4 line decoder . . . . . . . . . .
Circuit Diagram for D Flip Flop . . . . . . . . .
Graph for D Flip Flop . . . . . . . . . . . . . .

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ASSIGNMENT-1
Aim of the experiment:
To design and simulate RC Phase Shift Oscillator of 10kHz using op-amp and also check performance
with respect to the gain of the circuit (Transient Analysis).

Apparatus Required:
Orcad Pspice Software.

Theory:
The Op Amp is used in the inverting mode and therefore provides 180 phase shift. The additional phase
of 180 deg is provided by the RC feedback network to obtain a total phase shift of 360. The feedback
network consists of three identical RC stages. Each of the RC stage provides a 60 deg phase shift so
that the total phase shift due to feedback network 180. It is not necessary that all the three RC sections
are identical so long the total phase shift is 180. However, IF we use non identical stages, it is possible
that the total phase shift is 180 for more than one frequency this phenomenon can lead to undesirable
inter modal oscillations.

Figure:
Result:
We designed RC phase shift oscillator in ORCAD software

Precautions:
1.Connections should be correct.
2.Take care of the errors.

Figure 1: Circuit Diagram for RC Phase Shift Oscillator

Figure 2: Graph for RC phase shift oscillator

ASSIGNMENT-2
Aim of the experiment:
Design and simulate the Narrow Band Pass and Narrow Band Notch Filter.

Apparatus Required:
Orcad Pspice Software.

Theory1:
Narrow Band Pass Filter : A narrow bandpass filter employing multiple feedback is depicted in figure.
This filter employs only one op-amp, as shown in the figure. In comparison to all the filters discussed
so far, this filter has some unique features that are given below. 1. It has two feedback paths, and this
is the reason that it is called a multiple-feedback filter. 2. The op-amp is used in the inverting mode.
Generally, the narrow bandpass filter is designed for specific values of centre frequency fc and Q or fc
and BW. If the value of quality factor is greater than ten then the pass band is narrow and bandwidth
of the pass band is also less. This band pass filter is called as Narrow Band Pass Filter. It uses only
one active component (op-amp) rather than two and this op-amp is in inverting configuration.

Figure:
Figure:
Theory2:
Narrow Band Notch Filter : In signal processing, a band-stop filter or band-rejection filter is a filter that
passes most frequencies unaltered, but attenuates those in a specific range to very low levels. It is the
opposite of a band-pass filter. A notch filter is a band-stop filter with a narrow stopband (high Q factor).
Narrow notch filters (optical) are used in Raman spectroscopy, live sound reproduction (public address
systems, or PA systems) and in instrument amplifiers (especially amplifiers or preamplifiers for acoustic
instruments such as acoustic guitar, mandolin, bass instrument amplifier, etc.) to reduce or prevent
audio feedback, while having little noticeable effect on the rest of the frequency spectrum (electronic or
software filters). Other names include band limit filter, T-notch filter, band-elimination filter, and
band-reject filter. Typically, the width of the stopband is 1 to 2 decades (that is, the highest frequency
attenuated is 10 to 100 times the lowest frequency attenuated). However, in the audio band, a notch
filter has high and low frequencies that may be only semitones apart.

Figure 5: Circuit Diagram for Narrow Band Pass Filter

Figure 6: Graph for Narrow Band Pass Filter

Figure 7: Circuit Diagram for Eagle Narrow Circuit

Figure 8: Eagle Narrow PCB Design

Figure:

Figure 9: Circuit Diagram for Narrow Band Notch Filter

Figure 10: Graph for Narrow Band Notch Filter

Figure:

Figure 11: Eagle Diagram Narrow Band Notch Filter

Figure 12: Narrow Band Notch Filter PCB

Result:
We designed both the filters.

Precautions:
1.Connections should be correct.
2.Take care of the errors.

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ASSIGNMENT-3
Aim of the experiment:
To Design a 2-to-4 line decoder and simulate.

Apparatus Required:
Orcad Pspice Software.

Theory:
As a decoder, this circuit takes an n-bit binary number and produces an output on one of 2n output
lines. It is therefore commonly defined by the number of addressing input lines and the number of data
output lines. Typical decoder/demultiplexer ICs might contain two 2-to-4 line circuits, a 3-to-8 line
circuit, or a 4-to-16 line circuit. One exception to the binary nature of this circuit is the 4-to-10 line
decoder/demultiplexer, which is intended to convert a BCD (Binary Coded Decimal) input to an output
in the 0-9 range. If you use this circuit as a demultiplexer, you may want to add data latches at the
outputs to retain each signal while the others are being transmitted. However, this does not apply when
you are using this circuit as a decoder then you will want only a single active output to match the input
code.

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Figure:

Figure 13: Circuit Diagram for 2-to-4 line decoder

Result:
We designed 2-to-4 line decoder in Orcad software

Precautions:
1.Connections should be correct.
2.Take care of the errors.

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Figure 14: Graph for 2-to-4 line decoder

13

ASSIGNMENT-4
Aim of the experiment:
To Design and Simulate D Flip Flop.

Apparatus Required:
Orcad Pspice Software.

Theory:
One of the main disadvantages of the basic SR NAND Gate bistable circuit is that the indeterminate
input condition of SET = logic 0 and RESET = logic 0 is forbidden. This state will force both outputs to
be at logic 1, over-riding the feedback latching action and whichever input goes to logic level 1 first will
lose control, while the other input still at logic 0 controls the resulting state of the latch. But in order to
prevent this from happening an inverter can be connected between the SET and the RESET inputs to
produce another type of flip flop circuit known as a Data Latch, Delay flip flop, D-type Bistable, D-type
Flip Flop or just simply a D Flip Flop as it is more generally called. The D Flip Flop is by far the
most important of the clocked flip-flops as it ensures that ensures that inputs S and R are never equal
to one at the same time. The D-type flip flop are constructed from a gated SR flip-flop with an inverter
added between the S and the R inputs to allow for a single D (data) input. Then this single data input,
labelled D, is used in place of the set signal, and the inverter is used to generate the complementary
reset input thereby making a level-sensitive D-type flip-flop from a level-sensitive RS-latch as now S =
D and R = not D as shown.

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Figure:

Figure 15: Circuit Diagram for D Flip Flop

Figure 16: Graph for D Flip Flop

Result:
We designed D Flip Flop in Or cad software

Precautions:
1.Connections should be correct.
2.Take care of the errors. Software.