System/Verification: Advanced Methodology Track

Abstracts
AVM1
A Novel Approach For Automating Verification And Performance Analysis of High Speed
Cache Coherent Interconnect Subsystems In SoC
Broadcom
Shailesh Wardhen - Broadcom
Mukundan KN - Broadcom
Gnaneshwara Tatuskar - Cadence Design Systems
Yoga Priya - Cadence Design Systems
Todays complex SoCs for Enterprise networking applications comprise of very high speed
coherent network feeding into multiple high speed IP subsystems with their own
interconnects. This poses challenge of not only verifying integration of those different
interconnect components but also of estimating overall throughput seen for different
target applications when entire system is put together. This paper describe approach to
quickly assemble UVM based Test bench to validate full SoC interconnect and provide
real time performance analysis with actual RTL on workstation simulation.
AVM2
Code Coverage On System Verilog Testbench As A Verification Signoff Metric
Analog Devices
Ponnambalam Lakshmanan - Analog Devices
Kunal Jani - Analog Devices
Swati Ramachandran - Cadence Design Systems
Achieving coverage closure goals is one of the most visible and challenging assignments
in functional verification. Though todays SOC designs have very complex SV/UVM based
testbenches, most of our focus and effort continues to be on the coverage closure for
design; with testbench being largely ignored.

As indicated above, there are several design signoff coverage metrics that make the DV
engineers confident about the DUT being sufficiently stressed. However, when it comes
to the testbench, the only metric is functional coverage. What if that itself has holes? Do
we have any solution to address this gap?
This paper introduces a new metric for verification signoff: Testbench Code Coverage,
which aids in filling up this gap. Besides introducing the features of this metric, this paper
also describes how it helped in catching interesting scenarios that we failed to exercise in
the testbench; and could have possibly ended up as design bugs late in the project cycle.

AVM3
Co-Simulation With RTL Verification IP to Verify SystemC Models
Infineon Technologies
Simranjit Singh - Infineon Technologies
Prasanth Sasidharan - Infineon Technologies
As SoC complexity is increasing and time to market is shortening, SystemC based virtual
platforms (VP) are gaining popularity for early software development. The accuracy of a
VP to the hardware is very critical. This will enable the developed software to run
seamlessly on the hardware. The inaccuracies between hardware and VP are generally
caused by incorrect interpretation of the specification. Also, the VP models verification is
often limited to directed tests and is not as comprehensive as done for the hardware
models. Hence, there is a need to have better verification methodology for VP models
and a platform to compare against hardware models. In this session, we will discuss
about an approach to ensure accuracy of VP to hardware by using hardware verification
environments to verify the corresponding VP models.

AVM4
Fault Verification Of Safety Centric Automotive Mixed Signal Chip
NXP Semiconductors
Justin Jacob - NXP Semiconductors
Harish Bodappatti - NXP Semiconductors
Manikandan Panchapakesan - NXP Semiconductors
Lokesh Babu P - Cadence Design Systems
Functional safety (FuSa) refers to the concept that an overall system will remain
dependable and function as intended even in the event of an unplanned or unexpected
occurrence. So it is important to record and report functional safety measures in order to
have a verified system. The ISO 26262 functional safety standard addresses the
assessment and reduction of the risk that unexpected errors will lead to unplanned
behavior. The functional safety also brings the new requirement for the fault injection
and detection flow. In this presentation we will be focusing on how Cadence FuSa
solutions is used in our mixed signal chip to automate and optimize Fault simulation
campaign and meet safety coverage goals.

AVM5
Highly Controllable and Efficient Verification IP Architecture for Layered Protocol
Samsung Semiconductor India R&D
Ankit Agarwal - Samsung Semiconductor India R&D
Garima Srivastava - Samsung Semiconductor India R&D
Modelling verification components for layered verification structures used to mimic a
layered protocol exposes significant challenges. It is important that the test sequences be
provided with fine grain control of the desired verification components. In this session,
we will present a pragmatic approach, using System Verilog and Universal Verification
Methodology, which we developed for layered protocol verification to address the
challenges. The proposed architecture provides a rich set of control to the Verification IP
user through
(1) easy development of complex test scenarios
(2) ad-hoc error injection mechanisms without modifying the existing model
(3) top level virtual sequencer for all layer-targeted sequences, and
(4) the ability to perform complete protocol stack verification.

AVM6
Methodology for Faster and Exhaustive Verification of A Mixed Signal Subsystem
Analog Devices
Sandeep Kumar Bojja - Analog Devices
Kunal Jani - Analog Devices
Lokesh Babu P - Cadence Design System
Low power is clearly the principal theme in todays SOC designs; and the same is
achieved through a variety of aggressive low power techniques. ADucM302x is one such
Cortex-M3 based SoC. The Power Supply Monitor (PSM) of the SoC is a mixed signal
block; and is an integration of analog blocks like voltage regulator, comparator, supply
mux and reset circuits with a digital state machine for controlling the regulators gain and
trims for tweaking the thresholds. Given the nature of this critical block, the desire was to
exhaustively verify this block across all possible modes of operation and under varying
supply and load. Such extensive verification is difficult in cosims. We , therefore, adopted
a different verification strategy which involved coming up with a block level testbench for
the PSM block and relied on developing real number models for the various analog
modules. The development of a block level testbench for the PSM mixed signal design
significantly boosted our verification efforts. Further, it increased our faith in the RNM
aided verification methodology, which has some clear benefits as listed below.
a) Very fast run time
b) Can leverage the advantages associated with a typical digital verification
c) Digital engineers are far more comfortable and conversant debugging RNM models as
opposed to debugging cosims
d) Identifying critical bugs

AVM7
Techniques To Automate UVM Testbench And Stimulus To Achieve At Least 30% Of
Verification
Xilinx
Mohana Krishna P - Xilinx
In semiconductor industry time to market is very important along with technology
innovation. In VLSI design cycle, verification takes a key role and considerable amount of
time and effort. With some techniques, if verification time & efforts are reduced,
products can be delivered early in the marker. Few companies already developed VIP
(Verification IP) for many protocols, by using these readily available VIPs, test bench
development time can be reduced.
In this session, we will discuss techniques to automation UVM test bench including SV
testbench top module, SV UVM ENV, Register model, System Bus VIPs instance, stimulus
to check register interface & system side bus and regression scripts to speed up
verification.

AVM8
Usage of Advanced Verification Concepts in SystemVerilog Verification Environment
Mindtree
Sougata Bhattacharjee - Mindtree
Chandana Nallangi - Mindtree
Mahesh Pai - Mindtree
In todays world of VLSI, verification consumes almost 70% of the design usage,
considering the factors like time to market, design spin, cost effectiveness and
reusability. Advancement of SOCs into MPSOCs and with its inherent complexity and the
trending ULSI era, verification tends to be the most critical challenge in the
semiconductor industry.
In order to reduce the verification effort and to minimize the debug time, we have
adopted advanced concepts of SystemVerilog viz. multiple inheritance, composition and
interface class to develop a novel verification environment for the reference IP of SPI
integrated in the generic SOC.
In this session we discuss how advanced SystemVerilog constructs have an imp act on
verification environment