7/22/2014

Real Computer Science begins where we almost stop reading ...: MCQ Computer Architecture Set I

MCQ Computer Architecture Set I

1 . From where interrupts are generated?
a)Central processing unit
b) Memory chips
c) Registers
d) I/O dev ices
Ans: d
2. The output of a gate is low when at least one of its input is low . It is true for
a)AND gate
b) OR gate
c) NAND gate
d) NOR gate
Ans: A
3. Which one of the following is most suitable to make a parity checker
a) AND gate
b) OR gate
c) Ex clusiv e- OR gate
d) None of the abov e
Ans: C
4What is the minimum number of flip-flops required in a counter to count 1 00 pulses?
a)Fiv e
b) sev en
c) Ten
d) hundred
Ans: b
5. For a RS flip-flop constructed with NAND gates and input R=1 and s=1 the state is
a) Memory state
b) Set state
c) Reset state
d) Unused state
Ans: D
6. The adv antage of RISC processor ov er CISC processor is that
a) The hardware architecture is simpler
b) An instruction can be ex ecuted in one cy cle
c) Less number of registers accommodate in chip
d) Parallel ex ecution capabilities
Ans: b
7 . Which of the following is true about interrupts?
a) They are generated when memory cy cles are stolen
b) They are used in place of data channels
c) They can be generated by arithmetic operation
d) They can indicate completion of an I/O operation
Ans: A
8. Te dev ices connected to a microprocessor can use the data bus:
a) all the time
b) at regular interv al of time
c) only when its sending or receiv ing data
d) when the microprocessor is reset
Ans: c
9. Intel 8080 microprocessor has an instruction set of 91 instruction . The opcode to implement this
instruction set should be at least
a3 bit long
b) 5 bit long
c) 7 bit long
d) 9 bit long
Ans: c
1 0. Dy namic RAMs are best suited to
(a) slow sy stem
(b) large sy stem
(c) one bit sy stem
(d) none of the abov e
http://girdhargopalbansal.blogspot.in/2013/06/mcq-computer-architecture-set-i.html

1/4

7/22/2014

Real Computer Science begins where we almost stop reading ...: MCQ Computer Architecture Set I

Ans: a
1 . Intel Pentium CPU is a
RISC based **
CISC based
Both of the abov e
None of the abov e
2. A modem is used to link up two computers v ia
telephone line
dedicated line
Both of the abov e **
None of the abov e
3. The max imum integer which can be stored on a 8 bit accumulator is
112
200
255 **
224
4. In a sy stem with a 1 6 bit address bus, what is the max imum number of 1 K by te memory dev ices it
could contain
16
64
256 **
65536
5. Which of the following memories in a computer is v olatile?
RAM **
ROM
EPROM
ALL
6. A peripheral is
any driv es installed in the computer
tapedriv e connected to a computer
any phy sical dev ice connected to the computer **
None of abov e
7 . How many bits do y ou think will be adequate to encode indiv idual character in Dev nagari script
12
16
64
1 0 **
8. Which of the following bus is used to transfer data from main memory to peripheral dev ice?
DMA bus
Output bus
Data bus **
All of the abov e
9. To prov ide increased memory capacity for operating sy stem, the
http://girdhargopalbansal.blogspot.in/2013/06/mcq-computer-architecture-set-i.html

2/4

7/22/2014

Real Computer Science begins where we almost stop reading ...: MCQ Computer Architecture Set I

v irtual memory is created **

cache memory is increased
memory for OS is reserv ed
Additional memory is installed
1 0. CD -RAW is
Input dev ice only
output dev ice only **
Both of the abov e
None of the abov e
1 1 . Which of the following require large computer memory ?
Imaging
Graphics
V oice
All of the abov e **
1 2. Which major dev elopment led to the production of microcomputers?
Magnetic disks
floppy disks
Logic gates
Integrated Circuits **
1 3. In immediate addressing the operand is placed
in the CPU register
after opcode in the instruction **
in the memory
in the stack
1 4. Micro instructions are stored in
computer memory
primary storage
secondary storage
control memory **
cache memory
1 5. Pipeline processing implement
fetch instruction
decode instruction
fetch operand
calculate operand
ex ecute instruction
all of the abov e **
1 6. The 1 6- bit registers in 8085 is
general purpose register
accumulator
stack pointer and program counter **
all of the abov e
1 7 . Instruction pipelining has minimum stages
http://girdhargopalbansal.blogspot.in/2013/06/mcq-computer-architecture-set-i.html

3/4

7/22/2014

Real Computer Science begins where we almost stop reading ...: MCQ Computer Architecture Set I

4
2 **
3
6
1 8. Sy stems that do not hav e parallel processing capabilities are
SISD **
SIMD
MIMD
All of the abov e
1 9. The word size of the microprocessor refers to
the amount of a information that can be stored in a by te
the amount of a information that can be stored in a cy cle **
The number of machine operations performed in a second
the max imum length of an English word that can be input to a computer
20. How many address lines are needed to address each memory location in a 2048X 4 memory chip?
10
1 1 **
8
12

http://girdhargopalbansal.blogspot.in/2013/06/mcq-computer-architecture-set-i.html

4/4