CMOS

heiyong@ime.ac.cn
2013108

 vs.

In

Combinational
Logic
Circuit

In

Combinational
Logic
Circuit

Out
State

Out

Nxit_State

State

Output = f(In)

Output = f(In, State)

State=f'(Previous In,Previous State)

 vs.

PUN

InN
In1
In2
InN

Out

VDDGND

In1
In2

VDD

PDN

Clk

Mp

Out
In1
In2
In3
Clk

CL
PDN
Me

CMOS

CMOS
VDD

In1
In2

PUN

InN

InN

PMOS 1
F(In1,In2,InN)

In1
In2

VDD

PDN

Vin

Vout
CL

NMOS 0

PUN(Pull Up Network)1 PDN(Pull Down Network)0

PUPPDN,
(DeMorgans )

NMOS

PMOS

NMOS

NMOS 1;
0
NMOS

X=0

PMOS 0;
1
PMOS

X=1

Threshold Drops
VDD

PUN

VDD

VDD
D

0 VDD

VGS

CL
VDD 0

PDN
D

VDD
S

CL

0 VDD - VTn
CL

VGS

VDD |VTp|
S

CL

 CMOS

: NAND

: NOR

 CMOS
VDD

F(OUT) = D + A (B + C)
B
A
C
D

F(OUT)

1PDN
A
D
B

C
GND

2PDN

3PUN

 CMOS

VOHVOLVDDGND

VDDVSS(GND

CMOS
VDD-GND;
;
VDDGND;

0
VDDGND;


Req

A
A
Rp
A

Rp

Rp
B

Rn

Rp
CL

Cint

A
Rn
A

Cint

A
NAND2

Rp

B
Rn

INV

CL
Rn

Rn

CL
NOR2


Rp
A

Rp
B

Rn

CL

B
Rn
A

0.69 Rp/2 CL

0.69 Rp CL

Cint

0.69 2Rn CL

@
3

Input Data
Pattern

Delay
(psec)

A=B=01

69

A=1, B=01

62

A= 01, B=1

50

0.5

A=B=10

35

A=1, B=10

76

A= 10, B=1

57

A=B=10

2.5

Voltage [V]

A=1 0, B=1

1.5

A=1, B=10

-0.5

100

200

time [ps]

300

400

NMOS = 0.5m/0.25 m
PMOS = 0.75m/0.25 m


Rp
2 A

Rp
B

Rn
2

Rn
A

Rp
4 B

2
CL

Cint

Rp

Cint

Rn

Rn

CL
1

CMOS

8 6

8 6

4 3

4 6
OUT = D + A (B + C)
2

A
D

1
B

2C

CL

C3

C2

C1

RC
(Elmore)

tpHL = 0.69 Reqn(C1+2C2+3C3+4CL)

tp (Fan-In)(NAND)
1250

quadratic(

tp (psec)

1000
750

tpHL

500
250

4.
tp
tpLH
linear

0
2

10

(fan-in)

12

14

16

tp (Fan-Out)
tpNOR2

tpNAND2
tpINV

tp (psec)
2

10

12

(eff. fan-out)

14

16

(Slope)

(driving
strength)

tp (Fan-In)(Fan-Out)
(Fan-in): (quadratic)

(Fan-out):
CL
tp = a1FI + a2FI2 + a3FO

1
Transistor sizing
(fan-out)

InN

MN

In3

M3

C3

In2

M2

C2

In1

M1

C1

CL

RC
M1 > M2 > M3 > > MN
(
)

In3 1 M3

CL

In2 1 M2

C2

In1
M1
01

C1

CL, C1 C2

01
In1
M3

CL

In2 1 M2

C2

In3 1 M1

C1

CL

F = ABCDEFGH

4
BUFFERfan-in
fan-out

CL

CL

5

tpHL = 0.69 (3/4 (CL VDD)/ IDSATn )
= 0.69 (3/4 (CL Vswing)/ IDSATn )


Logic effort

(path


?
?
?
?


In

Out
1

CL

N: Ci+1/Ci = Ci/Ci-1
N: Ci+1/Ci ~ 4

?
Logic Effort,

(Logical Effort)

CL

Delay = k Runit Cunit 1 +

Cin
= (p + g f )

Delay = ( pi + g i f i )

p (intrinsic delay)
g (logical effort)
f (effective effort fanout)

ginv =1, pinv = 1

D tinv

i =1

d = p +h

h = g f

()= Cout/Cin

(Logical effort )

(electrical effort)

(Logical Effort)
(Logical effort)
( Logical effort is
the ratio of input capacitance of a gate to the input capacitance
of an inverter with the same output current)

(Logical effort)
CMOS

g=1

g = 4/3

g = 5/3


2-input
NAND

d = p +h
= p + gf

: d

Inverter

g=1
p=1
d = f +1

: h

g = 4/3
p=2
d = (4/3)f + 2

: p
0
0

Electrical Effort:
f = Cout / Cin


Gate type

Number of inputs
1

NAND

4/3

5/3

6/3

(n+2)/3

NOR

5/3

7/3

9/3

(2n+1)/3

4, 4

6, 12, 6

8, 16, 16, 8

Inverter

Tristate / mux

XOR, XNOR

CMOS
(Logical effort)
Gate type

Number of inputs
1

NAND

NOR

2n

Inverter

Tristate / mux
XOR, XNOR



Logical Effort

G = gi

Electrical Effort

F=

Cout _ path
Cin _ path

H = hi = g i f i


(HGF):
15

G
F
GF
h1
h2
H

=
=
=
=
=
= GF?

90

5
15

G = gi
F=

Cout _ path
Cin _ path

H = hi = g i f i

90


(HGF):
15

G
F
GF
f1
f2
H

=1
5
= 90 / 5 = 18
= 18
= (15 +15) / 5 = 6
= 90 / 15 = 6
= g1g2f1f2 = 36 = 2GF

15

90

90

 Branching Effort
Branching effort:

b=

Con path + Coff path

Con path

B = bi

F =

:
H = GBF

fi
bi

H = hi = g i f i

= FB

G = gi
F=

Cout _ path
Cin _ path

Delay = ( pi + g i f i )
i =1

: hi = gifi
electrical effort: F = Cout/Cin
logical effort: G = g1g2gN
Branching effort: B = b1b2bN
: H = GFB
Path delay: D = di = pi + hi

h =H
N

h= H
N

: g1f1 = g2f2 = = gNfN

fi = h gi

1/ N

D = (g i f i + pi ) = NH + P



tp = tp,j = tp0 (pj + (fj gj)/ )

hpath effort

f1g1 = f2g2 = . . . = fNgN

1

c
CL 5

a, b, c ?


path logical effort, G = gi
path effective fan-out F = CL/g1
branching effort
b = (Con-path + Coff-path)/Con-path
path branching effort B = bi
total path effort H = GFB

N

D = tp0 ( pj + (N H)/ )


i ,
i-1

si = (g1 s1)/gi (fj/bj)

j=1

1
g1 = 1

a
g2 =
5/3

g3 = 5/3

c
g4 = 1

CL 5

F = CL/Cg1 = 5
G = 1 x 5/3 x 5/3 x 1 = 25/9
B = 1 ()
4
H = GFB = 125/9, H = 1.93
f1=1.93, f2=1.93 x 3/5 = 1.16, f3 = 1.16, f4 = 1.93
a = f1g1/g2 = 1.16, b = f1f2g1/g3 = 1.34, c = f1f2f3g1/g4 = 2.60


Term

Stage

Path

number of stages

logical effort

G = gi

electrical effort

h=

Cout
Cin

H=

branching effort

b=

Con-path + Coff-path
Con-path

B = bi

effort

f = gh

F = GBH

effort delay

DF = f i

parasitic delay

P = pi

delay

d= f +p

Sutherland,
Sproull
Harris

Cout-path
Cin-path

D = d i = DF + P

H,h
F,f

(Logical Effort)
CMOS

(Logical effort)

(Logical effort)


Ratioed Logic

Ratioed Logic

PMOS

: CMOS
NMOS
PMOS

Ratioed Logic
N+

VOH = VDD
RPN
VOL =
RPN + RL

tpL= 0.69 RLCL

(Active Loads)
VDD
Depletion
Load

VDD
PMOS
Load

VT < 0

PMOS VSS

F
In1
In2
In3

PDN

VSS
depletion load NMOS

NMOS

F
In1
In2
In3

PDN

VSS
pseudo-NMOS

(pseudo)NMOS

NMOSPseudo-NMOS

VOH = VDD
VOL

CMOS

kp
= (VDD VT ) 1 1
k n

VT = VTN = VTP

NMOS
3.0

2.5

W/Lp = 4

Vout [V]

2.0

1.5

W/Lp = 2
1.0

0.5

W/Lp = 0.5

W/Lp = 1

W/Lp = 0.25
0.0
0.0

0.5

1.0

1.5

2.0

2.5

Vin [V]

NMOS

1. p
2. n nMOS n + 1
3. kn/kp
4. DC

5. NMLNMH

1. IL
2. NML VOL = ILRPDN
3. t PLH = C LVDD 2 I L , IL
4. t PHL = 0.69 RPDN CL RPDN

IL

1-
VDD

M1

Enable

M2

M1 >> M2

F
A

CL

M1M2
Adaptive Load
M2

2-
VDD

M1

VDD

M2

Out
A
A
B
B

Out

PDN1

PDN2

VSS

VSS

Differential Cascode Voltage Switch Logic (DCVSL)

DCVSL

NMOSPMOS
PMOSNMOS

CMOSLatch

XOR
Cross-over

DCVSL XOR-NXOR
Out
Out

XOR-NXOR gate


PassTransistor
Logic

(Pass-Transistor Logic)

NNMOS

NMOS

In
x

0.5 m/0.25 m

In

Out
[V]

VD D

3.0

1.5 m/0.25 m

0.5 m/0.25 m

Out

2.0

1.0

0.0

0.5

1.5

[ns]

B
F = AB
0

AND

AND :4
CMOS6

NMOS
C = 2.5V

C = 2.5 V
M2
A = 2.5 V

A = 2.5 V
B
CL

B
Mn
M1

VB2.5V, 2.5V - VTN

1:

VDD

3.0

VDD

B
A

Mn

M2
X

Out

Voltage [V]

Mr
2.0

W/Lr =1.75/0.25
W/L r =1.50/0.25

1.0

M1
W/Lr =1.0/0.25
0.0

: X
X
X

100

200

W/L r =1.25/0.25
300
Time [ps]

400

(W/Lr
X

500

2: VT=0

VDD

VDD

0V

2.5V

VDD

0V

2.5V

Out

3: Transmission Gate
C
C = 2.5 V

C
A

A = 2.5 V
A

B
CL

C=0V

C
30

2.5 V

Resistance, ohms

Rn
20

Rp

Rn
Vou t

2.5 V

Rp
10

0
0.0

0V
Rn || Rp

1.0

Vou t , V

2.0

-MUX XOR
V DD

M2
F

S
M1
B

S
MUX

B
B

M2
A

F
M1
B

XOR

M3/M4

XORMUX CMOS


2.5

2.5
V1

In

Req

Req

V1

(b)

Vn-1

Vi+1
C

Req

Vn
C

RC
Req

Req

Req

Req

Req

Vn

Vi

Vn-1

Vi+1
C

0
(a)

In

2.5

Vi

Vi-1

2.5

Req

Req

In
C

(c)

CPL(Complementary
Pass Transistor Logic)
CPL(

A
A
B
B

Pass-Transistor
Network

(a)
A
A
B
B

Inverse
Pass-Transistor
Network

F=AB

F=A+B

F=AB
AND/NAND

F=A

(b)

F=A+B

B
OR/NOR

A
EXOR/NEXOR

F=A





MOS

MOS

NRC

NMOS
1.
2.

3. PMOS


Dynamic
Logic

 CMOS

VDDGND
(fan-in)n2n (n N + n
P)

(fan-in)n n + 2 (n+1N + 1
P)


Clk

Clk

Mp

off
Mp on

Out
In1
In2

CL
PDN

In3
Clk

1
Out
((AB)+C)

A
C
B

Me

Clk

Precharge (CLK = 0)
Evaluate (CLK = 1)

off
Me on

(PDN off), CL


PDN
N + 2 (CMOS 2N)

(VOL = GND VOH = VDD)

-

(Cin)
(Cout)
Isc, PDN CL

CMOS


CMOS
VDD GND ( Psc)
glitching

CLK

VTnPDNVM,
VIH VIL VTn
(NML)

 1:
CLK
Clk

Mp

Out
CL

A
Clk

Me

VOut

subthreshold current

Clk

Mp

Mkp

CL

Out

B
Clk

Me

 2:

Clk

CL CL

Mp

Out

CL

B=0
Clk

CA
Me

CB

CA


Clk

Mp

Mkp

Clk
Out

A
B
Clk

Me

 3:

Clk

Mp

A=0

Out1 =1
CL1

Out2 =0
CL2

B=0
Clk

Me

NAND

NAND

In

Clk

Mp

A=0

Out1 =1
CL1

CL2

B=0
Clk

Me

Voltage

Out1
1

Clk

In

Out2

Time, ns

-1
0

Out2 =0

In

 4:

Clk

Mp

Out
CL

OutVDDCLK

Clk

Me

Clk
2.5

Out
In1

1.5

In3

Voltage

In2

In &
Clk

0.5

In4
Clk

Out
-0.5
0

0.5

Time, ns

(ground bounce)


V
Clk

Mp

Clk

Mp

Out1

Me

Clk

Out2
In

In
Clk

Clk

Me

Out1

VTn
V

Out2
t

0 1 !

(Domino Logic)

Clk

Mp

11
10

In1
In2

PDN

Out1

Mp Mkp

00
01

In4

PDN

In5

In3
Clk

Clk

Me

Clk

Me

Out2

Clk

Ini
Inj

PDN

Ini
Inj

PDN

Ini
Inj

PDN

Ini
Inj

PDN

Clk




,
10
logical effort


VDD

VDD
VDD

Clk

Mp

Clk

Mp

Out1

Mr
Out2

In1
In2
In3

PDN

PDN

In4

!
Clk

Me

Clk

= 0

Me

(Footless Domino)
VDD
Clk

VDD

Mp

Clk

Mp

Out1
0
0

Clk

Mp

Out2
1

In1
1

VDD

Outn
1

In2
1

In3
1

Inn
1

foot switch

 (Dual Rail)
off
Mp Mkp

Clk
Out = AB

on
Mkp

Clk

Mp

!A

0
!B

B
Clk

Me

non-inverting

Out = AB

np-CMOS
Clk

Mp

11
10

In1
In2

PDN

Out1

Clk

Me

In4

PUN

In5
00
01

In3
Clk

Me

Clk

Mp

PDN 0 1
PUN 1 0 t

Out2
(to PDN)

NPNORA
Clk

Mp

11
10

Out1

In1
In2

Clk

Me

In4

PUN

In5

PDN

00
01

In3
Clk

Clk

Me

to other
PDNs
: !

Mp

Out2
(to PDN)

to other
PUNs

CMOS

IC

Power Dissipation

Ppeak = VDD I DD max

(Average power)
T

VDD
Pav =
iDD (t )dt

T 0

CMOS1
Switching

Short-circuit

Static currents

Leakage
--

CMOS2

Ptotal= Pdynamic+ Pshort-circuit+Pstandby+Pleakage

Pstatic

CL
CL10


Vswing=VDD,

EC = CV2/2 = CLVDD2/2
Ec 10
Etot= CL VDD2

P = CL VDD2 f

(short Circuit)
NP

(Static power consumption)

VTIleakage

Drain Leakage
Ileakage
Subthreshold
Current

CMOS
Ptotal= Pdynamic+ Pshort-circuit+Pstatic
=fCLV2DD+VDDIsc+IleakageVDD

Power = Energy/transition * transition rate

= CL * Vdd2 * f01
= CL * Vdd2 * P01* f
= CEFF * Vdd2 * f

Power
Dissipation is Data Dependent
Function of Switching Activity

CEFF = Effective Capacitance = CL * P01


Example: Static 2 Input NOR Gate

2CMOS NOR

Assume:
P(A=1) = 1/2
P(B=1) = 1/2

Then:

2NOR

P(Out=1) = 1/4
P(0 1)
= P(Out=0).P(Out=1)
= 3/4 1/4 = 3/16

CEFF = 3/16 * CL

CMOS

2NOR

B
Z

Reconvergence

P(Z=1) = P(B=1) . P(X=1 | B=1)

Becomes
complex and intractable real fast

CMOSGliching
Hazard
also called: dynamic hazards
X

A
B

Z
C

ABC

101

000

X
Z

Unit Delay

Observe: No glitching in dynamic circuits

 1: NAND
out1

out2

out3

out4

out5

1
...

6.0

V (Volt)

4.0
out2

2.0

out1

out4

out3

out6

out5

out8

out7

0.0
0

t (nsec)

2: Adder

Add0

Add1

S0

Sum Output Voltage, Volts

Cin

Add2

Add14

S2

S14

S1

4.0

4
S15

6
2.0

S10

Cin
5
S1

0.0
0

10

Time, ns

Add15
S15

 Glitching?1
0

F1

F2

F3

0
0

F1

F3
0
0

F2

Equalize Lengths
of Timing Paths Through Design

 Glitching?2

SIC11

 Glitching?2

MIC11


Inputs

Outputs
COMBINATIONAL
LOGIC

Current State

Registers
Q

CLK

Next state

CLK

CLK

CLK

CLK
D

CLK

-
Vi 1

V o1 = V i 2

V o2

Vi2

V o1

V o2 = V i 1

V i1

V o2

A
V i 2 = V o1
1

B
V i 1 = V o2

V i 2 5 V o1

V i 2 5 V o1

(Meta-Stability)
A

V i 1 5 V o2

V i 1 5 V o2

1
ABC
1Mux
2

Latch()/ Register()/ flip-flop ()

Latch

Register(

Latch
S

Flip-Flops

RSJK

Latch Register
Latch

Register

Q = Clk Q + Clk D

Q = Clk Q + Clk D

D Q

D Q

Clk

Clk

Clk

Clk

latch

register flip-flops

Latch
(Positive

Negtive

Latch
= 0N Latch

= 1P Latch

N
Latch

Logic

Logic

P
Latch

 Latch

CLK

CLK
Q
CLK

D
CLK

CLK

MUX

( NMOS)

MuxLatch
(Positive)
(CLK= 1)

0
D

CLK

Q = Clk Q + Clk In

(Negative)
( CLK= 0)

1
D

CLK

Q = Clk Q + Clk In

MuxLatch
CLK

CLK
D

1
2
3

CLK

CLK
QM

NMOS

CLK

QM
CLK

CLK

1NMOS
2

Latch
CLK=0

 (Edge-Triggered) Register
Latch
Slave

Latch

CLK

Master
0
1
D

QM

D
QM
Q

CLK
CLK

LatchRegister
Latch

 Register
latch
Master-Slave
Latch

I2

T2

Latch

I3

I5

T4

I4

T3

QM
I1

T1

CLK

MUX latch

I6

Register

CLK=1
D

Timing
1set-up) : tsu
2hold: thold
3clk-qmax: tclk-q
4T
5d-qmax: td-q
Register

CLK
t
t su
D

Q
CLK

t hold

tclk-q

tc 2

t
q

td-q
Latch

D
t

Clk

tclk-q


FFs

Tclk >
LOGIC
tp,comb

tclk_q+tcomb_max+ tsetup

:
Tclk_q+Tcomb_min > T hold

Latch

Latch

CLK=0

Register

Register

SET

CLR

CLK=0
CLK

CLK=1
D

Clk-Q

2.5

Volts

CLK
1.5

0.5

2 0.5
0

tc 2

q(lh)

tc 2

q(hl)

0.5

1
1.5
time, nsec

2.5

(Setup Time)

aTsetup=0.21ns bTsetup=0.20ns

RS-NORNAND
NORRS
S

0
1

1
1

0
0

1
0

Q
S
R

Q
Q

Forbidden State

NANDRS
S

RS

VDD
M2

M4
Q

Q
CLK

M6

M5

M1

M3

M8

CLK

M7

M5 M6Q

M5 M6
W/L

RS

QL=0.25um

Latchregister
()
CLK

CLK
CLK

CLK

CLK

CLK

register
master

slave

!clk

clk

T1

I1

QM

T2

C1
clk

I2

C2
!clk
tsu = tpd_tx
thold = zero
tc-q = 2 tpd_inv + tpd_tx

clk
!clk


!clk

clk

T1

I1

QM

T2

C1
clk

clk
!clk

I2

C2
!clk

0-0
toverlap0-0 < tT1 +tI1 + tT2
1-1
toverlap1-1 < thold

Latch

( pseudostatic)
!clk

clk

C2MOSregister
Master

Slave

M2

clk

Mon
4

off

D
!clk

Mon
3

off

M1
master
slave

M6

QM
C1

!clk
clk

Moff
8

on

Moff
7

on

C2

M5

clk
!clk

master
slave

C2MOS

VDD

VDD

VDD

VDD

M2

M6

M2

M6

M4

M8

D
1

M1

M5

clk
!clk

M1

(a) (0-0)

clk
!clk

M3

M5

(b) (1-1)

clk
!clk

M7

clk
!clk

TSPCLatch
VDD

VDD

VDD

VDD

Out
In

CLK

CLK

In

CLK

CLK
Out

latch
( CLK= 1)

latch
( CLK= 0)

TSPC
VDD

VDD

VDD
In1

PUN

VDD
In2

Q
In

CLK

CLK

PDN

Q
CLK

CLK

In1

In2

TSPC

AND latch

TSPCregister
Master

clk

on
off

clk

master
slave
clk

Slave

on
off QM

on
clk off

on
off
clk

master
slave

TSPCregister
M3

clk

off

Mon
6

QM 1 D

clk Mon
off 2 X !D M5
M1

clk

Moff
4

on

M9

Q D

clk
off
on M8
M7

master
slave

clk

master
slave

 Latch
:
Latch

Latch
L1
Data

Clk

L2

D Q

D Q

Clk

Clk

L
Data
Clk

D Q
Clk

Latch
VDD

VDD

M3

M6
CLK

VDD

Q
D

CLKG

M2

CLKG

M1

MP

M5

CLKG
X

MN

M4

(a) register

(b) glitch generation

CLK
CLKG
(c) glitch clock

( Setup Time)
Clk
t
D
t
Q
t
(a)

1.05tC 2

tC 2

tSu

tD 2
tH
(b)

1
Latch (Setup-1 )
CN
TG1

Inv2

SM

D1

QM

Clk-Q Delay

Inv1

CP
TClk-Q
TSetup-1

Data

Time

Clock
TSetup-1
t=0

Time

2
Latch (Setup-1 )
CN
TG1

Inv2

SM

D1

QM

Clk-Q Delay

Inv1

CP
TClk-Q
TSetup-1

Data

Time

Clock
TSetup-1
t=0

Time

3
Latch (Setup-1 )
CN
TG1

Inv2

SM

D1

QM

Clk-Q Delay

Inv1

CP

TClk-Q

TSetup-1

Data

Clock
TSetup-1
t=0

Time

Time

4
Latch (Setup-1 )
CN
TG1

Inv2

SM

D1

Clk-Q Delay

QM

Inv1
TClk-Q

CP

TSetup-1

Data

Clock
TSetup-1
t=0

Time

Time

5
Latch (Setup-1 )
CN
TG1

Inv2

SM

D1

Clk-Q Delay
TClk-Q

QM

Inv1

CP

TSetup-1

Data

Clock
TSetup-1
t=0

Time

Time

1
Latch (hold-1 )
CN
TG1
SM

D1

Inv2

Clk-Q Delay

QM

Inv1

CP

0
TClk-Q
THold-1

Clock

Data
THold-1
t=0

Time

Time

2
Latch (hold-1 )
CN
TG1
SM

D1

Inv2

Clk-Q Delay

QM

Inv1

CP

0
TClk-Q
THold-1

Clock

Data
THold-1
t=0

Time

Time

3
Latch (hold-1 )
CN
TG1
SM

D1

Inv2

Clk-Q Delay

QM

Inv1

CP

0
TClk-Q

THold-1

Clock

Data
THold-1
t=0

Time

Time

4
Latch (hold-1 )
CN
TG1
SM

D1

D
Inv1

Inv2

Clk-Q Delay

QM

TClk-Q

CP

THold-1

Clock

Data
THold-1
t=0

Time

Time

5
Latch (hold-1 )
CN
TG1
SM

D1

Inv2

Clk-Q Delay

QM

TClk-Q

Inv1

CP

THold-1

Clock

Data

THold-1
t=0

Time

Time

CLK

CLK

CLK

log

REG

REG
CLK

REG

CLK

Out

REG

log

REG

REG

CLK

REG

REG

(Pipeline)
Out

CLK

CLK

Latch Pipeline

CLK

CLK

In

CLK

F
C1

C2

CLK
CLK

Compute F

Out

compute G

C3

 Setup Time

From

 Hold Time

From

---1

---2


(Schmitt Trigger)
V OH

Vou t
In

Out

VTC with hysteresis

V OL

Restores signal slopes

VM

VM+

Vi n


Vin

Vout

VM+

VM

t0

t0 + tp

CMOS
VDD

VDD

M4
M6

M2
Vin

M4

M3

Vout In

Out
M2

M1

M3

X
M1

M5

VDD

 VTC

2.5

2.5

2.0

2.0
VM1

1.5

1.5

)
(V

)
(V

1.0

VM2

1.0

k=1
k=3

0.5
0.0
0.0

k=2

0.5

0.5

1.0
1.5
Vin (V)

2.0

2.5

Voltage-transfer characteristics with hysteresis.

k=4

0.0
0.0

0.5

1.0
1.5
Vin (V)

2.0

2.5

The effect of varying the ratio of the

PMOS device M4. The width is k* 0.5m m.

 (Oscillators)
0

N-1

Ring Oscillator
3.0
2.5

V1 V3 V5

Volts

2.0
1.5
1.0
0.5
0.0
20.5
0.0

0.5

1.0

1.5

time (ns)

C2MOS

NORA

DC