3122016 [MIPS Instruction Reference MIPS Instruction Reference This is a description of the MIPS instruction set, their meanings, syntax, semantics, and bit encodings. The syntax given for each instruction refers to the assembly language syntax supported by the MIPS assembler. Hyphens in the encoding indicate "don't care" bits which are not considered when an instruction is being decoded General purpose registers (GPRs) are indicated with a dollar sign (S). The words SWORD and UWORD refer to 32-bit signed and 32-bit unsigned data types, respectively. anner in which the processor executes an instruction and advai ts program counters 1. execute the instruction at PC 2. copy nPC to PC 3. add 4 or the branch offset to nPC_ This behavior is indicated in the instruction specifications below. For brevity, the function advance_pe (int) is used in many of the instruction descriptions. This function is defined as follows: void advance _pe (SWORD offset) { PC APC; offset; I Note: ALL arithmetic immediate values are sign-extended, After that, they are handled as signed or unsigned 32 bit numbers, depending upon the instruction. The only difference between signed and unsigned instructions is that signed instructions can generate an overflow exception and unsigned instructions can not. The instruction descriptions are given below: ADD — Add (with overflow) [Description: [Adds two registers and stores the result in a register Operation: [Sd = $s + St; advance_pe (4); Syntax: _ladd Sd, Ss, St Encoding: [0000 ¢ st tttt dddd 4000 001 00) ADDI — Add immediate (with overflow) Description: [Adds a register and a sign-extended immediate value and stores the result in a register Operation: _|$t = $s + imm; advance_pe (4); Syntax: [addi St, Ss, imm |Encoding: 0010 G0ss sest tttt iiii iiii ii id ADDIU -- Add immediate unsigned (no overflow) Intpulvw.mrc.idaho.edurc/peopefficgtal MIPS. Hn 193122016 [MIPS Instruction Reference |Description: |Adds a register and a sign-extended immediate value and stores the result in a register| [Operation: _[$t= $s + imm; advance_pe (4); (Syntax: jaddiu St, $s, imm Encoding: lfoo10 oiss ssst tutt iiii iiii i1ii iiit ADDU — Add unsigned (no overflow) [Description: [Adds two registers and stores the result in a register [Operation: [Sd = $s + St: advance_pe (4); [Syntax: _ljaddu $d, $s, $t [Encoding: [0000 00ss seat tett dddd d000 0010 0001 AND — Bitwise and [Description: [Bitwise ands two registers and stores the result in a register [Operation; [Sd = $s & St; advance_pe (4); (Syntax: and Sd, $s, St [Encoding: [0000 c0ss ssst tett dddd d000 0010 0100 ANDI — Bitwise and immediate [Description: [Bitwise ands a register and an immediate value and stores the result in a register (Operation: [St= Ss & imm; advance_pe (4): (Syntax: andi St, $s, imm JEncoding: [0011 00ss sset tett iiii iii iiai aiii BEQ — Branch on equal (Description: [Branches if the two registers are equal Operation: if $s == $t advance_pe (offset << 2)); else advance_pe (4); [Syntax: _|[beq Ss, St, offset Encoding: foo01 cose sect tete iiii iii i1ii i1it BGEZ -- Branch on greater than or equal to zero [Description: [Branches if the register is greater than or equal to zero Operation: if $s >= 0 advance_pe (offset << 2)); else advance_pe (4): [Syntax: _|[bgez $s, offset [Encoding: [0000 diss sssd 0001 iiii iiii 113i Gii2 BGEZAL — Branch on greater than or equal to zero and link Intpulvw.mrc.idaho.edurc/peopefficgtal MIPS. Hn [Branches if the register is greater than or equal to zero and saves the return address in | 29rans MPS Instron Reference [Description:\{$31 [Operation: if $s >= 0 $31 = PC + 8 (or nPC +4); advance_pe (offfet << 2)); else advance_pe (4); [Synta; |bgezal $s, offset lEncoding: lfooc0 cise seel 0001 iiii iiii i1ii iiit BGTZ -- Branch on greater than zero [Description: [Branches if the register is greater than zero [Operation: if $s > 0 advance_pe (offset << 2)); else advance_pe (4); [Syntax: __|[batz Ss, offset [Encoding: lfoo01 115s sss0 0000 iii iii iii: Aiit BLEZ — Branch on less than or equal to zero |Description: [Branches if the register is less than or equal to zero Operation: if $s <= 0 advance_pe (offset << 2)); else advance_pe (4); [Synta Iblez $s, offset JEncoding: 0001 10ss sse0 0000 iiii iii iiii i112 BLTZ — Branch on less than zero [Description:|[Branches if the register is less than zero [Operation: if $s <0 advance_pe (offset << 2)); else advance_pe (4); [Syntax: _|[bliz $s, offset [Encoding: |[ooo0 iss sss0 0000 iii iiii iii iiii BLTZAL -- Branch on less than zero and link [Description: [Branches if the register is less than zero and saves the return address in $31 Operation: if $s <0 $31 = PC + 8 (or nPC + 4); advance_pe (offset << 2)); else advance_pe (4): [Syntax: _|[blwzal $s, offSet lEmcoding: 0000 ciss ssei 0000 iiii iii iiii aii2 BNE ~ Branch on not equal Description: [Branches if the two registers are not equal (Operation: if $s != $t advance_pe (offset << 2)); else advance_pe (4); (Syntax: ibne $s, St, offset [Encoding: lfooo1 o1cs sect ttt iii itil iiii iiit DIV -- Divide |Description: ] ‘hitpulvww.mrc.vidaho.edulmre{peoplelffidigital MIPSir.hiin!rans MPS Instron Reference [Divides $s by $t and stores the quotient in $LO and the remainder in SHI [Operation; [SLO = $s/ St, $HI= Ss % St; advance_pe (4); [Syntax: div $s, $t [Encoding: [0000 o0ss ssst tett 0000 0000 0001 1010 DIVU — Divide unsigned :|[Divides Ss by St and stores the quotient in $LO and the remainder in SHI Operation: [SLO = Ss/ St, SHI = $s % St; advanee_pe (4): [Syntax: _|\divu $s, St [Encoding: [0000 d0ss sset tett 0000 0000 0001 1011 J— Jump [Description: [Jumps to the calculated address Operation: [PC = nPC; nPC = (PC & 0xf0000000) | (target << 2): [Syntax: target Encoding: l[oooo 103i iiai i833 i213 iii aiai aiit JAL — Jump and link [Description:||Jumps to the calculated address and stores the return address in $31 [Operation: [$31 = PC + 8 (or nPC + 4); PC = nPC; nPC = (PC & 0xf0000000) | (target << 2): [Syntax: jal target fEncoding: lfooo0 113i iii iii: iiii iiii Giii Gait JR — Jump register [Description:|[Jump to the address contained in register Ss Operation: [PC = nPC; nPC = Ss; [Syntax: jr $s lEncoding: [0000 08s ss20 0000 0000 0000 0900 1000 LB- Load byte [Description:[A byte is loaded into a register from the specified address. [Operation: _|[St= MEM{[Ss + offset]: advance_pe (4): [Syntax: _ lb St, offset(Ss) lEncoding: |[L000 ooss ass= tert iiii iii didi aiit L — Load upper immediate (The immediate value is shifted left 16 bits and stored in the register. The lower 16 bits Intpulvw.mrc.idaho.edurc/peopefficgtal MIPS. Hnavazoie MPs Inston Retrence [Description:\jare zeroes. Operation: [St = (imm << 16); advance_pe (4); [Synt lui St, imm’ JEncoding: lfooi1 11-- ——- tete iiii iiii iiii aiid LW -- Load word [Description: [A word is loaded into a register from the specified address. [Operation: [St = MEM[Ss + offset]; advance_pe (4); [Syntax: lw St, offset($s) fEncoding: [i000 12ss ssec tect iii iii iia: uiiz MFHI - Move from HIT [Description:|[The contents of register HI are moved to the specified register. [Operation: [Sd = SHI; advanee_pe (4): (Syntax: mihi $d [Encoding: l[oo00 0000 0000 0000 ada do00 0001 0000 MELO -- Move from LO [Description: [The contents of register LO are moved to the specified register, Operation: [Sd = $LO; advanee_pe (4); [Syntax: [milo $d [Encoding: [0000 0000 0000 0000 dada 4000 0901 0010 MULT - Multiply Description: [Multiplies $s by St and stores the result in SLO. [Operation: [SLO = $s * St; advance_pe (4); [Syntax: _|[mult $s, St [Encoding: [0000 does seec tete 0000 0000 0001 1000 MULTU -- Multiply unsigned [Description: |Multiplies $s by $t and stores the result in SLO. [Operation: [SLO = $s * St; advance_pe (4); [Synt Imultu Ss, $t Encoding: |[o000 doss ssst tttt 0000 0000 0001 1001 NOOP — 210 operation [Description:|[Performs no operation. apd 6 aho caunrcpepeiilgaMIPSi arkaranoie MIPS intron Reference Operation: ljadvance_pe (4); [Syntax: inoop [Encoding: [0000 0000 0000 0000 0000 0000 0000 000 Note: The encoding for a NOOP represents the instruction SLL $0, $0, 0 which has no side effects. In fact, nearly every instruction that has $0 as its destination register will have no side effect and can thus be considered a NOOP instruction, OR -- Bitwise or [Description: [Bitwise logical ors two registers and stores the result in a register Operation: [Sd = $s | $t: advance_pe (4): [Syntax: _llor $4, $s, $t [Encoding: [0000 00ss ssst tett dddd d000 0010 0101 ORI - Bitwise or immediate [Description: [Bitwise ors a register and an immediate value and stores the result in a register! [Operation; [St Ss | imm; advance_pe (4); [Syntax: [ori St $s, imm [Encoding: lfoo11 ciss sest tett iiii iiii i1ii iiii SB — Store byte [Description: [The least significant byte of St is stored at the specified address. (Operation: [MEM{[Ss + offset] = (Oxff & St); advance_pc (4); [Syntax: __|sb St, offset(Ss) [Encoding: [020 00: tttt iiid didi idid didi SLL — Shift left logical Shifis a register value left by the shift amount listed in the instruction and places the iresult in a third register, Zeroes are shifted in. Operation: _[Sd= $<; advance_pe (4): [Syntax: sil Sd, Sth [Encoding: [0000 00ss ssst tttt dddd dhhh hhOO 0000 |Description: SLLV — Shift left logical variable Shifis a register value left by the value in a second register and places the result in a third register. Zeroes are shifted in, lOperation: [Sd = $t << Ss; advance_pe (4); [Syntax: _|sllv Sd, St, Ss [Encoding: 0000 00ss ssst tett dddd d--- --00 0100 |Description: Intpulivw.mrc.idaho.edunrc/peopefficigtal MIPS. Hn a3122016 [MIPS Instruction Reference SLT — Set on less than (signed) |Description: |If $s is less than $t, $d is sct to one. It gets zero otherwise. [Operation: Jif $s < $t $d = 1; advance_pc (4); else Sd = 0; advance_pe (4); [Syntax: isit $d, $s, $t lEncoding: l[oo00 00ss sssc tett dddd 4000 0010 1010 SLTI — Set on less than immediate (signed) [Description: [If $s is less than immediate, $t is set to one. It gets zero otherwise. [Operation: if $s < imm $t= 1; advance_pe (4); else St = 0; advance_pe (4); [Syntax: [siti $t, $s, imm. fEncoding: [oo10 10ss ssst tttt iiii iiii ii4i Giii SLTIU -- Set on less than immediate unsigned [Description:|If $s is less than the unsigned immediate, St is set to one. It gets zero otherwise. [Operation: if $s < imm $t = 1; advance_pe (4); else St= 0; advance_pe (4): [syntax: _|[sitiu St, Ss, imm lEncoding: lfooi0 iiss sost tett iiii iiii iii’ siti SLTU — Set on less than unsigned [Description:][If $s is less than $t, $d is set to one. It gets zero otherwise. Operation: if $s < $t $4= 1; advance_pe (4); else Sd = 0; advance_pe (4); [Syntax: _ situ Sd, $s, St [Encoding: |[o000 dss ssst tett dddd A000 0010 1011 SRA ~ Shift right arithmetic Shifts a register value right by the shift amount (shamt) and places the value in the [Pescription:| i stination register. The sign bit is shifted in, Operation: [Sd $1 >> h; advance_pe (4); [Syntax: [gra Sd, St, h [Encoding: ooo0 oo-- ---: tett adda ahhh hh0O 0011 SRL — Shift right logical |Description: SShifis a register value right by the shift amount (shamt) and places the value in the destination register. Zeroes are shifted in. [Operation: [Sd = $t >> h; advance_pe (4); [Syntax: _|srl Sd, $b [Encoding: [0000 00-- --- tett dddd ahhh hhOO 0010 Intpulivw.mrc.idaho.edunrc/peopefficigtal MIPS. Hn 793122016 SRLV — Shi [MIPS Instruction Reference ift right logical variable [Pescription:|Gostination register. Zeroes are shifted in [Operation: [Sd = St >> Ss; advance_pe (4); [Syntax: _|jsrlv Sd, St, Ss lEncoding: [0000 00ss sest tett dddd do00 0000 0110 SUB — Subtract [Description: [Subtracts two registers and stores the result in a register Operation: [Sd = $s - $t; advance_pe (4%, [Syntax: [sub Sd, Ss, St [Encoding: [0000 o0ss ssse tete dddd 4000 0010 0010 SUBU — Subtract unsigned [Description: [Subtracts two registers and stores the result in a register Operation: [Sd = $s - $t; advance_pe (4): [Syntax: __|subu Sd, Ss, St lEncoding: [0000 00ss sez tett dddd d000 0010 0011 SW -- Store word [Description: [The contents of $t is stored at the specified address, [Operation: | MEM[Ss + offset] = $t: advance_pe (4): [Syntax: __|[sw St, offset($s) [Encoding: [1010 11ss ssst tttt iiii iiii iiii iiii SYSCALL -— System call [Description: [Generates a software interrupt. Operation: advance_pe (4); [Syntax: [syscall [Encoding: [ovo co-- ---- ao none oae= ==00 1109) The syscall in struction is described in more detail on the System Calls page. XOR — Bitwise exclusive or [Description: [Exclusive ors two registers and stores the result in a register [Operation: [Sd = $s * St; advance_pe (4); [Syntax: _|[xor Sd, Ss, St [Encoding: |[o000 005s ssst tttt addd d--- --10 0110 Intpulvw.mrc.idaho.edunre/peopefficigtal MIPS. Shifts a register value right by the amount specified in $s and places the value in the3122016 [MIPS Instruction Reference XORI - Bitwise exclusive or immediate |Description: Bitwise exclusive ors a register and an immediate value and stores the result in a register [Operation: [St = Ss “imm; advance_pe (4): [Syntax: _|xori St, Ss, imm JEncoding: 0011 10ss sssc tett iiii iiii iiai aiit Updated on September 10, 1998 Intpulivw.mrc.idaho.edunrc/peopefficigtal MIPS. Hn