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T. Esther Rani,
M. Asha Rani,
ECE Department,Osmania
University
Hyderabad, India
e-mail:rameshwar_rao@hotmail.com
I.
INTRODUCTION
II.
___________________________________
978-1-4244 -8679-3/11/$26.00 2011 IEEE
224
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Figure1. Logic level diagram of a full adder.
Table1 shows the carry status of full adder. If both A and
B are 1s then carry is generated because summing A and B
would make output SUM 0 and CARRY 1. If both A and
B are 0s then summing A and B would give us 0 and any
previous carry is added to this SUM making CARRY bit 0.
This is in effect deleting the CARRY[6].
225
S2
AND
EXOR
EXNOR
OR
ADDITION
SUBTRACTION
INCREMENT
DECREMENT
A. Multiplexer Design
The multiplexers have been used in the ALU design for
input and output signals selection. The multiplexer is
implemented using pass transistors. This design is simple
and efficient in terms of area and timing. Figure6 shows the
circuit level diagram of the 2x1 MUX. The output of the 4x1
multiplexer stage is passed as input to the full adder. A
combination of the 2x1 MUX and 4x1 MUX at the input and
output stage selects the signals depending on the operation
being performed.
2x1 Multiplexer
226
Table IV. Power and Energy for the individual cells of ALU.
S.N
Design
Cell
Energ
Power
o.
y (pJ)
(W)
1.
2x1 MUX
0.9215
4.6075
2.
4x1 MUX
3.0245
15.123
CMOS
3.
Logical MUX
8.5212
42.606
Carry generator
2.4729
12.360
7.
Conventional Full
3.3342
16.675
4.
adder
4.
2x1 MUX with
0.3625
1.6079
transmission gates
5.
4x1 MUX with
0.8525
4.2625
Transmission
transmission gates
6. Gates
Logical MUX with
7.4285
37.145
transmission gates
Carry generator
2.3965
11.998
8.
with transmission
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10.
n & p- type
transistors
gate
10 Transistor full
adder
1.2599
REFERENCES
6.2995
[1]
Energy
[2]
CMOS
CMOS gates
Transmission gates
gates
&10-Transistor
&10-Transistor full
[3]
[4]
full adder
adder
840.82
351.95
239.52
4204.5
1759.5
1197.5
(pJ)
Power
[5]
(W)
[6]
IV. CONCLUSION
[7]
[8]
[9]
[10]
[11]
ACKNOWLEDGMENT
[12]
[13]
228