L16 f04 PDF

EE247
Lecture 16
D/A Converters
D/A examples
Serial charge redistribution DAC
Practical aspects of current-switch DACs
Segmented current-switch DACs
DAC self calibration techniques

Current copiers
Dynamic element matching
ADC Converters
Sampling
Sampling switch induced distortion
Sampling switch charge injection
EECS 247 Lecture 16: Data Converters
2004 H.K. Page 1
Serial Charge Redistribution DAC
Nominally C1=C2
Operation sequence:
Discharge C1 & C2, S3& S4
closed
For each bit in succession
beginning with LSB, b0:
S1 open- if bi=1 C1
precharge to VREF if bi=0 to
GND
S1 closed-S2 & S3 & S4
open- Charge sharing C1 &
C2
of precharge on C1
+ of charge previously
stored on C2 C2
2004 H.K. Page 2
Serial Charge Redistribution DAC

Example: Input Code 101
bo b1
b2
Example input code 101 output 5/8 VREF

Very small area
N redistribution cycles for N-bits conversion
2004 H.K. Page 3
Resistor Ladder (MSB) & Binary Weighted

Charge Redistribution(LSB) Segmented DAC
Example: 12bit
DAC
6-bit MSB
DAC R string
6-bit LSB DAC
binary
weighted
charge
redistribution
Complexity lower
reset
...
...
...
.
Vout
32 C
16C
8C
4C
2C
b5
b4
b3
b2
b1
b0
than full R string

Full R string
4096 resistors
Segmented
64 R + 7 Cs
(65 unit caps)
6bit
resistor
ladder
6-bit
binary weighted
charge redistribution DAC
Switch
Network
2004 H.K. Page 4
Binary Weighted Charge Redistribution(MSB) &

Resistor Ladder (LSB) Segmented DAC
reset
Homework 6:
Compare sensitivity
of these two
segmented DACs
to component
mismatches
Vout
32 C
16C
8C
4C
2C
b5
b4
b3
b2
b1
b0
...
...
...
.
VREF
Switch
Network
6bit
resistor
ladder
2004 H.K. Page 5
Practical Aspects
Current-Switched DACs
Unit element DACs ensure monotonicity by turning

on equal-weighted current sources in succession
Typically current switching performed by differential
pairs
Based on the code only one of the diff. pair devices
are on device mismatch not an issue
Issue: While binary weighted DAC can use the
incoming binary digital code directly, unit element
requires
N to (2N-1) decoder
Binary
Thermometer
000
0000000
001
0000001
010
0000011
011
0000111
100
0001111
101
0011111
110
0111111
111
1111111
2004 H.K. Page 6
Segmented
Current-Switched DAC
4-bit MSB
Unit element
DAC + 4-bit
binary
weighted
DAC
Note: 4-bit
MSB DAC
requires extra
4-to-16 bit
decoder
Digital code
for both
DACs stored
in a register
2004 H.K. Page 7
Segmented Current-Switched DAC

Contd
4-bit MSB
Unit element
DAC + 4-bit
binary
weighted
DAC
Note: 4-bit
MSB DAC
requires extra
4-to-16 bit
decoder
Digital code
for both
DACs stored
in a register
2004 H.K. Page 8

Contd
MSB Decoder
Domino Logic
Domino logic
Example: D4,5,6,7=1
Out=1
Register
Latched NAND gate:
CTRL=1 OUT=INB
IN
Register
2004 H.K. Page 9

Reference Current Considerations
Iref is
referenced to
VDD
Problem:
Reference
current
varies with
supply
voltage
2004 H.K. Page 10

Reference Current Considerations
Iref is
referenced to
VssGND
2004 H.K. Page 11

Considerations
Example: 2-bit MSB

Unit element DAC +
3-bit binary
weighted DAC
To ensure
monotonicity at the
MSB LSB
transition: First OFF
MSB current source
is routed to LSB
current generator
2004 H.K. Page 12
2004 H.K. Page 13
Current Source Replica

Self-Calibration
2004 H.K. Page 14
I/2
Current
Divider
I/2
2004 H.K. Page 15
2004 H.K. Page 16
Current Divider
Id =
d Id
Id
d Id
Id
I d1 + I d 2
2
I d1 I d 2
I/2
I/2
M1
M2
I/2+dId /2
M1
I/2-dId /2
M2
Id
d W L

+ d Vth
W
VG S Vt h L
Ideal Current
Divider
Real Current
Divider
M1& M2 mismatched
Problem: Device mismatch could severely limit DAC accuracy
2004 H.K. Page 17
2004 H.K. Page 18
Dynamic Element Matching

During 2
During 1
I1(1) = 12 I o (1 + 1 )
I
(1)
2
I1( 2 ) = 12 I o (1 1 )
= I o (1 1 )
1
2
( 2)
2
Io/2
= I o (1 + 1 )
1
2
Io/2
I1
I2
fclk
I 2(1) + I 2( 2 )
2
I o (1 1 ) + (1 + 1 )
=
2
2
I
= o
2
I2 =
/ 2 error 1
Io
2004 H.K. Page 19
2004 H.K. Page 20
Dynamic Element Matching

During 2
During 1
I1(1) = 12 I o (1 + 1 )
I
(1)
2
I1( 2 ) = 12 I o (1 1 )
= I o (1 1 )
1
2
I 3(1) = 12 I1(1) (1 + 2 )
( 2)
2
= I o (1 + 1 )
1
2
Io/4
I3
= I o (1 + 1 )(1 + 2 )
I4
I2
fclk
I 3( 2 ) = 12 I1( 2 ) (1 2 )
= 14 I o (1 1 )(1 2 )
1
4
Io/2
Io/4
I (1) + I 3( 2 )
I3 = 3
2
I o (1 + 1 )(1 + 2 ) + (1 1 )(1 2 )
=
2
4
I
= o (1 + 1 2 )
4
/ 2 error 2
I1
fclk
/ 2 error 1
Io
E.g. 1 = 2 = 1% matching error is (1%)2 = 0.01%

2004 H.K. Page 21
Summary
D/A Converter
D/A architecture
Unit element complexity proportional to 2B- excellent DNL
Binary weighted- complexity proportional to B- poor DNL
Segmented- unit element MSB + binary weighted LSB complexity
proportional (2B1-1) + B2 DNL compromise between the two
Static performance
Dynamic performance
DAC improvement techniques
Component matching
Glitches
Symmetrical switching rather than sequential switching
Current source self calibration
Dynamic element matching
2004 H.K. Page 22
MOS Sampling Circuits
2004 H.K. Page 23
Re-Cap
Analog Input
Analog
Preprocessing
How can we
build circuits
that "sample"
A/D
Conversion
DSP
Anti-Aliasing
Filter
Sampling
+Quantization
000
...001...
110
D/A
Conversion
"Bits to
Staircase"
Analog
Post processing
Reconstruction
Filter
Analog Output
2004 H.K. Page 24
Ideal Sampling
1
In an ideal world,
zero resistance
sampling switches
would close for the
briefest instant to
sample a continuous
voltage vIN onto the
capacitor C
Not realizable!
vIN
vOUT
S1
1
T=1/fS
2004 H.K. Page 25
Ideal T/H Sampling

1
vIN
vOUT
S1
1
T=1/fS
Vout tracks input when switch is closed

Grab exact value of Vin when switch opens
"Track and Hold" (T/H)
2004 H.K. Page 26
Ideal T/H Sampling

time
Continuous
Time
T/H signal
(SD Signal)
Clock
DT Signal
2004 H.K. Page 27
Practical Sampling
1
vIN
vOUT
M1
kT/C noise
Finite Rsw limited bandwidth
Rsw = f(Vin) distortion
Switch charge injection
Clock jitter
2004 H.K. Page 28
kT/C Noise
k BT 2
C
12
2B 1
C 12k BT
VFS
In high resolution ADCs kT/C noise usually dominates

overall error (power dissipation considerations).
B
Cmin (VFS = 1V)
8
12
14
16
20
0.003 pF
0.8 pF
13 pF
206 pF
52,800 pF
2004 H.K. Page 29
Acquisition Bandwidth
The resistance R of
switch S1 turns the
sampling network into a
lowpass filter with
risetime = RC =
Assuming Vin is
constant during the
sampling period and C
is initially discharged
vIN
vOUT
R S1
C
vout (t ) = vin (1 e t / )
2004 H.K. Page 30
Switch On-Resistance
1
Vin Vout t =
<<
2 fs
1
Vin e
2 f s
<<
Vin = VFS
Worst Case:
<<
R <<
vIN
vOUT
R S1
C
1
T
2 ln 2 B 1
1
1
2 f sC ln 2 B 1
Example:
B = 14,
1
T=1/fS
C = 13pF, fs = 100MHz
T/ >> 19.4, R << 40

2004 H.K. Page 31
Switch On-Resistance
I D ( triode ) = Cox
gON = Cox
gON
dI D ( triode )
dVDS
VDS 0
W
W
(VGS Vth ) = Cox (VDD Vth Vin )
L
L
W
(VDD Vth )
L
Vin
= go 1
VDD Vth
for
gON
W
VDS
VGS VTH
VDS ,
L
2
go = Cox
Switch conductance varies with input voltage

As the ratio of VDD /Vth gets smaller conductance variation more pronounced
Technology scaling aggravates the situation
2004 H.K. Page 32
Sampling Distortion
vout =
T
Vin
2 VDD Vt h
vi n 1 e
10bit ADC & T/ = 10

VDD Vth = 2V
VFS = 1V
2004 H.K. Page 33
Sampling Distortion
10bit ADC & T/ = 10

VDD Vth = 2V
VFS = 1V
10bit ADC & T/ = 10

VDD Vth = 4V
VFS = 1V
Effect of lower supply voltage on sampling distortion

HD3 increases by (VDD1/VDD2)2
HD2 increases by (VDD1/VDD2)
2004 H.K. Page 34
Sampling Distortion
SFDR is very sensitive to
sampling distortion
Decreasing by a factor
of 2 improves HD3 by
25dB!
Solutions:
Overdesign Larger
switches
increased switch
charge injection
Complementary switch
Maximize VDD/VFS
decreased dynamic
range
Constant VGS ? f(Vin)

10bit ADC T/ = 20
VDD Vth = 2V
VFS = 1V
2004 H.K. Page 35
Complementary Switch
1
go
1B
gon
goT =gon + gop
gop
1
1B
Complementary n & p switch advantages:

Increases the overall conductance
Linearize the switch conductance for the range
Vtp< Vin <Vdd-Vtn

2004 H.K. Page 36
Issues
Supply voltage scales down with technology scaling

Threshold voltages do not scale accordingly
Ref: A. Abo et al, A 1.5-V, 10-bit, 14.3-MS/s CMOS Pipeline Analog-to-Digital Converter, JSSC
May 1999, pp. 599.
2004 H.K. Page 37
Effect of Supply Voltage Scaling
go
gon
goT =gon + gop
gop
1B
1
1B
As supply voltage scales down input voltage range for constant go shrinks
Complementary switch not effective when VDD becomes comparable to Vth
2004 H.K. Page 38
Boosted & Constant VGS Sampling

VGS=const.
Increase gate overdrive voltage as much as possible + keep

VGS constant
Switch overdrive voltage is independent of signal level
Error from finite RON is linear (to first order)
Lower Ron achieved lower time constant
2004 H.K. Page 39
Constant VGS Sampling
2004 H.K. Page 40
Constant VGS Sampling Circuit

Constant Vgs Switch
Transient Analysis
to 1.5us
VDD
M1
10 / 0.35
M2
M3
10 / 0.35
10 / 0.35
10 / 0.35
M8
M6
10 / 0.35
M4
10 / 0.35
C1
Supply
1pF
VDD = 3V
VSS = 0V
C2
C3
M5
1pF
1pF
10 / 0.35
M12
P
M11
M9
M11
10 / 0.35
VP1
10 / 0.35
10 / 0.35
VS1
1.5V
1MHz
Chold
1pF
100ns
2004 H.K. Page 41
Clock Voltage Doubler

Clock Booster
Transient Analysis
to 500ns
Supply
VDD = 3V
VSS = 0V
VDD
M1
M2
10 / 0.35
10 / 0.35
C1
C2
1pF
1pF
P_Boost
P_N
VP1
100ns
2004 H.K. Page 42
Constant VGS Sampler: LOW

Constant Vgs Switch:
P is LOW
VDD
M3
~ 2 VDD
(boosted clock)
10 / 0.35
OFF
VDD
VDD
M4
C3
1pF
Sampling switch
M11 is OFF
10 / 0.35
Device
OFF
VDD
M12
M11
OFF
10 / 0.35
OFF
VS1
1.5V
1MHz
Chold
C3 charged to VDD
1pF
Input voltage
source
2004 H.K. Page 43
Constant VGS Sampler: HIGH

Constant Vgs Switch:
P is HIGH
10 / 0.35
M8
C3 previously
charged to VDD
M8 & M9 are on:

C3 across G-S of M11
M11 on with constant

VGS = VDD
VDD
C3
1pF
M11
M9
10 / 0.35
10 / 0.35
VS1
1.5V
1MHz
Chold
1pF
2004 H.K. Page 44
Constant VGS Sampling
2004 H.K. Page 45
Complete Circuit
Clock Multiplier
for M3
M7 & M13 for

reliability
Switch
Ref: A. Abo et al, A 1.5-V, 10-bit, 14.3-MS/s CMOS Pipeline Analog-to-Digital
Converter, JSSC May 1999, pp. 599.
2004 H.K. Page 46
Advanced Clock Boosting

[H. Pan et al., "A 3.3-V 12-b 50MS/s A/D converter in 0.6um CMOS
with over 80-dB SFDR," IEEE J.
Solid-State Circuits, pp. 1769-1780,
Dec. 2000]
An attempt to cancel body effect
2004 H.K. Page 47
Advanced Clock Boosting

[M. Waltari et al., "A selfcalibrated pipeline ADC
with 200MHz IF-sampling
frontend," ISSCC 2002,
Dig. Techn. Papers, pp.
314.]
Gate tracks average of input and output, reduces

effect of IR drop at high frequencies
Bulk also tracks signal reduced body effect
SFDR = 76.5dB at fin=200MHz (measured)
2004 H.K. Page 48
Practical Sampling
1
vIN
vOUT
M1
Rsw = f(Vin) distortion

Switch charge injection
2004 H.K. Page 49
Sampling Switch Charge Injection

VG
VG
VH
VIN -Vth
VIN
VIN
VL
Cs
VO
VO
M1
VIN
toff
First assume VIN is a DC voltage

When switch turns off offset voltage induced on Cs
Why?
2004 H.K. Page 50
Sampling
Switch Charge Injection
Cross section view
Distributed channel resistance &

gate & junction capacitances
LD
Cov
MOS xtor operating in triode region
Cov
Channel distributed RC network

Channel to substrate junction capacitance distributed & variable
Over-lap capacitance Cov = LDxWxCox associated with GS & GD overlap
2004 H.K. Page 51

Slow Clock
VG
VH
VIN -Vth
VIN
VL
VO
VIN
t
V
t- toff
t
Since clock fall time >> device speed
During the period (t- to toff) current in channel discharges channel charge
into source
Only source of error Charge transfer from Cov into Cs
2004 H.K. Page 52

Slow Clock
VG
VG
VH
Cov
VIN -Vth
VIN
D
Cs
VL
VO
V =
Cov
Co v + Cs
(Vi +Vt h VL )
Co v
(Vi + Vth VL )
Cs
Vo = Vi (1 + ) + Vos
where =
VIN
Co v
Cs
; Vo s =
Co v
Cs
t- toff
(Vth VL )
2004 H.K. Page 53

Slow Clock- Example
VG
12/0.35
VIN
M1
VG
VO
VH
Cs=1pF
VIN
VIN +Vth
VL
VO
Co v = 0.3 fF / Cox = 5 f F / 2 Vth = 0.5V
=
Co v
Vos =
Co v
Cs
Cs
1 2 x0.3 fF /
1pF
VIN
= .36% 7 bit
(Vth VL ) = 1.8mV
t- toff
2004 H.K. Page 54

Fast Clock
VG
VG
M1
VIN
VH
VIN +Vth
VO
VIN
Cs=1pF
VL
VO
VIN
toff
Sudden gate voltage drop no gate voltage to establish current in channel

channel charge has no choice but to escape out towards S & D
2004 H.K. Page 55

Fast Clock
VG
Vo =
Co v
Co v + Cs
Cov
Cov + Cs
(VH VL )
1
2
Qc h
1 WCo x ( L 2LD ) ( (VH Vi Vth ))
(VH VL )
2
Cs
Cs
VIN
VL
VO
1 WCox L
where =
2
Cs
Co v
VIN -Vth
Cs
Vo = Vi (1 + ) + Vos
Vos =
VH
VIN
1 W Cox L (VH Vt h )
(VH VL )
2
Cs
toff
Assumption channel charge divided between S & D 50% & 50%
Source of error channel charge transfer + charge transfer from Cov into Cs
2004 H.K. Page 56

Fast Clock- Example
VG
VG
12/0.35
VH
VIN
VIN -Vth
VO
M1
VIN
Cs=1pF
VL
VO
VIN
Cov = 0.3 f F / Cox = 5 f F / 2 Vth = 0 . 5V VD D = 3V
= 1/ 2
WLCox
Cs
12 x0.35x5 f F /
1pF
= 2.1% 4.5 bit
toff
1 WC L (V V )
Vos =
(VH VL ) ox H th = 9mV 26.3mV = 45.3mV
Cs
2
Cs
Co v
2004 H.K. Page 57
VOS
45mV
2.1%
1.8mV
.36%
Clock fall time
Clock fall time
Both errors are a function of clock fall time, input voltage level, source impedance
& sampling capacitance
2004 H.K. Page 58

Error Reduction
How do we reduce the error?
Reduce size switch?
= RON Cs =
Vo =
Cs
Cox
1 Qc h
(VG S Vth )
2 Cs
FOM = Vo
FOM
Cs
Co x
W
L
1 WCox L ( (VH Vi Vt h ) )
(VGS Vt h ) 2
Cs
L2
Reducing switch size increases increased distortion not a viable solution

Small and V use minimum chanel length
For a given technology t x V conts.
2004 H.K. Page 59
Sampling Switch Charge Injection

Summary
Extra charge injected onto sampling capacitor @
switch device turn-off
Charge sharing with Cov
Channel charge
Issues:
DC offset
Input dependant error voltage distortion
Solutions:
Complementary switch?
Addition of dummy switches?
Bottom-plate sampling?
2004 H.K. Page 60

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EE247

DAC self calibration techniques

EECS 247 Lecture 16: Data Converters

2004 H.K. Page 1

Serial Charge Redistribution DAC

2004 H.K. Page 2

Serial Charge Redistribution DAC

Example input code 101 output 5/8 VREF

2004 H.K. Page 3

Resistor Ladder (MSB) & Binary Weighted

than full R string

EECS 247 Lecture 16: Data Converters

Binary Weighted Charge Redistribution(MSB) &

2004 H.K. Page 5

Unit element DACs ensure monotonicity by turning

EECS 247 Lecture 16: Data Converters

2004 H.K. Page 6

2004 H.K. Page 7

Segmented Current-Switched DAC

2004 H.K. Page 8

Segmented Current-Switched DAC

2004 H.K. Page 9

Segmented Current-Switched DAC

EECS 247 Lecture 16: Data Converters

2004 H.K. Page 10

Segmented Current-Switched DAC

EECS 247 Lecture 16: Data Converters

2004 H.K. Page 11

Segmented Current-Switched DAC

Example: 2-bit MSB

EECS 247 Lecture 16: Data Converters

2004 H.K. Page 12

EECS 247 Lecture 16: Data Converters

2004 H.K. Page 13

Current Source Replica

EECS 247 Lecture 16: Data Converters

2004 H.K. Page 14

EECS 247 Lecture 16: Data Converters

2004 H.K. Page 15

EECS 247 Lecture 16: Data Converters

2004 H.K. Page 16

Problem: Device mismatch could severely limit DAC accuracy

EECS 247 Lecture 16: Data Converters

2004 H.K. Page 17

EECS 247 Lecture 16: Data Converters

2004 H.K. Page 18

Dynamic Element Matching

EECS 247 Lecture 16: Data Converters

2004 H.K. Page 19

EECS 247 Lecture 16: Data Converters

2004 H.K. Page 20

Dynamic Element Matching

E.g. 1 = 2 = 1% matching error is (1%)2 = 0.01%

2004 H.K. Page 21

DAC improvement techniques

EECS 247 Lecture 16: Data Converters

2004 H.K. Page 22

MOS Sampling Circuits

EECS 247 Lecture 16: Data Converters

2004 H.K. Page 23

EECS 247 Lecture 16: Data Converters

2004 H.K. Page 24

EECS 247 Lecture 16: Data Converters