J. Shanghai Jiaotong Univ. (Sci.

), 2011
DOI: 10.1007/s12204-010-1086-z

Implementation of Dynamic Matrix Control on

Field Programmable Gate Array
LAN Jian (

), LI De-wei (),

YANG Nan (

),

XI Yu-geng ()

(Department of Automation, Shanghai Jiaotong University; Key Laboratory of System Control and Information Processing,
Ministry of Education, Shanghai 200240, China)

Shanghai Jiaotong University and Springer-Verlag Berlin Heidelberg 2011

Abstract: High performance computer is often required by model predictive control (MPC) systems due to the
heavy online computation burden. To extend MPC to more application cases with low-cost computation facilities,
the implementation of MPC controller on eld programmable gate array (FPGA) system is studied. For the
dynamic matrix control (DMC) algorithm, the main design idea and the implemental strategy of DMC controller
are introduced based on a FPGAs embedded system. The performance tests show that both the computation
eciency and the accuracy of the proposed controller can be satised due to the parallel computing capability of
FPGA.
Key words: model predictive control (MPC), dynamic matrix control (DMC), quadratic programming (QP),
active set, programmable logic device, eld programmable gate array (FPGA)
CLC number: TP 273
Document code: A

0 Introduction
Due to the capability of handing constraints explicitly, model predictive control (MPC) is the unique
category of optimal control algorithms which can
deal with multi-variable systems subject to input and
state/output constraints. Therefore, MPC has been
widely applied in industrial process control. However,
since the constrained optimization problem has to be
solved online, MPC should be implemented by high
performance computers, which restricts its application
from the eld control facilities and low-cost computation devices. Recently, the application of MPC has been
greatly extended due to the increasing requirements of
various application elds. Hence, more and more attention has been paid to MPC controller for eld control
facilities. The main problem is how to implement MPC
controller by using low-cost computation devices.
Field programmable gate array (FPGA) technology
has been developed very quickly in recent years as a
Received date: 2010-07-06
Foundation item: the National Science Foundation of
China (Nos. 60934007 and 61074060), the Postdoctoral Science Foundation of China (No. 20090460627),
the Postdoctoral Scientific Program of Shanghai
(No. 10R21414600), the Specialized Research Fund
for the Doctoral Program of Higher Education
(No. 20070248004) and the China Postdoctoral Science
Foundation Special Support (No. 201003272)
E-mail: dwli@sjtu.edu.cn

class of programmable logic devices. It combines the

advantages of traditional software and hardware design
approach. So it not only guarantees the systems performance, but also makes the design of system more
exible and adaptable. It can also greatly reduce the
scale of the system hardware. Compared with digital
signal processing (DSP) processors, FPGA has more
programmable hardware resources and can directly implement complex algorithms in hardware. Meanwhile,
hardware resources of FPGA can be arranged according to dierent applications to increase resource utilization and computing eciency. On the other hand,
compared with application specic integrated circuit
(ASIC)[1] , FPGA has more exibility and adaptability,
which can greatly reduce the system design period[2] .
All these advantages make FPGA become a new highperformance computing system solution[3] which has
been widely applied in high-performance signal processing and other computing-intensive systems. Therefore,
although other microcontroller, such as advanced risk
machine (ARM), FPGA, DSP etc., can be the candidate hardware platforms for MPC controller, using
FPGA to implement MPC controller has attracted particular interest[4-6] .
In order to implement the MPC controller on FPGA
with high eciency and precision, the problems such
as designing the system structure of MPC controller,
arranging the control algorithm on the structure of
the system hardware/software and utilizing the paral-

J. Shanghai Jiaotong Univ. (Sci.), 2011

lel processing capabilities of FPGA as much as possible

are considered in this paper. Since dynamic matrix control (DMC) algorithm is a familiar MPC algorithm for
practical applications, this paper focuses on the design
of DMC controller based on FPGA. By analyzing run
time and the complexity of dierent parts of DMC algorithm, the original algorithm is decomposed. The part,
which can be completed by hardware and parallel logic,
is implemented by hardware design as much as possible.
And the others are completed by software. This design
can improve the eciency of MPC controller. In this
paper, the design is implemented on a XILINX FPGA
device (http://china.xilinx.com).

where, P (k) is the future output reference vector at

time k; Q and R are weight matrices on output errors and control input increments respectively; umax ,
umin , ymax and ymin are the constrained upper and
low bounds of input increments and outputs respectively; B = diag(B0 , , B0 ) and

1 DMC Algorithm[7-8]

By solving the optimization problem Eq. (1) online,

DMC controller can obtain the solution vector uM (k),
and acts its rst element u(k) on the plant. Then,
the future system output vector predicted by predictive
model is
yN1 (k) = yN0 (k) + au(k),
(2)

DMC is a predictive control algorithm, which is

widely accepted by practical applications.
Commonly, DMC controller includes three parts: predictive model, rolling horizon optimization, feedback/adjustment. The step response of the target system is used as its predictive model.
For a given system, let the value of step response
at each sample time as ai = (iT ), i = 1, 2, , N .
is step response parameter, T is sampling time,
N is the length of horizon of system model. a =
T
[a1 a2 aN ] is called the predictive model of the
system. Choosing the length of control horizon as M
and the length of optimization horizon as P , the dynamic matrix of DMC can be written as

a1
0
.

..
.

.
.

A = aM
a1
.
.

..
..

aP aP M+1
At time k, assume the control input increment as
uM (k). By using dynamic matrix A, it can be obtained that

B0 = .
.
.
1

0 0
.
.
1 . . ..

.
.. . .

. 0
.
1 1

more details about Eq. (2) are refered to Ref. [7].

Since there are always model errors or unknown disturbance in practical applications, DMC controller will
adjust the predictive result in Eq. (2) according to the
practical output y(k + 1). Let the error between the
predictive result in Eq. (2) and the real output as
+ 1|k).
e(k + 1) = y(k + 1) y(k

By the adjustment coecient vector h, the adjusted

predictive vector is
ycor (k + 1) = yN1 (k) + he(k + 1).

Quadratic
programming

Output

s.t.

umin  BuM (k)  umax ,

yP M (k) = yP 0 (k) + AuM (k),
ymin  yP M (k)  ymax ,

Plant

yP M (k) = yP 0 (k) + AuM (k),

min J(k) = P (k) yP M (k)Q +uM (k)R , (1)

(4)

At time k + 1, the whole procedure mentioned above is

repeated. The framework of DMC is shown in Fig. 1.

Predictive y
model

where yP M (k) is the predicted output at future under

future control increment uM (k), and yP 0 (k) is the
predicted outputs at future when uM (k) = 0. For
DMC, the vector yP 0 (k) can be obtained by shifting the
predicted zero-input output vector at last time ahead
one step.
The online optimization problem of DMC controller
can be formulated as

(3)

Shift

Adjustment

Fig. 1

The structure of DMC

For the DMC controller, the most important part is

how to solve the optimization problem Eq. (1) online,
which can be formulated as a quadratic programming
(QP) problem:
1
T
uT
M HuM + d uM ,
2
CuM  l,

min J(k) =
s.t.

(5)

J. Shanghai Jiaotong Univ. (Sci.), 2011

where
H = 2(AT QA + R),
dT = 2(P (k) yP M (k))T QA,
C = [B B A A]T ,
T

l = [umax umin ymax ymin ] .

From the algorithm of DMC mentioned above, it is
obvious that the key point to implement the DMC algorithm is to solve the QP online.

2 The Design of DMC Controller on

FPGA
2.1 The Algorithm of QP for DMC
The main task of DMC controller is repeatedly solving QP problem Eq. (5), which inuences the request
on hardware platform and the eciency of DMC controller. The QP problem is a classical mathematical
programming problem and many methods have been
proposed in literature, such as the active set method
and interior point method. By comparing these algorithms, it is easy to see that for the problem with
medium or small scale, the active set method can be
implemented with lower request on memory and calculation capability. Hence, for low-cost computation
devices and local control facilities, we adopt active set
method. The brief steps of active set method are introduced as follows.
Algorithm 1[9]
Step 1 Set the initial feasible solution x(1) and
calculate the equality-constraints.
Step 2 Calculate the search direction and solve an
equality-constrained quadratic program to get the optimal solution x(k+1) and Lagrange multiplier . Then,
the optimal search direction is d(k) = x(k+1) x(k) .
Step 3 If d(k) = 0, calculate the corresponding
Lagrange multiplier (k) ,
 If (k)  0, then x(k+1) is optimal solution for
the QP problem.
 Otherwise, calculate min (k) and subtract the
subject which corresponds to min (k) , then set
x(k+1) = x(k) and return to Step 2.
Step 4 If d(k) = 0, calculate the search step tk and
let x(k+1) = x(k) + tk d(k) . If tk < 1, then update the
ak corresponding constraint as a new active constraint,
else I(x(k+1) ) = I(x(k) ), I is the active set, set k =
k + 1 and return Step 2.
Remark For the above algorithm, linear programming (LP) is often adopted in Step 1 to obtain a feasible
solution of the QP problem. However, if there are no
constraints on future outputs, zero vector maybe a feasible solution for the QP problem in DMC. Therefore,
in the practical application, a switcher can be set for the
eld engineers to determine whether the LP is needed.

In addition, from the property of DMC, the feasible solution can be obtained according to the solution at last
time by moving it one time instant ahead.
2.2 Design of DMC on FPGA
Due to the advantages of exible design, parallel processing and low prices, FPGA is selected as the hardware platform to implement the DMC controller.
As described in Section 1, DMC algorithm is composed by predictive model, rolling horizon optimization,
and feedback/adjustment. It can be decomposed into
the following modules: shift and predictive, QP, adjustment, feedback, output. The structure is shown in
Fig. 2.
Shift and
predictive module

Quadratic
programming

Output
module
Plant

Adjustment
module

Fig. 2

Feedback
module

DMCs function diagram

According to the decomposition shown in Fig. 2, the

functions of hardware and software on FPGA can be
dened as follows: hardware functions include programmable I/O interface, A/D, D/A, matrix operators,
FPGAs hard or soft core processor, timer, memory,
etc.; software includes the initialization parameters of
DMC, QP and shift.
The following will introduce the QP hardware/software design and interface interaction in
detail. From Section 2.1, Algorithm 1 mainly includes
four steps, where Step 2 includes a mass of matrix
operations and is very time-consuming, especially for
matrix multiplication and matrix inversion.
By using the PROFILING tool to analyze the active set method on FPGA, it can be concluded that
the matrix multiplication occupies most of computing
time and is the critical operation for active set method.
To improve the computational eciency and utilize
FPGAs parallel computation capability, a matrix calculator should be designed separately from other modules, which can eciently calculate matrix multiplication, addition, subtraction and vector multiplication.
In addition, taking into account that to inverse matrix
by the logic device is complicated and resource consuming, the calculation of matrix inversion is implemented
by software.
Although the matrix calculator can remarkably improve the computational eciency, data exchange with
CPU needs much time and aects the total computing
eciency. So if we can integrate some control ow and
matrix calculator into a hardware module, the eciency
of design can be improved.
From the above analysis, the block diagram for system hardware design of DMC controller is shown in
Fig. 3.

J. Shanghai Jiaotong Univ. (Sci.), 2011

Static RAM

duce it.

Flash memory

ISE design suit

XILINX platform studio

A/D
D/A

CPU

GPIO
Process hardware
development

Matrix
calculator

Timer

GPIO General purpose input output

Fig. 3

Software sevelopment kit

The system hardware design block diagram

3 The Implementation of DMC Controller on FPGA

3.1 Implementation Procedure
With consideration of the resource and computational speed, the ML403 (http://china.xilinx.com/
products/devkits/hw-v4-ML403-uni-g.html) development board is selected as the hardware platform. The
ML403 development board includes XILINX VIRTEX
IV (XC4VFX12-10-g668) FPGA integrated circuit,
USB interface, ash memory, joint test ation group
(JTAG) interface, and oers a hardcore POWERPC405
processor. Correspondingly, we select XILINXs ISE
development kit as the development tool. Despite the
standard IP cores oered by XILINX, we can also
add custom IP core, which is written by VERILOG
HDL/VHDL (http://www.openhw.org).
The main design procedure of DMC controller is
shown in Fig. 4. In the following, we briey introTable 1

Hardware
platform

Software
development

Verificiation file
generatiom

Software
debug

Design
implementation

Software
profiling

Device
configuratiom

Device
configuratiom

ISEIntegrated software environment

Fig. 4

The process of implementation

Step 1 Build an embedded system hardware platform. Table 1 shows the overall system resource utilization.
Step 2 Prepare the embedded software. Write a
software program which includes DMC algorithm and
interfaces to hardware module.
Step 3 Debug software and hardware. Prepare the
test program. Then, debug and optimize our design.
Step 4 Hardware-in-the-loop verication. Compare the results between MATLAB simulation and implemented DMC controller. If the errors exceed the
allowable error precision, redesign of the entire system
will be taken.

The resource consumption on FPGA

FF
(Percentage)

LUTs
(Percentage)

DSP48
(Percentage)

Slice
(Percentage)

FIFO16/RAMB16
(Percentage)

DCM
(Percentage)

System colck

7 234(66%)

9 128(83%)

13(40%)

3 854(70%)

33(91%)

1(25%)

100 MHz

FFFlat flop, LUTLook up table, FIFOFirst input first output, RAMBRAM blok, DCMDigital clock management

Control and
management
module

Operating module

Control
singal

Data

Control
singal

Storage module
Data

3.2 Implementation of Main Modules

From the analysis of Section 2, the matrix operation
is the bottleneck for the eciency of DMC controller.
Here, we give a design to improve the eciency by making use of the parallel computation of FPGA.
In order to achieve arbitrary dimensions of the matrix multiplication, we decompose matrix multiplication into product of vectors which can be completed by
the FIFO and oat multiplier. This is completed by the
operating module shown in Fig. 5.
In the above matrix calculator, the control management module is used to store the dimension of the information about matrices and generate control signals for
the operating module and storage module. Operating
module is used to calculate matrix operations such as
multiplication, addition and subtraction. Storage mod-

FPGA bus

Fig. 5

The structure of matrix calculator

ule stores the results of matrix operation, which can

be accessed by the FPGA processor local bus. In summary, the matrix calculator module integrates the function of solving QP problem with equality constraints

J. Shanghai Jiaotong Univ. (Sci.), 2011

FPGA, the outputs, inputs and input increments are

shown in Figs. 68, where the results of MATLAB are
shown in left and FPGA in right. Figure 9 gives the
errors of outputs, inputs and input increments between
DMC controller implemented by FPGA and MATLAB
respectively. From these gures, we can conclude that
the dierences between DMC running in FPGA and
MATLAB are trivial and can be ignored.
For dierent control horizon M , the average computing time of using or not using hardware matrix calculator are shown in Table 2 where t is average time without matrix operator, tm is average time using matrix
operator, te is average time using equation quadratic
program operator. Table 2 shows that the average calculation speed of using hardware matrix calculator is
much faster.

to eliminate the temporary data exchange between the

module and CPU, which can reduce the calculation
time.

4 Testing of DMC Controller

To verify our DMC controller, we select the following
MIMO linear time-invariant system as a test object:

y2

2
s2 + 2s + 2
=
3
s2 + 4s + 8

1

s + 1 u1 .

1
u2
2
s + 2s + 5

Taking the sampling time T = 0.2 s, and choosing predictive horizon and control horizon as 10 and 2 respectively. The error precision is 10e6 and the constraints
are:

Table 2

|u1 |  0.2, |u2 |  0.2,

0  y1  0.9, 0  y2  0.65,
0.5  u1  3,

2  u2  0.

And the references of the output are 0.8 and 0.6 respectively.
To compare DMC implemented by MATLAB and
0.8

y1

0
20 40 60 80 100
Sample times
MATLAB

tm /ms

te /ms

5.14

0.52

0.28

18.71

1.21

0.64

39.86

4.79

2.45

0.6
0.4

0.4

0.2

0.2
20 40 60 80 100
Sample times

20 40 60 80 100
Sample times

Fig. 6

The comparison of outputs (T = 0.2 s)

3

0.5

0.5

1.0

1.5
2.0
20 40 60 80 100
0
Sample times
MATLAB

20 40 60 80
Sample times

1.5

100

1.0

20 40 60 80 100
Sample times

2.0
0

The comparison of inputs (T = 0.2 s)

0.2

0.2

0.1

0.1

0.1

0.1

0.1
0.2
0

u1

0.2

u2

0.2

20 40 60 80 100
Sample times

FPGA

Fig. 7

u1

u2

u2

u1

u1

20 40 60 80 100
Sample times

FPGA

0.1
0.2
20 40 60 80 100
0
Sample times
MATLAB

Fig. 8

u2

y1

y2
0.2

0.2

t/ms

0.6

0.4

0.4

0.8

0.6

0.6

The comparison of the average computing

time

y2


y1

0.1

0.1
20 40 60 80 100
Sample times

0.2
0

0.2
20 40 60 80 100
0
Sample times
FPGA

The comparison of input increments (T = 0.2 s)

20 40 60 80 100
Sample times

Error of u2 106

Error of u1 106

J. Shanghai Jiaotong Univ. (Sci.), 2011

2
0

2
4
0

10

20

30

40 50 60
Sample times

Fig. 9

70

80

90

100

0
5

10
0

10

20

30

40 50 60
Sample times

70

80

90

100

The errors of input increments (T = 0.2 s)

When using hardware matrix calculator, the computing time of dierent iteration steps are shown in Table 3.
This table shows that when the system state is close to
the steady-state, the computing time is shorter. However, at the beginning of control, the computing time is
much longer. Therefore, the sampling time should be
determined by the computing time at the beginning.
Table 3

The time-consuming of every step in

average of dierent iterations

Iterations

Time consumption (Total)/ms

0.58 (0.58)

0.56(2.81)

10

0.55(5.45)

40

0.42(16.8)

100

0.29(28.6)

5 Conclusion
This paper studies an MPC controllers implementation on FPGA. By using the FPGAs parallel process
capacity, proper design and resources utilization, the
DMC algorithm is implemented for small scale applications with limited computing capacity. Performance
testing shows that our design is more eective compared
to traditional implementations.
Considering the complexity of MPC algorithm and
the variety of FPGA systems, the design can be further
improved by increasing the percentage of algorithm implemented by hardware in the future research. Meanwhile, optimizing hardware layout and interconnection
by tools such as XILINX ISE can reduce signal delay
and race and hazard phenomenon, thus improve the

eectiveness and robustness of the whole controller.

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