Professional Documents
Culture Documents
Microprocessor Architecture
Data Bus
Address Bus
4004
8008
8088
8086
16
20
80286
16
24
IBM PC/AT
80386DX
32
32
80486
32
32
Pentium
64
32
232 = 4 GB of Memory
Pentium II
64
Pentium III
64
Pentium IV
64
The
8086
and
8088
Unidirectional.
Information flows out of the microprocessor and
into the memory or peripherals.
Bi-directional.
Information flows both ways between the
microprocessor and memory or I/O.
INTR
NMI
MN / MX
RD
WR
HOLD
HLDA
M / IO
OEN
ALE
INTA
TEST
READY
RESET
I/O Devices
Instruction Pointer
IP
CS
DS
Segment Registers
SS
ES
Data Registers
AH
AL
AX
BH
BL
BX
CH
CL
CX
DH
DL
DX
SP
BP
SI
DI
Status Register
Processors & Assembly Language
Code Segment
Data Segment
Stack Segment
Extra Segment
Accumulator
Base Register
Counter
Data Register
Stack Pointer
Base Pointer
Source Index
Destination Index
SR
10
11
Segmented Memory
Each Segment Register
points to the starting
address of a particular
segment of memory
FFFFFH
Code Segment
(64Kbytes)
CS
DS
SS
Data Segment
(64Kbytes)
ES
Stack Segment
(64Kbytes)
Extra Segment
(64Kbytes)
00000H
12
Code Segment CS
Stack Segment SS
Data Segment DS
Extra Segment ES
13
14
15
Offset Register
Segment Register
0000
20 bit adder
20 bit address
Processors & Assembly Language
16
Segment Registers
SS
ES
Code Segment
Data Segment
Stack Segment
Extra Segment
BP
SI
DI
Stack Pointer
Base Pointer
Source Index
Destination Index
17
Examples
If the segment Base = 1234H and Offset is 0022H,
what is the physical address?
What would be the offset required to map to
physical address location 002C3H if the contents
of the corresponding Segment register are
002AH?
18
19
00726H
A0H
00725H
55H
00724H
02H
If the 8086 asks for the contents of
address 00724H, what will it get
00723H
F2H
back from memory?
Memory will return the value 5502H on the data
bus.
20
00004H
Byte 4
00003H
Byte 3
00002H
Byte 2
00001H
Byte 1
00000H
Byte 0
} word 1
} word 0
00004H
Byte 4
00003H
Byte 3
00002H
Byte 2
00001H
Byte 1
00000H
Byte 0
} word 3
} word 2
21
22
00105H
i, j;
c;
00104H
Byte 0
00103H
Byte 1
00102H
Byte 0
00101H
Byte 1
00100H
Byte 0
c
j
}
main ()
{
char
int
c;
i, j;
00105H
00104H
Byte 1
00103H
Byte 0
00102H
Byte 1
00101H
Byte 0
00100H
Byte 0
23
24
Aligned Double
If the double word starts at a memory address that
is a multiple of 4, it is called an aligned double.
00008H
00007H
Byte 7
00006H
Byte 6
00005H
Byte 5
00004H
Byte 4
00003H
Byte 3
00002H
Byte 2
00001H
Byte 1
00000H
Byte 0
}
}
Double word 1
Double word 0
25
Misaligned double
0000BH
Byte 11
0000AH
Byte 10
00009H
Byte 9
00008H
Byte 8
00007H
Byte 7
00006H
Byte 6
00005H
Byte 5
00004H
Byte 4
00003H
Byte 3
00002H
Byte 2
00001H
Byte 1
00000H
Byte 0
Double word 1
Double word 0
26
27
00103H
*i;
j;
c;
}
main ()
{
char
int
int
00102H
Byte 0
00101H
Byte 1
00100H
Byte 0
000FFH
Byte 3
000FEH
Byte 2
000FDH
Byte 1
000FCH
Byte 0
c
j
00103H
c;
*i;
j;
00102H
Byte 1
00101H
Byte 0
00100H
Byte 3
000FFH
Byte 2
000FEH
Byte 1
000FDH
Byte 0
000FCH
Byte 0
28
Data Types
Nibble
Byte
Word
Double word
4 bits
8 bits
16 bits
32 bits
29
Unsigned Integer
All of the bits represent significant value.
The number is considered an absolute value.
Signed Integer
The most significant bit represents the sign of the
number.
If the MSB is 0, the number is positive and the rest of the
bits represent the bits of the number.
If the MSB is 1, the number is negative and the rest of
the bits represent the 2s complement of the actual
number.
30
Range of Representation
31
32
BCD Representation
10004
89
10003
10002
09
10001
08
10000
33
Meanings of Data
10004
89H
10003
B3H
10002
29H
10001
08H
10000
It cannot be BCD as the 2nd digit is > 9.
It might be the value 31 (unsigned) or +31 (signed).
1FH
34
35
FFFFFH
FFFFCH
FFFFBH
FFFEFH
Reserved
Dedicated
General Use
Memory Space
0007FH
Reserved
00014H
00013H
00000H
Dedicated
36
Memory
Processor
IP
Next Instruction
Current Code
Segment
CS
IP is typically incremented by 2
after reading the current instruction.
Why?
37
AL
BX
BH
BL
CX
CH
CL
DX
DH
DL
}
}
}
}
Accumulator
Base Register
Count Register
Data Register
38
39
40
The Stack
Memory
Stack Segment
SP
Stack
Growth
Processor
Top
SS
End
Bottom
41
The Stack
42
Stack Instructions
PUSH AX
Decrement SP by 2
This moves the top of the stack (TOS) pointer 2 memory
location higher than the current location.
POP AX
Copy the contents of TOS to AX.
AX is 16 bits. Therefore, the contents of 2 memory
locations will be copied.
Increment SP by 2.
Move the TOS pointer below the value that has just been
poped.
Processors & Assembly Language
43
AX
00
BA
50
06
32
1050B
01H
1050A
12H
10509
3BH
10508
B5H
10507
A2H
10506
29H
10506
10505
FEH
10505
10504
32H
10504
10503
4DH
10503
10502
00H
10501
12H
10501
10500
56H
10500
Before
SS
1050B
1050A
Stack
SP
10
SP
10509
10508
AX
Junk
SS
10507
10502
After
By the way the stack segment in this example is close to filling up.
Dr. Bassel Soudan &
Processors & Assembly Language
Dr. Ali El-Moursy
44
AX
00
BA
50
06
32
1050B
01H
1050A
12H
10509
3BH
10508
B5H
10507
A2H
10506
29H
10506
10505
FEH
10505
10504
32H
10504
10503
4DH
10503
10502
00H
10501
12H
10501
10500
56H
10500
Before
Processors & Assembly Language
SS
1050B
1050A
Stack
SP
10
SP
10509
10508
AX
Junk
SS
10507
10502
After
Dr. Bassel Soudan &
Dr. Ali El-Moursy
45
46
47
A 16 bit register to hold indicator bits. Not all bits are used.
11
10
OF
DF
IF
TF
SF
ZF
AF
PF
CF
Carry Flag
Parity Flag
Auxiliary Carry
Zero
Sign Flag
Trap Flag
Interrupt Enable
Direction Flag
Overflow Flag
48
Carry Flag
The bit is set to 1 if the previous operation resulted in a carry out or
borrow in.
Parity Flag
The bit is set to 1 if the previous operation resulted in a value that
has even Parity
Auxiliary Carry
The bit is set to 1 if the previous operation resulted in a carry out
from low nibble to high nibble
Zero Flag
Set to 1 if the previous operation resulted in a zero result.
Otherwise the bit is set to 0.
Sign Flag
Set to 1 if the previous operation resulted in a negative numbers.
Overflow
Set to 1 if the previous operation resulted in a signed value that is
out of range.
49
Review
Each Segment Register
points to the starting
address of a particular
segment of memory
FFFFFH
Code Segment
(64Kbytes)
CS
DS
SS
Data Segment
(64Kbytes)
ES
Stack Segment
(64Kbytes)
Extra Segment
(64Kbytes)
00000H
50
Instruction Pointer
IP
CS
DS
Segment Registers
SS
ES
Data Registers
AH
AL
AX
BH
BL
BX
CH
CL
CX
DH
DL
DX
SP
BP
SI
DI
Status Register
Processors & Assembly Language
Code Segment
Data Segment
Stack Segment
Extra Segment
Accumulator
Base Register
Counter
Data Register
Stack Pointer
Base Pointer
Source Index
Destination Index
SR
51
0000
Offset Register
Segment Register
0000
20 bit adder
20 bit address
52