IEEE TRANSACTIONS ON POWER ELECTRONICS, VOL. 28, NO.

12, DECEMBER 2013

5535

Novel Interleaved Bidirectional Snubberless

Soft-Switching Current-Fed Full-Bridge
Voltage Doubler for Fuel-Cell Vehicles
Pan Xuewei, Student Member, IEEE, and Akshay K. Rathore, Senior Member, IEEE

AbstractThis paper presents a novel interleaved soft-switching

bidirectional snubberless current-fed full-bridge voltage doubler
(dc/dc converter) for an energy storage system in fuel cell electric vehicles. A novel secondary modulation technique is also proposed to clamp the voltage across the primary-side switches naturally with zero-current commutation. It, therefore, eliminates the
necessity for an external active-clamped circuit or passive snubbers to absorb the switch turn-off voltage spike, a major challenge
in current-fed converters. Zero-current switching of primary-side
devices and zero-voltage switching of secondary-side devices are
achieved, which significantly reduce switching losses. An interleaved design is adopted over a single cell to increase the power
handling capacity obtaining merits of lower input current ripple,
reduction of passive components size, reduced device voltage and
current ratings, reduced conduction losses due to current sharing,
and better thermal distribution. Primary device voltage is clamped
at rather low-reflected output voltage, which enables the use of
low-voltage semiconductor devices having low on-state resistance.
Considering input current is shared between interleaved cells, conduction loss of the primary side, a considerable part of total loss,
is significantly reduced and higher efficiency can be achieved to
obtain a compact and higher power density system. Steady-state
operation, analysis, and design of the proposed topology have been
presented. Simulation is conducted over software package PSIM
9.0.4 to verify the accuracy of the proposed analysis and design.
A 500-W prototype has been built and tested in the laboratory to
validate the converter performance.
Index TermsCurrent-fed converter, fuel-cell vehicle (FCV),
interleaving, snubberless, soft-switching.

I. INTRODUCTION
RANSPORTATION electrification has become a clear tendency owing to lower emission, better vehicle performance, and higher fuel economy than conventional internal
combustion (IC) engine-based vehicles. Over the past decades,
electric vehicles, hybrid electric vehicles, plug-in hybrid electric
vehicles, and fuel-cell vehicles (FCVs) are emerging means of

Manuscript received October 31, 2012; revised January 16, 2013; accepted
February 21, 2013. Date of current version June 6, 2013. This work was supported by the Singapore Ministry of Education Academic Research Fund Tier 1
under Grant R-263-000-627-133. However, any opinions, findings, conclusions,
or recommendations expressed herein are those of the authors and do not necessarily reflect the views of the Singapore Ministry of Education. Recommended
for publication by Associate Editor N. Kar.
The authors are with the Department of Electrical and Computer Engineering, National University of Singapore, 117576 Singapore (e-mail: a0082351@
nus.edu.sg; eleakr@nus.edu.sg).
Color versions of one or more of the figures in this paper are available online
at http://ieeexplore.ieee.org.
Digital Object Identifier 10.1109/TPEL.2013.2252199

Fig. 1.

Architecture of a fuel cell car.

transportation to replace the conventional IC vehicle by using

a three-phase electric motor for propulsion. With the merits of
cleanliness (zero-emission), satisfied driving range, short refueling time, high efficiency, high reliability, FCVs exhibit significant potential in transportation. Several major automotive
industries are manufacturing and testing their FCV. Since 2009,
over 20 FCV prototypes and demonstration cars, such as Mazda
5 Hydrogen RE Hybrid, Volkswagen CaddyMaxi HyMotion,
Hyundai Tucson-ix35 FCEV, Mercedes-Benz-F800, have been
released [1], [2]. Ballard designed fully integrated fuel-cell modules delivering 75 and 150 kW for local bus transportation in
London, which operates up to 19 h without refueling [3].
The typical architecture of a fuel cell car is illustrated in
Fig. 1 [2][8]. The fuel-cell stack converts hydrogen gas stored
onboard after reaction with oxygen from air, i.e., oxidization,
into electricity to drive the electric motor. As long as continuity
of fuel supply is maintained, the electric motor can propel the
vehicle quietly, smoothly, and efficiently requiring less maintenance. However, FCVs suffer from slow dynamic response to
load variation due to their slow internal electrochemical, mechanical, and thermal dynamic characteristics and, therefore,
needs energy storage that can deliver quick power. An auxiliary
energy storage system (ESS) such as battery or supercapacitor
is usually utilized for cold start up, absorbing the regenerative
braking energy, and achieving good performance during transient operation.
As illustrated by a functional diagram of a typical fuel-cellpowered propulsion system in Fig. 2 [9], a fuel cell is connected
to a high-voltage dc bus acting as the main source of power. A
bidirectional dc/dc converter is utilized to interface the auxiliary
power source ESS to high-voltage dc bus. This dc/dc converter
plays a vital role in coordination with the main power source

0885-8993/$31.00 2013 IEEE

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Fig. 2.

IEEE TRANSACTIONS ON POWER ELECTRONICS, VOL. 28, NO. 12, DECEMBER 2013

Functional diagram of a fuel cell propulsion system [9].

and auxiliary power source, which needs to satisfy the following

requirements: 1) a high step-up ratio to boost low terminal voltage of batteries to variable high-voltage fuel-cell dc bus (150
300 V); 2) bidirectional power flow. The converter should be
able to supply energy during the cold startup and transition operation in the forward direction and absorb energy during regenerative braking in the reverse direction; 3) high power handling
power capacity; 4) high-frequency (HF) operation to obtain a
compact, lightweight, high power density, and low cost system;
and 5) high efficiency. It is a general requirement to obtain an
efficient utilization of energy and a reduced thermal design.
Several bidirectional dc/dc converters for FCV have been proposed in the literature [9][18]. Voltage-fed converters [11][13]
suffer from several limitations, i.e., high pulsating current at input, limited soft-switching range, rectifier diode ringing, duty
cycle loss [20], and comparatively low efficiency for highvoltage amplification and high input current applications. Compared with voltage-fed converters, current-fed converters have
been justified and demonstrated as a suitable option for such
applications. One of the very popular topologies is a current-fed
dual active bridge converter with a HF transformer. However,
the major drawback with such a converter is high voltage spike
at device turn-off owing to the energy stored in the leakage inductance. An RCD snubber circuit was employed [14] to limit
voltage overshoot. A similar approach was applied in [15] with a
lossless snubber circuit to reduce the voltage stress of switches.
In [16][19], an active clamping snubber circuit is used, which
consists of an active switch and a capacitor, to clamp the device voltage and achieve ZVZCS at the same time. However,
the disadvantages such as high current stress, higher circulating
current at light load, and related thermal issues exist.
In this paper, a novel secondary modulation-based interleaved
soft-switching bidirectional snubberless current-fed full-bridge
voltage doubler is proposed, as shown in Fig. 3. The proposed
converter consists of two interleaved cells with a current-fed
full-bridge switches connected in parallel on the low-voltage
side and a half-bridge voltage doublers connected in series
on the high-voltage side. For this application, interleaved approaches (multicell) are adopted over a single cell to increase
the power handling capacity while achieving high efficiency and
reduced thermal requirements. A voltage doubler or half-bridge
is selected to reduce the number of switches, the transformer
turns ratio, and voltage ratings of secondary-side devices. The
proposed converter offers the following merits:
1) Switching losses are reduced significantly owing to ZCS of
primary switches and ZVS of secondary switches, which
also permits higher switching frequency operation with

Fig. 3.

2)

3)

4)

5)

6)

Proposed interleaved ZCS current-fed full-bridge dc/dc converter.

smaller magnetics. It thus achieves a compact and high

power density system.
The voltage across primary-side devices is independent
of the duty cycle with varying input voltage and output
power and clamped at rather low-reflected output voltage.
It avoids the need of a passive snubber or active-clamped
circuit [21][24] making it snubberless and enables the
use of semiconductor devices of low voltage rating, which
have low on-state resistance. Therefore, the conduction
loss is significantly reduced and higher efficiency can be
achieved.
A high step-up ratio is satisfied due to the inherent boost
function of the current-fed topology and use of an HF
transformer.
An interleaved design increases the power handling capacity and reliability. In the case of failure of one of the
cells, the system can still function, delivering 50% of rated
power.
Reduction in the size of passive components. Input and
output filters size is reduced due to continuous current
and high ripple frequency owing to interleaving.
Bidirectional power flow. In the forward direction, the
proposed converter works as a current-fed converter. In the
reverse direction, the converter acts as a standard voltagefed half-bridge isolated dc/dc converter with an inductive
output filter. It has been reported in the literature [25][27],
and therefore, this paper does not emphasize on it.
II. OPERATION AND ANALYSIS OF THE CONVERTER

In this section, a steady-state operation and analysis with the

ZCS concept has been explained. Before turning-off of a diagonal switch pair (S1 S4 , S2 S3 , S5 S8 , or S6 S7 ) at the primary
side, the other pair of the primary-side switches is turned ON.
The reflected output voltage Vo /4n appears across the transformer primary. It diverts the current from one switch pair to
the other pair causing current through one switch pair to rise
and the other pairs current to fall to zero. Later, the body
diodes across the switch pair start conducting and their gating signals are removed leading to ZCS turn-off of devices.
Then, the device voltage rises and is clamped at reflected output
voltage.

XUEWEI AND RATHORE: NOVEL INTERLEAVED BIDIRECTIONAL SNUBBERLESS SOFT-SWITCHING

5537

For the simplicity of the study of operation and analysis, the

following assumptions are made for the operation and analysis
of the converter: 1) boost inductors L1 and L2 are large enough
to maintain constant current through them. Output capacitors
Co1 , Co2 , Co3 , and Co4 are large enough to maintain constant voltage across them; 2) all components are assumed ideal;
3) series inductors Llk 1 and Llk 2 include the leakage inductances of the HF transformers; and 4) magnetizing inductances
of the transformers are infinitely large.
The steady-state operating waveforms are shown in Fig. 4.
The primary switches pairs S1 S4 and S2 S3 in Cell 1 are
operated with identical gating signals phase shifted with each
other by 180 and the duty cycle should be kept more than 50%.
The same for the switches pairs S5 S8 and S6 S7 in Cell 2.
The phase difference between gating signals of switches pairs
S1 S4 and S5 S8 is 90 . The operation of the converter during
different intervals in a one-quarter cycle is explained with the
help of equivalent circuits shown in Fig. 5. For the rest of the
HF cycle, the intervals are repeated in the same sequence with
other symmetrical devices conducting to complete the full HF
cycle.
Interval 1 [see Fig. 5(a); to < t < t1 ]:
CELL 1: In this interval, primary switches S2 and S3 and antiparallel body diode D10 of secondary-side switches are conducting. The current through inductor Llk 1 is negative and constant.
The currents through main components are iS 2 = iS 3 = Iin /2,
iS 1 = iS 4 = 0, iL lk 1 = Iin /2, iD 10 = Iin /2n. Voltages across
the switches S1 and S4 are VS 1 = VS 4 = Vo /4n.
CELL 2: In this interval, all four primary switches of Cell 2
are conducting. A negative voltage across the inductor Llk 2 is
equal to Vo /4n and current through it is decreasing linearly. The
currents through the switching devices are given by
iL lk 2 = IL lk 2 (t0 )

Vo
(t t0 )
4n Llk

(1)

iS 5 = iS 8 = IS 5 (t0 )

Vo
(t t0 )
8n Llk

(2)

iS 6 = iS 7 = IS 6 (t0 ) +

Vo
(t t0 )
8n Llk

(3)

iD 11 =

Vo
IL lk 2 (t0 )
2
(t t0 ).
n
4n Llk

(4)

Before the end of this interval t = t1 , the anti-parallel body

diode D11 of switch S11 is conducting. S11 can be gated ON
for ZVS turn-on. Final values: iL lk 2 = 0, iS 5 = iS 6 = iS 7 =
iS 8 = Iin /4, iD 11 = 0.
Interval 2 [see Fig. 5(b); t1 < t < t2 ]:
CELL 1: Interval 2 stays the same with interval 1.
CELL 2: In this interval, S11 is turned ON with ZVS. Currents
through all the switching devices of Cell 2 continue to increase
or decrease with the same slope as interval 1.
Interval 3 [see Fig. 5(c); t2 < t < t3 ]:
CELL 1: At t = t2 , primary switches S1 and S4 are turned
ON. The corresponding snubber capacitors C1 and C4 discharge
in a very short period of time. And then, all four primary switches
of Cell 1 are conducting. A positive voltage equal to Vo /4n
appears across the inductor Llk 1 and the current through it starts

Fig. 4. Operating waveforms of the proposed interleaved ZCS current-fed

dual active bridge converter.

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IEEE TRANSACTIONS ON POWER ELECTRONICS, VOL. 28, NO. 12, DECEMBER 2013

Fig. 5. Equivalent circuits during different intervals of operation of the proposed converter for the waveforms shown in Fig. 4. (a) Interval 1. (b) Interval 2.
(c) Interval 3. (d) Interval 4. (e) Interval 5. (f) Interval 6. (g) Interval 7. (h) Interval 8. (i) Interval 9. (j) Interval 10. (k) Interval 11.

to increase linearly. Switches S1 and S4 start conducting with

zero current which helps to reduce associated turn-on loss. The
currents through the devices are given by
iL lk 1 =

Vo
Iin
+
(t t2 )
2
4n Llk

(5)

iS 1 = iS 4 =

Vo
(t t2 )
8n Llk

(6)

iS 2 = iS 3 =

Vo
Iin

(t t2 )
2
8n Llk

(7)

iD 10 =

Vo
Iin
2
(t t2 ).
2n 4n Llk

(8)

CELL 2: In this interval, currents through all the devices of

Cell 2 continue to increase or decrease with the same slope
as interval 2. At the end of this interval, the switch currents
iS 5 and iS 8 reach zero, obtaining ZCS of S5 and S8 . Final
values are iL lk 2 = Iin /2, iS 6 = iS 7 = Iin /2, iS 5 = iS 8 = 0,
and iS 11 = Iin /2n.
Interval 4 [see Fig. 5(d); t3 < t < t4 ]:
CELL 1: In this interval, currents through all the switching
devices of Cell 1 continue to increase or decrease with the same
slope as interval 3.
CELL 2: In this interval, the current through inductor
Llk 2 keeps decreasing and body diodes D5 and D8 start
conducting. At the end of this interval, currents through

XUEWEI AND RATHORE: NOVEL INTERLEAVED BIDIRECTIONAL SNUBBERLESS SOFT-SWITCHING

inductor Llk 2 , switches S6 and S7 reach their peak values.

This interval should be very short to limit the peak current
through the components, reducing the current stress and kVA
ratings.
The currents through operating components are given by
iL lk 2 =

Vo
Iin

(t t4 )
2
4n Llk

(9)

iS 6 = iS 7 =

Vo
Iin
+
(t t4 )
2
8n Llk

(10)

iD 5 = iD 8 =

Vo
(t t4 )
8n Llk

(11)

iS 11 =

Vo
Iin
+
(t t4 ).
2n 4n2 Llk

(12)

Interval 5 [see Fig. 5(e); t4 < t < t5 )]:

CELL 1: In this interval, currents through all the switching
devices of Cell 1 continue to increase or decrease with the same
slope as interval 3.
CELL 2: During this interval, primary switches S5 and S8 are
switched OFF. Since body diodes D5 and D8 are conducting,
S5 and S8 are ZCS turned OFF. At the same moment, secondary
switch S11 is turned OFF. An anti-parallel body diode of switch
S12 takes over the current immediately. The voltage across the
inductor Llk 2 becomes positive and the current through it starts
increasing. The currents through the switches S6 and S7 and
body diodes D5 and D8 start to decrease.
The currents through operating components are given by
iL lk 2 = Ilk ,p eak +

Vo
(t t5 )
4n Llk

iS 6 = iS 7 = Isw ,p eak
iD 5 = iD 8 = ID 2,p eak
iD 12 =

Vo
(t t5 )
8n Llk
Vo
(t t5 )
8n Llk

Vo
Ilk ,p eak
2
(t t5 ).
n
4n Llk

(13)
(14)
(15)
(16)

At the end of this interval, currents through D5 and D8 reduce

to zero. Final values are iL lk 2 = Iin /2, iS 6 = iS 7 = Iin /2, iD 5 =
iD 8 = 0, and iD 12 = Iin /2n.
Interval 6 [see Fig. 5(f); t5 < t < t6 ]:
CELL 1: In this interval, currents through all the switching
devices of Cell 1 continue to increase or decrease with the same
slope as interval 3.
Before the end of this interval t = t6 , the body diode D10 of
switch S10 is conducting. S10 can be gated ON for ZVS turn-on.
Final values are iL lk 1 = 0, iS 1 = iS 2 = iS 3 = iS 4 = Iin /4, and
iD 10 = 0.
CELL 2: Snubber capacitors C5 and C8 charge to Vo /4n
in a very short period of time. Constant current is flowing
through switch S7 , inductor Llk 2 , S6 , and the body diode of
the secondary switch S12 . The currents through main components are iS 6 = iS 7 = Iin /2, iS 5 = iS 8 = 0, iL lk 2 = Iin /2,
and iD 12 = Iin /2n. The voltage across the switches S5 and S8
is VS 5 = VS 8 = Vo /4n.

5539

III. DESIGN OF THE CONVERTER

In this section, design is illustrated by a design example with
a converter of the following specifications: minimum input voltage Vin = 12 V, output voltage Vo = 150300 V, nominal output
voltage = 300 V, output power Po = 500 W, and switching
frequency fs = 100 kHz. The design equations are presented to
determine the components ratings. It helps the selection of the
components and to analytically predict the performance of the
converter.
1) The average input current is Iin = Po /(Vin ). Assuming
an ideal efficiency of 95%, Iin = 43.9 A.
2) The maximum voltage across the primary switches is
Vo
.
(17)
4n
3) The voltage conversion ratio or input and output voltages
are related as
2 n Vin
Vo =
.
(18)
1d
4) The leakage inductance of the transformer or series inductance Llk is calculated using
VP ,SW =

Llk =

Vo (d 0.5)
.
4 n Iin fs

(19)

5) The RMS current through the primary switches is given

by

Iin 2 d
.
(20)
IP ,rm s =
2
3
The calculated value is IP ,rm s = 13.85 A.
6) The output power can be derived as
P =

2
vo vin (3 4d)
4n vin
.
16 n Llk fs

(21)

The transformer turns ratio selection is based on conduction losses, which mainly consist of the conduction
losses in the primary switches because they carry higher
currents. Increasing the turns ratio can reduce the maximum voltage across the primary switches, which makes
it possible to use low voltage rating switches with lower
on-state resistance [from (17)]. The leakage inductance of
the transformer Llk decreases with the increase of turnsratio, thus improving the power transferring ability of the
converter [from (21)]. Power transferring capacity is limited by the leakage inductance of the HF transformer. In
addition, when the converter works in the reverse direction to absorb the energy owing to regenerative braking,
smaller leakage inductance will result in smaller duty cycle loss. However, higher turns ratio yields higher switch
RMS current [from (18) and (20)]. Voltage regulation over
varying fuel cell dc bus with varying battery terminal voltage is another concern to be addressed during design. An
optimum turns ratio n = 2.5 and duty ratio d = 0.8 are
selected to achieve low overall conduction losses. Output
voltage can be regulated from 150 to 300 V by modulating the duty ratio from 0.5 to 0.8. Leakage inductance of
Llk = 2.05 H is obtained from (19) for the given values.

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IEEE TRANSACTIONS ON POWER ELECTRONICS, VOL. 28, NO. 12, DECEMBER 2013

7) The RMS current through the primary winding of each

HF transformer is given by

Iin 5 4d
.
(22)
IL lk ,rm s =
2
3
The calculated value of IL lk ,rm s = 17 A.
8) The value of the boost inductor is given by
L=

Vin (d 0.5)
I fs

(23)

(24)
(25)

The calculated value of ID ,rm s = 4.39 A.

10) The RMS current through the secondary-side switches is
given by

Iin 2d 1
.
(26)
IS,rm s =
4n
3
The calculated value of IS,rm s = 1.96 A.
The voltage rating of the secondary-side devices is Vo /2 =
150 V.
11) The VA rating of each HF transformer is given by

Vo Iin 2 (5 4d) (1 d)
.
(27)
V Ax-m er =
8n
3
The calculated value is V AX -m er = 321.9 VA.
A loss modeling of the proposed converter can be done by
considering the static loss of primary- and secondary-side
switches, boost inductors, output capacitors, HF transformer, and switching loss of switches.
12) The conduction loss of each boost inductor is given by
PL ,Con = RL IL2 ,rm s =

2
RL Iin
4

(28)

PP ,Con = rP ,on

IP2 ,rm s

2
PS,Con = rS,on IS,rm
s

rP ,on

(2 d)
=
12
2

+ rD ID
,rm s + vD iD

Csnubb er Vp2 fs
+0
2

Csnubb er Vo2 fs
16 n2

(31)

PS,Sw = PSw ,on + PSw ,o = 0 +

=

V I fs tf
6

Vo Iin fs tf
12 n

(32)

where tf is the fall time of the secondary-side switches during

turn-off.
The copper loss of the HF transformer is given by
PTr,Copp = rpri IL2 lk ,rm s + rsec

IL2 lk ,rm s
n2

Pcore = Physteresis + Peddy

Physteresis =

2
Bm

Vc fs
2u

2
Peddy = Ke fs2 Bm
0

2
2
(2d 1) rD Iin
(11 10d)
rS,on Iin
+
48 n2
48 n2
vD Iin (7 6d)
(30)
+
16 n

where rP ,on and rS,on are the on-resistances of the primary- and
secondary-side switches, respectively. vD is the forward voltage
of the body diode of secondary-side switches.

(34)
(35)
(36)

where Physteresis represents the hysteresis loss of the core and

Peddy represents the eddy current loss. Since the ferrite material
with high resistivity is used, the eddy current is negligible.
The equivalent series resistance (ESR) loss of output capacitors is given by
2
2
Pcap = rcap (IS,rm
s + ID ,rm s )

(37)

where rcap is the ESR of each output capacitor.

The total loss is given by
Ploss = PL ,Con 2 + (PP ,Con + PP ,Sw ) 8
+ (PS,Con + PS,Sw ) 4 + (PL ,core + PTr,core ) 2
(38)

The transfer efficiency is given by

=

(29)

(33)

where rpri and rsec are ohmic resistances of primary and secondary sides of the HF transformer respectively.
The core loss of the boost inductor and the HF transformer
can be calculated by

+ PTr,Copp 2 + Pcap 4.

where RL is the ohmic resistance of the boost inductor.

The conduction losses of the primary- and secondary-side
switches are given by
2
Iin

PP ,Sw = PSw ,on + PSw ,o =

=

where I is the boost inductor ripple current. For I =

1 A, L = 36 H.
9) The average current and RMS current through the body
diodes of secondary devices are given by
iD = Iin (7 6d)
16n

Iin 11 10d
ID ,rm s =
.
4n
3

The switching losses of the primary- and secondary-side

switches are given by

Pout
Vin Iin Ploss
=
.
Pin
Vin Iin

(39)

These equations are derived on the condition that the antiparallel diode conduction time is quite short and negligible with
the intention to ensure ZCS of primary switches without significant increase in peak current of the switches. However, at light
load, the body diode conduction time is comparatively large and
(18) is not valid any more. Due to extended body diode conduction, the output voltage is boosted to higher value than the
nominal boost converter. Equation (18) is modified to
Vo =

2n Vin
(1 d d )

(40)

XUEWEI AND RATHORE: NOVEL INTERLEAVED BIDIRECTIONAL SNUBBERLESS SOFT-SWITCHING

5541

where d is given by
d = d 0.5

4 n Iin Llk fs
.
Vo

(41)

From (41), it can be observed that for a given value of Llk

and Vo , d increases as the load is decreased.
Table I gives a comparison of four bidirectional isolated converter topologies including the current-fed dual half-bridge converter [9], the voltage-fed dual active fullbridge converter [12],
the current-fed dual active bridge with active-clamped converter [16], and the proposed converter (single cell) in terms
of the number of components, voltage and current stress, softswitching range, etc., for the same design specification. The input current ripple of voltage-fed converters [12] is much higher
than that of current-fed topologies; thus, a large input filter is
required. Though the current-fed dual half-bridge topology [9]
has lesser number of active components, the total device rating
of primary switches is very high with current carrying capacity
of up to three times the battery current. Another drawback of
this topology is that four split capacitors are required. These
four split dc capacitors have to handle full-load current, which
occupy a considerable volume of the converter. A current-fed
dual active bridge with active-clamped topology [16] suffers
from disadvantages such as the high number of switches, high
current stress, and high circulating current at light load. The proposed converter applies a novel modulation technique to clamp
the primary devices voltage and achieve soft-switching. Softswitching and voltage-clamping is inherent and is achieved at
variation in load and input voltage.
IV. SIMULATION AND EXPERIMENTAL RESULTS
The proposed converter has been simulated using software
package PSIM 9.0.4 and later a prototype rated at 500-W was
developed and tested in research lab to verify the steady-state
analysis and simulation results. The specifications of the converter are input voltage Vin = 12 V, nominal output voltage
Vo = 300 V, output power Po = 500 W, and device switching
frequency fs = 100 kHz. Simulation results are illustrated in
Figs. 6 and 7, which coincide closely with theoretical operating
waveforms shown in Fig. 4.
Simulation waveforms of input boost inductor currents I(L1 ),
I(L2 ), input current Iin , series inductor currents I(LL lk 1 ) and
I(LL lk 2 ) are shown in Fig. 6. The ripple frequency of input
boost inductor currents is 2x device switching frequency. Currents I(L1 ) and I(L2 ) are phase shifted with each other by
nearly 180 . Thus, the input current Iin is of considerably low
current ripple because of ripple cancellation of I(L1 ) and I(L2 ).
The ripple frequency of Iin is 4x device of switching frequency,
which reduces the requirements of input capacitor Cin . Fig. 6(b)
clearly shows that voltages across output capacitors of each cell
(Co1 and Co2 , Co3 and Co4 ) are phase shifted with each other
by 180 . Voltage across Co1 of CELL 1 is phase shifted by
90 with Co3 of CELL 2. Cancellation effect results in much
lower output ripple magnitude, which alleviate output filter requirement. The peak currents through series inductors LL lk 1

Fig. 6. Simulation waveforms: (a) input boost inductor currents I(L 1 ), I(L 2 ),
input current Iin , series inductor currents I(L L l k 1 ) and I(L L l k 2 ), (b) voltages
across output capacitors V C o 1 , V C o 2 , V C o 3 , V C o 4 and output voltage V O , (c)
voltage waveforms V (L L l k 1 ), V (L L l k 2 ), and (d) voltage waveforms V A B
and V C D .

and LL lk 2 above the constant value are caused by the extended

conduction of body diodes of corresponding primary switches
ensuring their ZCS turn-off. As shown by the voltage waveforms VA B and VC D in Fig. 6(d), the voltages across the primary switches, which are equal to VA B or VC D , are naturally
clamped at low voltage, i.e., Vo /4n.

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TABLE I
COMPARISON OF FOUR BIDIRECTIONAL ISOLATED CONVERTER TOPOLOGIES AT V in = 12 V AND FULL LOAD (1 kW)

Fig. 8.

Laboratory prototype.

TABLE II
MAJOR COMPONENTS PARAMETERS OF THE EXPERIMENTAL PROTOTYPE

Fig. 7. Simulation waveforms. (a) Primary-switch currents I(S 1 ), I(S 2 ),

I(S 5 ), and I(S 6 ). (b) Secondary-switch currents I(S 9 ), I(S 1 0 ), I(S 1 1 ), and
I(S 1 2 ).

Fig. 7 shows simulation waveforms of currents through primary switches I(S1 ), I(S2 ), I(S5 ), and I(S6 ) and secondary
switches I(S9 ), I(S10 ), I(S11 ), and I(S12 ). The negative parts
of these waveforms correspond to currents flowing through their
respective body diodes. ZCS of primary switches are clearly illustrated. I(S1 ), I(S2 ), I(S5 ), and I(S6 ) naturally decrease to
zero owing to secondary-side modulation and then corresponding anti-parallel body diodes conduct before gating signals are
removed which ensures ZCS turn-off of the primary switches.
As shown in current waveforms I(S9 ), I(S10 ), I(S11 ), and
I(S12 ) in Fig. 7(b), the body diodes of switches conduct before
the devices start conducting, confirming ZVS of the secondary-

side switches. The phase relationships between switches pairs

of both cells are also obviously demonstrated by Figs. 6 and 7.
A laboratory prototype of the proposed converter rated at
500 W, as shown in Fig. 8, has been developed and tested to
demonstrate its performance. Details of the experimental converter are given in Table II. Gating signals for the switches
have been generated using Xilinx Spartan-3 field-programmable
gate array board. Two IR2181 are used to drive primary-side

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5543

Fig. 9. Gating signals of all the switching devices for output power of 500 W at
300 V. (a) Primary-side switches. (b) Secondary-side switches (x-axis: 2 s/div,
y-axis: 10 V/div).

MOSFETs and one IR21814 is used to drive secondary-side

MOSFETs. Gating signals are illustrated in Fig. 9. These gating
signals of two switch pairs of each cell are phase shifted with
each other by 180 and two cells are shifted by 90 .
Experimental results are shown in Figs. 1013 that match
closely with theoretical predicted waveforms and simulation
waveforms. It can be obviously observed that ZCS of primary
switches and ZVS of secondary switches at both full load (see
Fig. 10) and at partial load (see Fig. 11) are achieved. In waveforms shown in Figs. 10(a) and (b) and 11(a) and (b), the gating
signal of primary switch Vgs is first removed before the switch
voltage Vds starts rising. The clear gap between these two waveforms corresponds to the conduction of the anti-parallel body
diode of the respective switch. Due to secondary modulation,
the switch current naturally falls to zero and then becomes negative because of the conduction of the body diode, confirming
the ZCS turn-off of the primary switches.
Figs. 10(c) and (d) and 11(c) and (d) clearly show the ZVS
turn-on of the secondary switches. Gating signal Vgs is applied to
the secondary switch when switch voltage Vds is zero. Besides,
its body diode conducts prior to its switchs conduction, which
verifies ZVS of secondary devices. Figs. 10(a) and (b) and 11(a)
and (b) show that the voltage across the primary devices is
clamped at a rather low voltage that enables the use of low
voltage rating devices to reduce conduction loss. Therefore,
the proposed modulation method obtains soft-switching of all
devices and clamped device voltage without additional activeclamping or passive snubbers circuits.
Additionally, the turn-on procedure of primary switches is
also demonstrated in waveforms shown in Figs. 10(a) and (b) and

Fig. 10. Experimental results for output power of 500 W at 300 V (x-axis:
2 s/div). (a) and (b) Gate-to-source voltage V g s (10 V/div) and drain-to-source
voltage V d s (50 V/div) across the primary-side MOSFETs and currents through
them (20 A/div). (c) and (d) Gate-to-source voltage V g s (10 V/div) and drainto-source voltage V d s (200 V/div) across the secondary-side MOSFETs and
currents through them (20 A/div).

11(a) and (b). Before turning ON, the voltage across the primary
switch is clamped at Vo /4n = 30 V. When the switch is gated
ON, the current through it is rising at a slope of di/dt = 7.5 A/s
from zero. With this limited di/dt through the primary switch and
low-clamped voltage across it, the turn-on loss (due to overlap of
switch voltage and current during switching transition time) is
low. Considering ZCS turn-off of the primary switches and ZVS
turn-on switching transition loss of the secondary-side switches
mentioned previously, the total switching losses are reduced
enormously. In addition, primary switches of low voltage rating

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IEEE TRANSACTIONS ON POWER ELECTRONICS, VOL. 28, NO. 12, DECEMBER 2013

Fig. 11. Experimental results for output power of 250 W at 300 V (x-axis:
2 s/div). (a) and (b) Gate-to-source voltage V g s (10 V/div) and drain-to-source
voltage V d s (50 V/div) across the primary-side MOSFETs and currents through
them (20 A/div). (c) and (d) Gate-to-source voltage V g s (10 V/div) and drainto-source voltage V d s (200 V/div) across the secondary-side MOSFETs and
currents through them (20 A/div).

(60 V) with low on-state resistance can be used resulting in

lower conduction loss and higher efficiency.
Fig. 12(a) shows waveforms of voltage across the HF transformers and current through the primary windings of both cells.
The HF bipolar voltage is clamped at a low voltage without
ringing and spikes due to zero-current commutation. Currents
through the primary windings iL lk 1 and iL lk 2 are continuous
unlike traditional hard-switching and active-clamped converters. Current through primary- and secondary-side devices of
both cells are illustrated in Fig. 12(b) and (c) and are in good
agreement with theoretical operating waveforms and simulation
results. It can be clearly observed that S1 and S2 of Cell 1 (S5
and S6 of Cell 2) are phase shifted by 180 . S1 of Cell 1 is phase
shifted by 90 with S5 of Cell 2. Similar phase shift relation-

Fig. 12. Experimental results for output power of 500 W at 300 V (x-axis:
2 s/div). (a) Voltage across the HF transformer v A B and v C D (50 V/div)
and currents through the primary windings iL l k 1 and iL l k 2 (50 A/div). (b)
Currents through the primary-side MOSFETs (20 A/div). (c) Currents through
the secondary-side MOSFETs (20 A/div).

ship holds true for the corresponding secondary-side switches.

These current waveforms also clearly demonstrate ZCS of primary switches and ZVS of secondary switches of both cells.
Input boost inductor currents i(L1 ), i(L2 ) with 2x device
switching frequency and input current iin with 4x device switching frequency are shown in Fig. 13(a) and keenly aligns with
simulation waveforms of Fig. 6(a). The phase shift between
i(L1 ) and i(L2 ) is close to 180 . The ripple magnitudes are
around 2 A because the values of input boost inductors used
in prototype are smaller than designed values. But ripple cancellation effect results in much smaller ripple in input current.
The ratio of iin / iin is around 1.3%. High-input-current ripple
frequency and low-ripple magnitude reduce the size of the input
capacitor and improve the utilization and lifetime of battery.
The voltage across output capacitors Co1 and Co2 and the
total voltage across them are displayed in Fig. 13. It can be
seen that voltages across Co1 and Co2 are equal and balanced,

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5545

primary-side devices naturally with zero-current commutation

and therefore eliminates the necessity for active clamp or passive snubbers required to absorb device turn-off voltage spike
in conventional current-fed topologies. An interleaved design is
adopted to increase the power handling capacity. Lower input
current ripple, reduction of passive components size, reduced
device voltage and current ratings, better thermal distribution
are obtained. Usage of low-voltage devices and current sharing
between interleaved cells results in low conduction losses in primary devices, which is significant due to higher currents on the
primary side. Detailed steady-state operation, analysis, and design have been illustrated. Simulation and experimental results
clearly confirm and demonstrate the claimed soft-switching of
all semiconductor devices, natural clamping, and zero-current
commutation of primary-side devices. These merits make the
converter promising for FCV application, front-end dc/dc power
conversion for fuel-cell inverters and ESS.
REFERENCES

Fig. 13. Experimental results for output power of 500 W at 300 V (x-axis:
2 s/div): (a) Boost inductor current waveforms iL 1 , iL 2 and input current iin
(2 A/div, 5 s/div). (b) Voltages across output capacitors of CELL 1 (50 V/div,
2 s/div). (c) Scaled voltages across output capacitors of CELL 1 (10 V/div,
5 s/div).

which indicates that the proposed topology and modulation does

not bring unbalance problems. Some minor parasitic ringing
is noticed due to stray inductances of wiring connections and
parasitic capacitances in printed circuit board. As shown in
Fig. 13(c), voltages across output capacitors Co1 and Co2 are
phase shifted with each other by 180 . The output voltage ripple
is reduced due to ripple cancellation effect.
As shown in Figs. 10 and 11, the peak current through the
primary switch and transformer is higher than the input current to ensure ZCS of primary devices. Though the difference
between them increases with reduction in load, the rms value
of current through the primary switch and transformer is proportional to the output power. Thus, the conduction losses in
primary switches decrease as usual at low output power unlike
voltage-fed resonant converters. For the experimental prototype,
a rated efficiency of 93% is obtained.
V. CONCLUSION
A novel interleaved soft-switching bidirectional current-fed
full-bridge isolated voltage doubler is proposed for FCVs application. The proposed converter maintains ZCS turn-off of primary devices and ZVS turn-on of secondary devices throughout
the wide variation of output power. Turn-on loss of primary devices is also shown to be low. Hence, maintaining soft-switching
of all devices substantially reduces the switching loss and allows higher switching frequency operation of the converter to
achieve a more compact and higher power density system. The
proposed modulation technique clamps the voltage across the

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Pan Xuewei (S12) received the B.E. degree in electronic engineering from the University of Electronic
Science and Technology of China, Chengdu, China,
in 2011. He is currently working toward the Ph.D.
degree in power electronics in the Department of
Electrical and Computer Engineering, National University of Singapore, Singapore.
His research interests include soft-switching methods and modulation techniques for high-frequency
power conversion for renewable energy.

Akshay K. Rathore (M05SM12) received the

B.E. degree in electrical engineering from the Maharana Pratap University of Agriculture and Technology, Udaipur, India, in 2001, the M.Tech. degree
in electrical machines and drives from the Indian
Institute of Technology, Banaras Hindu University,
Varanasi, India, in 2003, and the Ph.D. degree in
power electronics from the University of Victoria,
BC, Canada, in 2008.
From February 2003 to August 2004, he was a
Lecturer in the College of Technology and Engineering, Udaipur and Mody Institute of Technology and Science, Lakshmangarh,
India. From May to December 2007, he was a Sessional Lecturer in the Department of Electrical and Computer Engineering, University of Victoria, BC,
Canada. From September 2008 to August 2009, he was a Postdoctoral Research Fellow in Electrical Machines and Drives Lab, University of Wuppertal,
Wuppertal, Germany. From September 2009 to September 2010, he was a Postdoctoral Research Associate at the University of Illinois, Chicago, USA. Since
November 2010, he has been an Assistant Professor in electrical and computer
engineering at the National University of Singapore, Singapore. He has contributed to nearly 60 research papers and delivered three tutorials on current-fed
high-frequency soft-switching converters. His research interests include softswitching techniques, high-frequency power conversion for distribution generation and renewable energy sources (fuel cells and photovoltaic), current-fed
topologies, modulation techniques, electric- and fuel-cell vehicles, energy storage, and high-performance control of motor drives and power converters.
Dr. Rathore was a recipient of Thouvennelle Graduate Scholarship and the
University of Victoria full Ph.D. Fellowship during his Ph.D. He received the
Gold Medal for achieving highest academic standing among all electrical engineering specialization during his M.Tech. He is an Associate Editor of the
IEEE TRANSACTIONS ON INDUSTRY APPLICATIONS, a Guest Associate Editor
for special issue on transportation electrification and vehicle systems in the
IEEE TRANSACTION ON POWER ELECTRONICS, and an Associate Editor of the
International Journal of Power Electronics. He has been a Track Chair for the
IEEE Industrial Electronics Conference (IECON), Montreal, Canada, in 2012,
IECON, Vienna, Austria, in 2013, and the IEEE Power Electronics and Drive
Systems (PEDS), Kitakyushu, Japan, in 2013. He was a Tutorial Chair for PEDS
2011. He has been listed in Marquis Whos Who in Science and Engineering in
2006, Whos Who in the World, and Whos Who in America in 2008. He is a
reviewer of the IEEE Transactions, the Institute of Engineering and Technology,
and Elsevier journals.