R Anilkumar

Studies on Solar Cell AC Parameters
(Instrumentation, Measurements and Applications)
A Thesis
Submitted for the Degree of
Doctor of Philosophy
in the Faculty of Engineering
by
R Anil Kumar
Department of Instrumentation
Indian Institute of Science

Bangalore- 560 012, India
March 2004
Acknowledgements
I am highly indebted to Prof. J. Nagaraju, Department of Instrumentation, Indian Institute of
Science and Dr. M.S. Suresh, Head Battery Division, ISRO Satellite Centre, for their inspiring
guidance and stimulating encouragement throughout the course of this research work. I express my
deep sense of gratitude towards them for introducing me to this research work and for their keen
interest and persisting encouragement.
I take this opportunity to thank Dr. K. Kasturirangan, Dr. Madhavan Nair, Dr. P. S. Goel,
Prof. A. V. Pataki, Shri. B. N. Baliga, and Dr. N. K. Misra, ISRO Satellite Centre, and Dr. M.M.
Nayak, LPSC, ISRO, for encouraging me to carry out this research work.
I thank Prof. R.M. Vasu, Prof. M.V. Krishna Murthy, and Prof. S. Mohan, IISc, Indian
Institute of Science, for their keen interest on the research work.
I thank Prof. S.B. Krupanidhi, MRC, IISc for providing timely advices and helping time to
time throughout this research works.
I thank Ministry of Non-conventional Energy Research (MNES), New Delhi, for providing
the project to Dr. J Nagaraju, IISc, for developing the Solar Cell Impedance Analyzer.
I thank Dr. Gunashekar, Dr. S. Rameshu, Dr. Gopakumar, Dr. Umanand and Shri. Krishna
Kumar, CEDT, IISc for providing necessary suggestions during the course of the research work.
I wish to record my thanks to my colleagues at Solar Panel Division, Thermovac & Climatic
Test Facility, UHV lab, Shock & Vibration lab, Battery Division, Indigenisation & Components
Group, Drafting & Technical Documentation Facility, Library & Documentation Division, Engineering
Maintenance Division and Administration, ISRO Satellite Centre, for providing necessary support
and for their valuable suggestions.
I thank my colleagues Shri. M. Balasubramani, Shri. Prashant Misra, Shri. Makarand
Deshmukh, Shri. Dhananjay Kekuda, and Shri Balakrishnamraju, Department of Instrumentation,
Indian Institute of Science, for there valuable help at many points of time.
I thank Shri B. L. Agrawal, Shri. N. Srinivasa Murthy, Dr. Anil Agrawal, Shri. Devi Prasad
Karnik, Shri, J. N. Hemanta Kumar and Shri A. Ramachandra, ISRO Satellite Centre, for providing
necessary facilities, support and technical help to perform this research work.
Special thanks to Dr. H. Anantha Krishna, my colleague at Cryogenic Test Facility, who is a
source of inspiration and provided timely support with necessary suggestion throughout my
academic and professional career.
I thank Dr. H. Bhojaraj and Dr. K Kanaka Rao for providing necessary timely help and
support. I thank Dr Chandramouli and Shri M.G. Sandeep for their timely help and support.
I owe my respected thanks to my parents Shri. K. Ramaseshasastry and Smt. R. Shashi,

who are the source of inspiration to carry out this degree, for their keen interest and
encouragement through out my life and career. I thank my in-laws Shri Krishna Murthy and Smt.
Susheela, for encouraging me to carry out my research.
The special thanks to my life partner Smt. K. Indu Prathima for sparing her valuable time in
providing encouragement, day to day support and efforts for completing this degree with due
patience and co-operation through out my research work. Thanks to Master A. Ashwin who added
lot of enthusiasm to carry out and complete this research work.
I thank my brother-in-law Shri. K.S. Manjunath, who supported me to make this thesis, and
my sister Smt. R. Savitha and my niece Kum. M. Padamashree and nephew Master Vinay. Thanks
to Shri. K. Praveen, Smt. Kripa and Shri. K. Vinay Vasant.
I thank family members of Dr. M. S. Suresh and Dr. J. Nagaraju for their co-operation and
support.
My hearty thanks to all my colleagues and friends who have contributed in bringing this
work to present shape.
R Anil Kumar
CONTENTS
Page numbers
Abstract
Nomenclature
List of Publications
List of Figures
List of Tables
Chapter 1: INTRODUCTION
1.1
Photovoltaics
1.2
Solar cell
1.2.1
Structural details of solar cell
1.2.2
Static (DC) characteristics of a solar cell
1.2.2.1 Series resistance
1.2.2.2 Shunt resistance
1.2.2.3 Parameters affecting solar cell static (DC) characteristic
1.2.2.3.1
Effect of solar radiation intensity
1.2.2.3.2
Effect of temperature
1.2.3 Dynamic (AC) characteristics of a solar cell
1.2.3.1
Solar cell capacitance
1.2.3.1.1 Transition capacitance
1.2.3.1.2 Diffusion capacitance (Cd)
1.2.3.1.3 Bulk capacitance
1.2.3.1.4 Metal-Semiconductor junction capacitance
1.2.3.2
Solar cell dynamic resistance (Rd)
1.3
Importance of solar cell AC parameters
1.4
Measurement techniques
1.4.1 Frequency domain (Impedance spectroscopy)
1.4.1.1 Principle
1.4.1.2 Impedance spectrum of passive components and networks
1.4.2 Time domain technique (Charge accumulation measurement)
1.4.2.1 Principle
1
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Chapter 2: LITERATURE OVERVIEW

2.1
Measurement Techniques
2.1.1 Time domain
2.1.2 Frequency domain
2.2
Measurements on solar cell
2.3
Impedance measuring instruments
2.4
Applications of solar cell
2.5
Conclusions
2.6
Scope and objectives of the present investigations
2.7
Thesis presentation
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Chapter 3
INSTRUMENTATION
3.1
Experimental set-up
3.1.1 Electro-Chemical Interface (ECI)
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Page numbers
3.1.2 Frequency Response Analyzer (FRA)
3.1.3 Noise reduction
3.1.4 Calibration of the Experimental Set-up
3.1.5 Limitations of the measurement setup
3.2 Solar Cell Impedance Analyzer
3.2.1 Design requirements
3.2.2 Description of the Instrument
3.2.2.1 Arbitrary function generator card (NI5401)
3.2.2.2 Power amplifier with control circuit (custom built)
3.2.2.3 High-speed data acquisition card (NI5112)
3.2.2.4 Testing of hardware
3.2.3 Software
3.2.4 Techniques employed to reduce noise and errors
3.2.5 Software range extender and Internal calibration
3.2.6 Calibration of solar cell impedance analyzer
3.2.7 Repeatability
3.2.8 Summary
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Chapter 4: MEASUREMENTS
4.1
Solar Cell Measurements under dark and illumination
4.1.1 Experimentation
4.1.2 Results and Discussion
4.1.3 Summary on illumination and dark measurements
4.2
Measurements on Different Types of Solar Cells
4.2.1 Experimentation
4.2.2 Measurement on GaAs/Ge Solar Cell
4.2.2.1 AC Parameters at Room Temperature (298K)
4.2.2.1.1
Cell Capacitance (Cp)
4.2.2.1.2
Cell Parallel Resistance (Rp)
4.2.2.1.3
Cell Series Resistance (r)
and Cell Inductance (L)
4.2.2.2 AC Parameters at Different Temperatures
4.2.2.2.1
Cell Capacitance
4.2.2.2.2
Cell Resistance
4.2.2.2.3
Diode Factor and Parallel Resistance at Vmp
4.2.2.3 Summary
4.2.3 Measurements on Silicon BSFR Solar Cell
4.2.3.1 AC Parameters At Room Temperature (298K)
4.2.3.1.1
4.2.3.1.2
Cell Resistance (Rp)
4.2.3.1.3
Cell Series Resistance (r) and
Cell Inductance (L)
4.2.3.1.4
Deviation of Impedance Spectrum
4.2.3.2.1
Cell Capacitance
4.2.3.2.2
Cell Resistance
4.2.3.2.3
Mean Carrier Lifetime
4.2.3.3
Summary
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Page numbers
4.2.4
Comparison of AC Parameters between GaAs/Ge and Silicon

BSFR Solar Cells
4.2.5 Measurements on Silicon Solar Cell
4.2.5.1 Summary
4.2.6 Charge Accumulation Measurement
4.2.6.1 Experimentation
4.2.6.2 Calibration of experimental set-up
4.2.6.3 Results and Discussion
4.2.6.4 Summary
Chapter 5
APPLICATIONS OF SOLAR CELL AC PARAMETERS
5.1
Scaling of Single Cell Capacitance to Array Capacitance
5.2
Effect of Solar Array Capacitance on the Performance
of Switching Shunt Voltage Regulator
5.2.1 Ripple Voltage at the Output Due to Solar Cell Capacitance
5.2.1.1 Steady State Analysis
5.2.1.4 Design Considerations
5.2.2 current peaking
5.3.3 Power Loss in Shunt Switch
5.3.3.1 Power loss due to energy stored in
the capacitance of the solar array
5.3.3.2 Power loss due ON resistance of the shunt switch
5.3.3.2 Power loss due to Turn ON and OFF time of the
shunt switch
5.3.3.4 Power loss estimation
5.3.3.5 Comparison of power loss in shunt
switch with silicon and GaAs/Ge solar cell arrays
5.3
Effect of cell parallel resistance on design
and performance of shunt switching voltage regulator.
5.4.1 Importance and need of cell parallel resistance (Rp)
5.4
Summary
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Chapter 6
CONCLUDING REMARKS
6.1
Instrumentation
6.2
Measurements
6.3
Applications
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References
Appendix 1
Appendix 2
Appendix 3
Appendix 4
Appendix 5
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283
Abstract
Photovoltaic (PV) conversion of solar energy appears to be one of the most
promising ways of meeting the increasing energy demand. In space, photovoltaic power
source is the only safe alternative. Conventional silicon solar cell technologies have seen
several improvements and off late GaAs/Ge and multijunction solar cells are developed to
improve conversion efficiency. Demand for higher power, smaller size, lesser weight and
higher efficiency has necessitated the use of high frequency switching power
conditioners, which requires a better understanding of the AC characteristics of the solar
cell, especially its capacitance. Solar cell is large p-n junction diode, whose AC
parameters (capacitance and resistance) varies nonlinearly with its operating voltage,
temperature and depend on the method (frequency or time domain) of measurement.
Hence, studies on AC parameters of solar cells is taken up involving development of
instrumentation, measurements on various types of solar cells and applications of AC
parameters on switching shunt regulators.
In the present research work a measurement set-up to measure the solar cell AC
parameters using impedance spectroscopy technique is established first with the
commercial instruments. Here a small AC voltage (<VT) is applied about the operating
voltage (DC bias) and its complex impedance is measured from the resultant current over
a wide range of frequencies. Cell capacitance, parallel resistance, series resistance and
inductance are estimated from the impedance spectrum, which is plot of the cell
impedance in a complex plane. The principle of measurement, details of measurement
set-up with calibration, testing and limitations observed when applied to solar cells, are
presented. To over come the limitations in the measurement set-up, a dedicated userfriendly instrument called Solar Cell Impedance Analyser is developed to measure solar
cell AC parameters. It is a personal computer based virtual instrument, which has a power
amplifier, a high-speed data acquisition card and an arbitrary function generator card with
a custom built micro controller based hardware with an application specific software
developed using graphical programming language. A novel concept of software range
extender is introduced, which virtually increases the dynamic range of the power
amplifier.
The AC parameters of the GaAs/Ge solar cell are measured both under
illumination (AM0) and dark at 298 K (room temperature) using impedance spectroscopy.
The errors are more in illuminated data when compared to dark data. Hence all further
measurements are made in dark condition and a procedure is suggested to extrapolate the
dark data to illumination. The AC parameters of GaAs/Ge and silicon solar cells are
measured at different bias voltages and cell temperatures ranging from 198K to 348K,
where as measurements on silicon terrestrial solar are made at 298K. Capacitance,
parallel resistance, series resistance and inductance of solar cell are estimated from this
data. It is observed that (i) GaAs/Ge shows mainly transition capacitance throughout its
operating range while silicon solar cells exhibit both transition and diffusion capacitances.
(ii) The cell capacitance increases with temperature at all bias voltages, where as its
resistance decreases with temperature. (iii) At maximum power point, GaAs/Ge solar cell
capacitance is constant at all temperatures, whereas BSFR silicon solar cell capacitance
increases with temperature. (iv) The GaAs/Ge solar cell resistance and diode factor at
maximum power voltage decreases with temperature, whereas the BSFR silicon solar cell
resistance peaks at 245K.
Since the solar cell arrays are used in photovoltaic power generating system, an
analysis is presented to scale up the single cell capacitance to array capacitance. The
deviation observed between the arrays capacitance derived from a single cell data and the
actual array capacitance is in the range of 7.5% to 35% depending on the dispersion in
cell short circuit currents and I-V characteristics of solar cells used in the panel.
The present study has identified that the charge equivalent and energy equivalent
capacitances are to be used in the design of shunt switching regulator and a technique to
measure this charge equivalent capacitance directly in time domain is developed. It is
shown that solar cell capacitance affects the switching regulator performance by
increasing the output ripple, increasing the power loss in the shunt switch and its peak
current. Extra ripple due to array capacitance is calculated and its effect with switching
frequency is studied. An experimental switching regulator is designed to confirm the
theoretical considerations. It is observed that the output voltage ripple in a switching
regulator increases with solar cell array capacitance and which dominates above
frequency fo = (Cqa RL)-1, where Cqa is array charge equivalent capacitance and RL is load
resistance. This additional power loss in the shunt switch due to charge stored in the solar
array is estimated, which is found to increase with switching frequency dominating the
total power loss in the shunt switch. The array capacitance limits the switching frequency
of the shunt regulator. The peak current in the shunt switch can be reduced with a large
turn ON time, which in turn increases the power loss in the shunt switch.
Nomenclature
Alphabets
A
Ampere
Ac
Area of cross-section in m2 of solar cell
Constant
Capacitor
Cpa
Solar array / panel capacitance (Cp)
CB
Bulk capacitance between front and back contacts
CBus
Bus capacitor
Cd
Diode diffusion capacitance of solar cell
Ce
Energy equivalent capacitance of solar cell
Cea
Solar array / panel Energy equivalent capacitance
Cms
Metal-semiconductor junction capacitance
CP
Solar cell parallel capacitance
Cq
Charge equivalent capacitance
Cqa
Solar array / Panel Charge equivalent capacitance
Ct
Diode transition capacitance
Dc
Diffusion coefficient
dV/dt
Rate of change of voltage
Eac
Energy stored in solar cell capacitance
Ec
Conduction Energy level
Eg
Band gap energy
En
Energy
EON
Energy dissipated in the shunt switch during Turn ON
EOFF
Energy dissipated in the shunt switch during Turn OFF
Ev
Valance energy level
frequency of measurement
Farad
fs
Switching frequency of voltage regulator
Solar cell dynamic conductance
i(t)
instantaneous current
Current
Id
Diode current
IL
Load current
Imaginary (Z) Imaginary part of impedance

Im
Maximum current
Imp
Current at maximum power point
Io
Diode reverse saturation current
Ip
Peak current
Ip(min)
Minimum Peak current
Ip(Max)
Maximum Peak current
Iph
Photon generated current
Ipp
Peak-to peak current
IS
Impedance Spectroscopy
Irms
Root mean square current
ISC
Short circuit current
Complex quantity (SQRT (-1))
Boltzmans constant = 8.617 x 10-5 eV/K.
Inductor
Ls
Diffusion length
milli
NA
Doping concentration in p region
ND
Doping concentration in n region
Ni
Intrinsic concentration of electrons & holes for the base semiconductor
Pa
Average power loss in shunt switch due to array capacitance
Pmax
Maximum power
Pmp
Maximum power point
Pi
Incident solar radiation power
PT
Total average power loss in the shunt switch
PTON
Average power loss due to turn ON time in shunt switch
PTOFF
Average power loss due to turn OFF time in shunt switch
Prd
Average power loss due to ON resistance of shunt switch
Electron charge
Charge
Qo
Total charge stored in solar cell
Bulk / Series resistance
Resistance
Rbn
Bulk resistance of the n type region
Rbp
Bulk resistance of the p type region
RC
Equivalent series resistance of capacitor
Rcn
Contact resistance between metal and n type semiconductor
Rcp
Contact resistance between metal and p type semiconductor
Rd
Diode dynamic resistance of solar cell
RdsON
ON resistance of MOSFET
Real (Z)
Real part of impedance
RL
Load current
Rp
Parallel resistance RT || Rd
Rs
Series equivalent resistance of RP||XP
Rsen
Sense resistor
Rt
Shunt resistance of solar cell
Surface recombination velocity
Time
Temperature
TOFF
OFF time
TON
ON time
Tp
Time period
Voltage
v(t)
Instantaneous voltage
Va
Array voltage
VB
Bus voltage
Vd
Cell voltage
Vg
Forward voltage drop across diode
Vjd
Solar cell diode voltage under dark
Vji
Solar cell diode voltage under illumination
Vo
Junction voltage / Built-in voltage
Vm
Maximum voltage
Vmp
Maximum power point voltage
Vpp
Peak to peak voltage
VOC
Open circuit voltage
Vref
Reference voltage
Vrms
Root mean square voltage
Vs
Voltage across solar array (VB+V)
VT
Thermal voltage
VTH
Threshold voltage
VTR
Ripple voltage
V1
Ripple voltage at the output
V2
Additional /Extra ripple due to solar array capacitance at output
Voltage across blocking diode
Watt
XP
Reactance of Cp
Xs
Series equivalent reactance of RP||XP
YB
Admittance function of shunt regulator
Impedance
|Z|
Magnitude of impedance
|Z ()|
Magnitude of Impedance as function of frequency
Greek Alphabets
o
Permittivity of free space, 8.85*10-12 F/m
Relative permittivity of semiconductor
Micro
Diode factor / Ideality factor
Solar cell efficiency
Phase angle
Mean Minority Carrier Lifetime
Angular frequency
Ohm
Planks constant
Abbreviations
AC
Alternating Current
AL
Aluminium
ARC
Anti reflection coating
AM0
Air Mass Zero
BSR
Back Surface Reflector
BSFR
CuInSe2
Back Surface Field Reflector

Copper Indium di-Selenium solar cell
Cu(ln,Ga)Se2 Copper Indium Gallium di-Selenium solar cell

D
Duty cycle
DC
Direct Current
ECI
Electro-Chemical Interface
EMI
Electro Magnetic Interference
FF
Fill factor
FRA
Frequency response analyzer
GaAs/Ge
Gallium Arsenide on Germanium solar cell
GEO
Geo-synchronous earth orbit
I-V
Current- Voltage (Static)
LEO
Low earth orbit
Mega
MPP
Maximum power point
MOSFET
Metal Oxide semiconductor field effecting transistor
nano
OCVD
Open Circuit Voltage Decay
pico
PC
Personal Computer
PV
Photovoltaic
PWM
Pulse Width Modulation
SCCD
Short circuit current decay
Publications
1. Anil Kumar R, M S Suresh, and J Nagaraju, Measurement and
Comparison of AC parameters of silicon (BSR and BSFR) and Gallium
Arsenide (GaAs/Ge) solar cell used in space application, Solar Energy
Materials and Solar Cells, Vol.60 (2000) pp.155-166.
2. Anil Kumar R, M S Suresh, and J Nagaraju, Facility to measure AC
parameters using an impedance spectroscopy techniques, Review of
Scientific Instruments, Vol. 72 (8), (2001), pp. 3422-3426
3. Anil Kumar R, M S Suresh, and J Nagaraju, Measurement of AC
Parameters of Gallium Arsenide (GaAs/Ge) solar
cell by impedance
spectroscopy, IEEE Trans. Electron Design. 48 (9) (2001), pp. 21772179.

4. Anil Kumar R, M S Suresh, and J Nagaraju, GaAs/Ge
solar cell AC
parameters at different temperatures, Solar Energy Materials and Solar

Cell, Vol.77 (2003) pp.145-153
5. Anil Kumar R, M S Suresh, and J Nagaraju, Time domain technique to
measure solar cell capacitance, Review of Scientific Instruments, Vol.
74 (7), (2003), pp. 3516-3518
6. Anil Kumar R, M S Suresh, and J Nagaraju, GaAs/Ge solar cell AC
parameters under illumination, Solar Energy Journal, Vol. 76 (2004), pp.
417 - 421
7. Anil Kumar R, M S Suresh, and J Nagaraju, Effect of solar array
capacitance on design performance of shunt switching voltage regulator,
IEEE Transactions on Power Electronics (submitted)
8. Anil Kumar R, M S Suresh, and J Nagaraju, Silicon (BSFR) solar cell ac

parameters at different temperatures, Solar Energy Materials and Solar
Cell, (Submitted)
9. Anil Kumar R, M S Suresh, and J Nagaraju, Virtual Impedance Analyser
to measure solar cell AC parameters, Review of Scientific Instruments,
(Submitted).
10. Anil Kumar R, M S Suresh, and J Nagaraju, Estimation of power losses
in Shunt Switch due to solar array capacitance, Solar Energy Journal,
(Submitted).
LIST OF FIGURES
Chapter 1
Figure 1.1: Schematic of a stand-alone photovoltaic power system.
Figure 1.2: Typical construction of a p-n junction solar cell
Figure 1.3: Energy band diagram of a p-n junction solar cell under illumination
Figure 1.4: Ideal equivalent circuit of a solar cell
Figure 1.5: Dark I-V characteristics of solar cell
Figure 1.6: I-V characteristics of illuminated solar cell
Figure 1.7: Structural details of different solar cells
Figure 1.8: Static or DC equivalent circuit of a solar cell
Figure 1.9: Parameters affecting solar cell static characteristics
Figure 1.10: Dynamic or AC equivalent circuit of a solar cell.
Figure-1.11: 'I-V' characteristics of a solar cell measured using LAPSS
Figure 1.12: Small signal measurement at a operating point
Figure 1.13: Impedance spectrum of passive components
Figure 1.14: Impedance spectra of series passive networks
Figure 1.15: Impedance spectra of parallel passive networks
Figure 1.16: Impedance spectrum of a network consisting of capacitor and resistor in parallel
Figure 1.17: Impedance spectrum of a R-C-r network
Figure 1.18: Typical Impedance spectrum of a network with two parallel RC and a series resistor (r)
Chapter 3
Figure 3.1: Schematic of experimental set-up
Figure 3.2: Block diagram of ECI
Figure 3.3: Block diagram of FRA
Figure 3.4: Solartron calibration network
Figure 3.5: Impedance spectrum of Calibration setup
Figure 3.6: Block diagram of the solar cell impedance analyzer.
Figure 3.7: Circuit diagram of the power amplifier with control circuit
Figure 3.8 (a): Solar cell impedance analyzer
Figure 3.8 (b): Solar cell impedance analyzer in the measurement set-up
Figure 3.9: Photograph showing internal details of solar cell impedance analyzer
Figure 3.10: Block diagram of set-up to test hardware
Figure 3.11: Impedance of I non- inductive precision resistor measured at different frequencies
Figure 3.12: Deviation from (1+j0) at different frequencies (response of amplifier)
Figure 3.15: Flow chart for login
Figure 3.13: Flow chart of Main module
Figure 3.14: Front panel of the instrument
Figure 3.16: Login GUI
Figure 3.17: Main control panel
Figure 3.18: Flow chart for Offline Process
Figure 3.19: Snap shot of the Offline GUI
Figure 3.20 (a): Flow diagram of Selecting the test specifications
Figure 3.20 (b): Flow chart for Defining test specifications
Figure 3.21: Snap shot of the Define test specifications
Figure 3.22: Flow diagram of Internal calibration
Figure 3.23: Internal calibration GUI
Figure 3.24: snap shot of the Save test GUI
Figure 3.25: Potentiostat to apply DC bias to DUT (GUI)
Figure 3.26: Flow diagram for Data acquisition and online plotting
Figure 3.27: GUI of the Frequency response analyzer (Warming up)
Figure 3.28: GUI of the Frequency response analyzer (Test under progress) with online display of
impedance spectrum
Figure 3.29: Part of Source code in graphical language (LABVIEW-6i) for Frequency Response analyzer
Figure 3.30: Typical data file saved after test
Figure 3.31: GUI of the Frequency response analyzer (Test under progress) with online display of bode
plot
Figure 3.32: Flow chart of RS232 communication and Help
Figure 3.33:Source code of Exit
Figure 3.34: Impedance Spectrum of software close loop test
Figure 3.35: Measured value of 1 over a wide range of frequency with internal calibration
Figure 3.36: Source code to calculate impedance from measured value
Figure 3.37: Source code to measure error in the internal calibration
Figure 3.38: Source code to eliminate error in actual measurement
Figure 3.39: Calibration network with precision resistor and capacitor in parallel
Figure 3.40: Impedance spectrum of network shown in Figure 3.39
Figure 3.41: Impedance spectrum of the network measured at different time
Chapter 4
Figure 4.1: Solar cell equivalent circuit
Figure 4.2: Schematic of the measure set-up used to measured solar cell AC parameters in illumination
Figure 4.3: Impedance spectra of GaAs/Ge solar cell at 299K in Illumination
Figure 4.4: Impedance spectra of GaAs/Ge solar cell at 299K in Dark
Figure 4.5: Variation of cell (GaAs/Ge) capacitance with cell terminal voltage in dark and illumination
Figure 4.6: Variation of cell capacitance with cell diode voltage in dark and illumination
Figure 4.7: Variation of cell resistance with different cell terminal voltage both in dark and illumination
Figure 4.8: Variation of cell resistance with cell diode voltage in dark and illumination
Figure 4.9: Comparison of cell capacitance measured in illumination and derived form dark data at
different cell voltage
Figure 4.10: Operating point of a cell in shadow
Figure 4.11: Set-up to measure solar cell AC parameters
Figure 4.12: Brass mounting block with solar cell and thermocouple
Figure 4.13: Impedance spectra of GaAs/Ge solar cell at different bias at 298K
Figure 4.15:Variation in cell capacitance with voltage at 248 K
Figure 4.16: 1/Cpm verses cell voltage of GaAs/Ge solar cell at 298 K
Figure 4.17: 1/Cp2 verses cell voltage of GaAs/Ge solar cell at 298 K
Figure 4.18: Variation in cell resistance with voltage at 248 K
Figure 4.19: Impedance spectra of GaAs/Ge solar cell at different bias at190K
Figure 4.24: Impedance spectra of GaAs/Ge solar cell at different bias at 348 K
Figure 4.31: Variation of solar cell capacitance with voltage at different temperatures
Figure 4.32: Variation of cell capacitance with voltage at different temperature
Figure 4.33: Capacitance of GaAs/Ge solar cell at Vmp for different temperatures
Figure 4.34: Cell resistance at different cell voltages and cell temperatures
Figure 4.35: Variation of diode factor and cell resistance with cell temperature at Vmp
Figure 4.36: Impedance spectra of Silicon (BSFR) solar cell at different reverse bias voltage at 298K
Figure 4.37: Impedance spectra of Silicon (BSFR) solar cell at different forward bias voltage at 298K
Figure 4.38: Cell capacitance verses cell voltage (Silicon BSFR solar cell) at 298 K
Figure 4.39: Variation of 1/Cpm at different cell voltages for BSFR silicon solar cells
Figure 4.40: Variation in cell resistance with different bias voltages
Figure 4.41: Impedance spectrum deviated from semicircle
Figure 4.42: Impedance spectra of Silicon (BSFR) solar cell at different bias voltages at 198K
Figure 4.53: Impedance spectra of Silicon (BSFR) solar cell at 0.5V and different temperatures
Figure 4.54: Silicon (BSFR) Cell capacitance at different temperatures
Figure 4.55: Cell capacitance verses cell voltage (Silicon BSFR solar cell)
Figure 4.56: Variation of diode factor with temperature
Figure 4.57: BSFR silicon cell capacitance at the maximum power point for different temperatures
Figure 4.58: Silicon (BSFR) cell parallel resistance at different temperatures
Figure 4.59: Variation of cell parallel resistance (Rp) with cell temperature at Vmp
Figure 4.60: Mean carrier lifetime verses cell temperature for silicon (BSFR) solar cell
Figure 4.61: Comparison of GaAs/Ge and Silicon BSFR solar cells capacitance
Figure 4.62: Comparison of GaAs/Ge and Silicon BSFR solar cells resistance
Figure 4.63: Impedance spectrum of Silicon (terrestrial) solar cell at 298K
Figure 4.64: Variation of Cell capacitance with cell voltage (terrestrial silicon solar cell)
Figure 4.65: Variation of cell resistance capacitance with cell voltage (Terrestrial silicon solar cell)
Figure 4.66:Charge-accumulation measurement set-up
Figure 4.67: Standard network for calibration
Figure 4.68: Variation in current with time for network 1 at different bias voltages
Figure 4.69 : Variation in current with time for network 2 at different bias voltages
Figure 4.70: Transient response of solar cell current at different bias voltages
Figure 4.71: Cell Capacitance at different cell voltage (GaAs/Ge)
Chapter 5
Figure 5.1: Solar cells connected in series
Figure 5.2: Static characteristics of silicon solar cell and array
Figure 5.3: Solar cells connected in parallel
Figure 5.4: Schematic of a fixed frequency PWM shunt switching voltage regulator
Figure 5.5: Typical Bus voltage ripple
Figure 5.6: Typical current through shunt switch S1 at the instant of its closure
Figure 5.7: Variation of cell capacitance, current and power as a function of cell voltage
Figure 5.8: (a) Equivalent circuit of shunt regulator, (b) switch status, (c) current through bus capacitor
and (d) output voltage ripple
Figure 5.9 (a): Shunt switch status, (b) Voltage across shunt switch, (c) Output voltage ripple with extra
ripple due to array capacitance
Figure 5.10: Extra ripple versus array voltage
Figure 5.11: Variation of array capacitance with array voltage
Figure 5.12: Measured ripple voltage at 0.122 A, 20 kHz
Figure 5.18: Measured extra ripple at load current of 0.6A and 20 kHz
Figure 5.19: Variation of extra ripple with load current
Figure 5.20: Variation of total ripple with load current
Figure 5.21: Measured voltage ripple at 20 kHz, 0.305A load current
Figure 5.25: Variation of extra ripple and total ripple with switching frequency
Figure 5.26: Variation of bus capacitance, ripple voltages with switching frequency (Theoretical estimate)
Figure 5.27 : Shunt switch current during turn-ON

Figure 5.32: Turn ON characteristics of MOSFET
Figure 5.33: Turn OFF characteristics of MOSFET
Figure 5.34: Power loss in the shunt switch at different switching frequencies
Figure 5.35: Power loss in shunt switch due to array capacitance
Figure 5.36: Equivalent circuit of solar array
Appendix 2
Figure A2.1: Parallel and series equivalent circuits
List of Tables
Chapter 3
Table 3.1: Setting of different parameters of FRA for measurement
Table 3.2: Impedance of calibration setup as a function of frequency
Table 3.3: Comparison of Actual and measured values of network components
Table 3.4: Measured Data for calibration network shown in Figure 3.38
Table 3.5: Comparison between actual measured values of network components
Chapter 4
Table 4.1: Static parameters of GaAs/Ge (20mm x 40mm) cell at 298K
Table 4.2: Measured cell capacitance and resistance at different bias voltages (both dark and illumination)
Table 4.3: AC parameters of GaAs/Ge solar cell at different cell bias voltages
Table 4.4: Cell Capacitance at different cell voltage and temperature
Table 4.5: Cell resistance at different cell voltage and temperature
Table 4.6: Static parameters of Silicon (BSFR) (20mm x 40mm) cell at 298K
Table 4.7: AC parameters of silicon (BSFR) at different cell bias voltages
Table 4.8: Silicon (BSFR) Cell capacitance at different cell voltage and temperature
Table 4.9: Cell dynamic resistance at different cell voltage and temperature
Table 4.10: Static parameters of Silicon terrestrial (100mm diameter) cell at 298 K
Table 4.11: Capacitance at different cell voltages for terrestrial silicon solar cell
Table 4.12: Resistance at different cell voltages for terrestrial silicon solar cell
Table 4.13: Comparison of measured and actual value of capacitor in network 1
Chapter 5
Table 5.1: Capacitance of silicon solar cell at different bias voltages
Chapter 1
INTRODUCTION
1.1
Photovoltaics
Power generation using photovoltaics (PV) has emerged as a very important non-
conventional energy source, which has evolved and matured to become an economical
alternative to other sources of power. The elementary unit in a photovoltaic generator is a
solar cell, several of which are connected in series and parallel to get the desired power at
the required operating voltage. The schematic of a typical photovoltaic power system is
shown in Figure 1.1, which consists of a solar photovoltaic panel, a shunt voltage
regulator, a battery, and its charge-discharge controller (battery management circuit). The
Figure 1.1: Schematic of a stand-alone photovoltaic power system.

solar energy being an intermittent source of energy, a storage device such as battery is
necessary. The shunt regulator regulates the power from solar panel to the desired
voltage. The generated power is used to supply power to load and also charge battery.
The battery management circuit controls the battery charging and regulates the voltage
during the discharge. This also performs some functions such as overload, deep discharge
and over charging protection. If the load requires AC power rather than DC, another
power inverter circuit is introduced which converts DC power into regulated AC power.
Sometimes all the functions of power control and protection are fused into a single
circuit. The overall efficiency of a solar power system is the product of the efficiency of
the individual subsystems, which could be around 10 % to 25 %.
In an effort to improve the conversion efficiency of solar cells, the conventional
silicon solar cell technology has seen several improvements. The back surface reflector
(BSR) cells and back surface field and reflector (BSFR) cells pushed the cell efficiency
from 10 % to 14 % and more. Of late, the gallium arsenide (GaAs/Ge) solar cell has
pushed the conversion efficiency to 18 % while the multijunction cells pushed it further to
28% efficiency.
1.2
Solar cell
Solar cell is a p-n junction diode of large area (1-100 cm2), which converts energy
of the incident photons into electrical energy. A typical construction of a p-n junction
solar cell is shown in Figure 1.2, which consists of a shallow p-n junction formed on the
surface of a substrate, front ohmic contact grids and a back ohmic contact, and an
antireflection coating on the front surface. When a solar cell is exposed to solar spectrum,
photons having energy equal to or greater than the band gap (Eg) of the solar cell material,
get absorbed and hole and electron pairs are generated, which are collected by the
respective terminals. Photon energy in excess of Eg is converted into electrical energy
while photon energy less than Eg is either dissipated as heat in the solar cell or
transmitted through. The energy band diagram of a p-n junction under illumination is
shown in Figure 1.3 and its ideal equivalent circuit is shown in Figure 1.4, where a
constant current source is in parallel with a diode. The current source Iph results from the
charge carriers excited by solar radiation. The electrical characteristic of a solar cell under
dark condition is similar to that of a p-n diode as shown in Figure 1.5.
Figure 1.2: Typical construction of a p-n

junction solar cell
Figure 1.3: Energy band diagram of a p-n

junction solar cell under
illumination
Figure 1.4: Ideal equivalent circuit of a solar cell
Figure 1.5: Dark I-V characteristics of solar cell
The diode current Id is,
Vd Ir
I d = I o e VT 1
(1.1)
Under illumination the solar cell current is,

VdV+ Ir
I L = I ph I d = I ph I o e T 1
VVd
I L ISC I o e T
(1.2)
(1.3)
where,
Io
IL
Iph
Vd
r
VT
T
q
k
reverse saturation current

load current
photon generated current ~ Isc
cell voltage / bias voltage / applied voltage
diode factor
bulk resistance of the diode (series resistance)
thermal voltage = kT/q
temperature in K
electron charge
Boltzmann constant
The Current-Voltage (I-V) characteristic under illumination is shown in

Figure 1.6. It shows the cell open
circuit voltage (Voc), the short circuit
current (Isc), the voltage at maximum
power (Vmp), the current at maximum
power (Imp), and the maximum power
point (Pmp). The conventional current
direction is used, which is generally
Figure 1.6: I-V characteristics of illuminated

solar cell
used in electronics. It may be observed that when solar cell is generating power, current is
negative. The solar cell efficiency (s) is defined as the ratio of maximum power
generated (Pm) to the solar radiation (Pi) incident on the cell.
1.2.1
Structural details of solar cell
Solar cell is a p-n junction grown on a substrate, generally p type. The top
layer, called the emitter is a very thin layer so that light can penetrate into the depletion
region. A metallic grid at the top collects electrons and the bottom metalization also
serves the similar function. Anti-reflection coating is provided on the top surface to avoid
reflection of light. Several other features are added to the cell to make it more efficient.
The most commonly used solar cells are silicon back surface reflector (BSR), silicon back
surface field & reflector (BSFR) and gallium arsenide on germanium (GaAs/Ge) solar
cells. Figure 1.7(a) shows the structure of a silicon solar cell. Figure 1.7 (b) shows the
Figure 1.7: Structural details of different solar cells
structure of a silicon BSFR solar cell, which has an additional p+ layer adjacent to the
cells back contact. This setup a field that aids in the separation of photon-generated
electronhole pairs and the collection of minority carriers, thus increasing the efficiency
of this cell. The silicon solar cell has an efficiency of about 10 to 12 % and the while
BSFR silicon solar cell has an efficiency of about 14%. However BSFR cells degrade
5
faster in space and the efficiency, at the end of their life is as that of silicon solar cells.
Figure 1.7 (c) shows the structure of a gallium arsenide on germanium (GaAs/Ge) solar
cell. The gallium arsenide solar cell has an efficiency of about 18 %, as its Eg is higher
than silicon solar cell. The silicon BSFR and GaAs/Ge solar cells are space grade solar
cells. Each of these types of solar cells has their niche applications, due to their specific
advantages and disadvantages.
1.2.2 Static (DC) characteristics of a solar cell

Figure 1.8, shows the static (DC) equivalent circuit of a solar cell, which consists
of a current source (current equal to short

circuit current (Isc) of the solar cell) a p-n
junction diode and a resistance (Rt) in parallel
and a series resistance (r). The diode is
assumed to be ideal and hence the static
characteristic of a solar cell is not a function
of frequency.
Figure 1.8: Static or DC equivalent

circuit of a solar cell
1.2.2.1 Series resistance
Series resistance (r) is the total ohmic resistance of the cell, which is the sum of
different resistances as given below,
r = R cp + R bp + R bn + R cn
(1.4)
where,
Rcp
Rcn
Rbp
Rbn
contact resistance between metal and p type semiconductor

contact resistance between metal and n type semiconductor
bulk resistance of the p type region
bulk resistance of the n type region
The main contribution to series resistance (r) comes from Rbn and Rbp
A small variation in 'r' can have profound impact on the energy conversion
efficiency of a solar cell as shown in Figure1.9 (a). Change in r could be caused by
any of the three factors; viz., a) exposure to heavy particle radiation, b) temperature
cycling and c) humidity.
1.2.2.2 Shunt resistance
Shunt resistance (Rt) arises from the recombination of electronhole pairs in the
transition region of the p-n junction. Due to this, a portion of the electrical energy
generated inside the solar cell is lost through internal cell leakage. Several such leakage
paths exists; viz a) recombination current within the bulk of the solar cell, b) surface
leakage through the cell edges and c) through ncontact metalization; which shunts the
photo-generated current from reaching the load. These leakage paths are neither
uniformly distributed across the cell area nor uniform from one cell to the other. In
general, they are non-linear, unstable and time variant. The effects of all leakage paths are
conceptually combined into a single shunt resistance (Rt). The typical range of shunt
resistance per unit area is 500 /cm2 to 1 k/cm2 for a silicon solar cell. Variation in
shunt resistance will also vary the power delivered to the load as shown in Figure 1.9 (b).
1.2.2.3 Parameters affecting solar cell static (DC) characteristic
The solar cell static (DC) characteristic is a function of the solar radiation
intensity, solar radiation spectrum and cell temperature. The two important parameters
affecting the solar cell characteristics are discussed in detail.
1.2.2.3.1
Effect of solar radiation intensity
The effect of light intensity on the solar cell output is shown in Figure 1.9 (c).
Here, the cell temperature and spectral distribution of the light are maintained/assumed to
be constant. It may be observed from Figure 1.9 (c) that the open circuit voltage increases
marginally with the intensity of the solar radiation and saturates. The cell Voc is constant
in the intensity range 500W/m2-1500W/m2. [Rauschenbach.H.S (1980)]. However, the
short circuit current increases linearly with the intensity of solar radiation, as it is a
function of intensity.
1.2.2.3.2
Effect of temperature
The increase in the cell operating temperature causes a little increase in the cell
short circuit current but a significant decrease in the cell voltage. Figure 1.9 (d) shows the
effect of temperature on I-V characteristics of a solar cell, keeping intensity and spectral
distribution of light constant. The change in cell voltage with temperature is due to a
change in diode conduction characteristics. With increasing solar cell temperature, the
entire I-V curves shift towards lower voltage at a rate of approximately 2.2 to 2.3mV/oC
for silicon solar cell [Millman and Halkias (1972)]. The variation in cell efficiency with
temperature is due to both current and voltage variations.
a) Effect of series resistance
c) Effect of intensity
b) Effect of shunt resistance
d) Effect of Temperature
Figure 1.9: Parameters affecting solar cell static characteristics
1.2.3
Dynamic (AC) characteristics of a solar cell
Static characteristics of a solar cell do not describe the dynamic behavior of the
Figure 1.10: Dynamic or AC equivalent circuit of a solar cell.
where,
Cd
Ct
CB
Cms
Rd
Rt
r
Rp
Cp
diode diffusion capacitance

diode transition capacitance
bulk capacitance between front and back contacts
metal-semiconductor junction capacitance
dynamic resistance of the diode
shunt resistance
series resistance
Rt || Rd
Cd || Ct
*Note: neglecting CB and Cms
solar cell. In order to describe the dynamic or AC behavior of a solar cell, it is necessary
to substitute the solar cell junction diode (Figure 1.8) by its capacitances (Cd and Ct) and
dynamic resistance (Rd) as shown in Figure 1.10. In addition, metal to semiconductor
junction capacitance (Cms) at interconnections and bulk capacitance (CB) between front
and back contact as shown in Figure 1.10 should be considered.
1.2.3.1 Solar cell capacitance
Four types of capacitances are observed in a solar cell, transition capacitance (Ct),
diffusion capacitance (Cd), bulk capacitance (CB) and metal-semiconductor (both p and
n side) junction capacitance (Cms).
1.2.3.1.1
Transition capacitance
Transition capacitance is caused by the separation of charges in the space charge

region and is given by [Millman and Halkias (1972)],
Ct =
dQ
B
=
dVd (Vo Vd )1/ m
(1.5)
where,
m
B
Vo
Vd
2 for abrupt junction and 3 for graded junction

constant
junction voltage
applied voltage / cell voltage
The values of junction voltage (Vo) and constant (B) could be calculated from the doping
levels of n and p regions,
Vo =
kT N A N D
ln
q Ni2
B = Ac
q N or
2
1
1
1
=
+
N NA ND
(1.6)
(1.7)
(1.8)
where,
Ac
o
r
NA
ND
Ni
area of solar cell

permittivity of free space
relative permittivity of semiconductor material
doping concentration in p region
doping concentration in n region
intrinsic concentration of electrons & holes of the base
semiconductor
(Space charge, depletion, transition, junction capacitance are synonymous)
10
1.2.3.1.2
Diffusion capacitance (Cd)
The origin of this capacitance lies in the injected charge stored near the junction
outside the transition region. This capacitance for a step input can be defined as the rate
of change of stored charge with voltage. This is also called storage capacitance.
Cd =
dI
dQ
= L = g d =
dV
dVd
Rd
(1.9)
where,
dIL/dVd
dVd/dIL = 1/gd
solar cell dynamic conductance (gd)

solar cell dynamic resistance (Rd)
By differentiating Equation 1.3,

Rd =
VT
Id
(1.10)
Substituting Equation 1.10 for Rd in Equation 1.9.

Cd =
I d
VT
(1.11)
Substituting Equation 1.1 for current (Id), Equation 1.11 is re-written as,
Vd
Cd =
I o e VT
VT
(1.12)
where,
Id
current through the solar cell diode (same as solar cell dark current)
diode factor
minority carrier lifetime
It is observed from Equation 1.11, that the diffusion capacitance is proportional to

the solar cell diode current (Id). It is to be noted that for a cell current (IL) solar cell diode
current (Id) is equal to (Isc-IL) in an illuminated solar cell and equal to IL in dark condition.
11
Diffusion capacitance (Cd) is a function of frequency and wave shape of the input
signal [Millman and Halkias (1972)]. The diffusion capacitance (Cd) for a sinusoidal
input at low frequencies is given by,
Cd =
where,
1
I oe
2 VT
Rdo
Vd
VT
2Rdo
for
( << 1)
(1.13)
Rd at low frequency
which is half the value given in Equation 1.11, for a step input signal.
At frequencies ( >>1) the diffusion capacitance is given by,
1
2
1
Cdhf =
Ioe
2 VT
Vd
VT
(1.14)
Cdhf
where
1.2.3.1.3
2 1
=
2 R do
Cdo
(1.15)
Cd at low frequency
Bulk capacitance
The bulk capacitance is due to the dielectric property of the semiconductor,

sandwiched between two parallel plates, which is similar to a parallel plate capacitor.
This is in the order of 50pF/cm2 for silicon and very small compared to other cell
capacitance values and hence, it is neglected.
1.2.3.1.4
Metal-Semiconductor junction capacitance
A capacitance exists at the metal-semiconductor junction at both p and n

semiconductor-electrodes interfaces. However, this is in parallel with its series resistance
12
(rcp and rcn) of the cell. Series resistance is of the order of 0.01 or less, hence the effect
of this capacitance is very small.
1.2.3.2 Solar cell dynamic resistance (Rd)
For small signal operation, the dynamic resistance or incremental resistance (Rd)
is an important parameter and is defined as the reciprocal of the slope of the I-V
characteristics (Rd = dV / dId). The dynamic resistance is not a constant, but depends on
the diode current (Id) [Millman and Halkias (1972)],
gd =
I
dI L
= d
dVd VT
(1.16)
Vd
dV
VT VT VT
Rd = d
=
e
as I d >> I o
dI L
Id
Io
(1.17)
Under short circuit condition the solar cell diode current is very small (ideally
zero), hence the solar cell dynamic conductance will be small and dynamic resistance will
be large. Under open circuit condition the solar cell diode current is large, hence the solar
cell dynamic conductance will be large and dynamic resistance will be small as seen from
the Equations 1.16 and 1.17. The dynamic resistance (Rd) varies inversely with current
and directly proportionally with temperature. The dynamic resistance (Rd) is also a
function of frequency (similar to capacitance) as given by [Millman and Halkias (1972)],
1
Vd
Rdhf
2 2 VT - VT
e
=
I o
Rdhf
2 2
=
Rdo

(1.18)
where
Rdo
(1.19)
Rd at low frequency
13
1.3
Importance of solar cell AC parameters

In the past, power conditioners were either linear or low speed switching circuits.
High speed switching, pulse width modulated (PWM) charge controller, converter and
power conditioners came into vogue as demand for higher power, smaller size, lesser
weight and higher efficiency increased. This necessitated a better understanding of the
AC characteristics of a solar cell, especially its capacitance.
The effect of solar cell capacitance was first observed by James Lovelady and
Youssef Kohanzadeh (1985) while characterizing the higher efficiency BSFR silicon solar
panel / cell using Large Area Pulsed

Solar Simulator (LAPSS) with 1ms
light pulse. These I-V characteristics
matched
with
the
I-V
characteristics taken under continuous illumination only at the end

points (open circuit and short
Figure-1.11: 'I-V' characteristics of a solar cell
measured using LAPSS
circuit) and deviated everywhere

else. However, at the maximum
power point the LAPSS measured values are below the actual values, while sweeping
from short circuit to open circuit condition. Similarly while sweeping from open circuit to
short circuit condition the LAPSS measured values are more than the actual values as
shown in Figure 1.11. This behavior was identified as due to capacitive effect of the solar
cell / panel, which is a function of measurement speed. This shows that, the behavior of a
solar panel cannot be characterized completely by its static parameters. Generally in highspeed shunt switching voltage regulators the operating point of the solar panel vary at
14
high speed. Hence, the performance of the voltage regulator depend on AC parameters of
solar cell/panel.
Therefore, a systematic and thorough study is needed to understand the variation
of solar cell AC parameters with operating point, temperature and illumination along with
their effect on design of power conditioners.
1.4
Measurement techniques
It has been seen earlier that solar cell capacitance and resistance are nonlinear
with respect to operating voltage. Hence, the measured value depends on the method and
conditions of measurement. One of the methods to measure AC parameters is by applying
a small signal around the operating point. This is frequency domain technique, which
assumes piece wise linearity around the operating point and measures local or differential
values.
Another method is the time domain technique, wherein AC parameters are
measured over a range of operating points. For example in solar cells the measurement is
carried out from short circuit to open circuit voltage or vice-versa. This measures the
integral value over the measurement range.
1.4.1
Frequency domain (Impedance spectroscopy)
Impedance spectroscopy (IS) is a frequency domain technique and is particularly

characterized by the measurement and analysis of complex components of the impedance
of a device in a complex plane. Such a plot is used in interpreting the small signal
response of a non-linear electrical network. Impedance spectroscopy is commonly used
by electro-chemists to study the kinetics of electro-chemical reactions, corrosion related
problems, etc.
1.4.1.1 Principle
When a signal v (t) = Vm sin(t) is applied to a device a current

i (t) = Im sin (t + ) results where '' is the phase difference between current and voltage
15
and f = /2, 'f' is the signal frequency. Conventionally complex impedance of a device is
defined as
Z() =
Vm e jw
V
= m e j
j( w + )
Ime
Im
(1.20)
which can be written as,

Z() =
V
Vm
Cos + j m Sin
Im
Im
(1.21)
Z | () = (Vm/Im) Cos
where ,
and
Z || () = (Vm/Im) Sin
Z ( ) = Z | ( ) jZ || ( )
(1.22)
or
R jX
The magnitude and phase of the impedance is given by,

Z() =
[Z ()] + [Z (w )]
|
||
(1.23)
and
Z|| ()
= tan 1 |
Z ()
(1.24)
Figure 1.12: Small signal measurement at a operating point
16
In a nonlinear device such as solar cell, if a small sinusoidal signal is applied

about its operating point (Vdc), current of the same frequency results with a shift in the
phase () of the signal, about the DC current. The signal amplitude must be small enough,
so that the non-linear characteristic can be assumed linear over the operating point called
piecewise linearization. This ensures that harmonic frequencies are not generated and
measures the dynamic characteristic of the device as shown in Figure 1.12. Piecewise
linearization permits the use of linear circuit theory to model a nonlinear device about the
operating point.
In impedance spectroscopy, the real and imaginary components of a device
measured over a range of frequencies, generally 3 to 4 decades, and are plotted in
complex plane called the impedance spectrum. The imaginary part of the impedance
('Y' coordinate) and the real part ('X' coordinate) define a point on the impedance plane at
a given frequency. Impedance spectrum is the locus of the point for varying frequencies.
From the shape and magnitude of these impedance spectra, the device can be modeled
using electrical components assuming piecewise linearity. By measuring the responses
over a range of operating points the nonlinear device can be characterized in detail.
1.4.1.2 Impedance spectrum of passive components and networks
Impedance spectra of passive components such as resistor, capacitor, and inductor

are shown in Figures 1.13 (a), (b) and (c) respectively.
For an ideal resistor, the impedance spectrum is a point on the real axis at a distance
equal to the value of R from the origin as shown in Figure 1.13(a). The impedance is
independent of frequency (). The reactance of an inductor is a function of frequency
(). The impedance spectrum of an ideal inductor (L) is a straight line along the positive
imaginary axis. As the frequency () approaches to infinity the impedance spectrum
17
moves away from the origin on the imaginary axis, as shown in Figure 1.13(b).
Similarly, for an ideal capacitor (C) the impedance spectrum is as shown in
Figure 1.13(c).
a)
b)
c)
Figure 1.13: Impedance spectrum of passive components
The impedance spectrum for an R-L series network is shown in Figure 1.14(a),
which is a combination of the impedances of an ideal resistor and an ideal inductor. The
distance between the impedance spectrum and origin along the real axis is equal to the
(a)
(b)
Figure 1.14: Impedance spectra of series passive networks
18
resistor (R) that is in series with inductor (L). Similarly, the impedance spectrum for
ideal resistor and capacitor (R-C) connected in series is shown in Figure 1.14(b).
The impedance spectrum of a parallel R-L network is shown in Figure 1.15(a),
which is a semicircle with a radius equal to `R/2. The semicircle lies in the first quadrant
about the real axis and touches the origin.
Similarly the impedance spectrum of a parallel R-C network is shown in
Figure 1.15 (b). Here, the impedance spectrum lies in the fourth quadrant and is a semi-
circle touching the origin. The radius of the semi-circle is equal `R/2 (similar to that
given for parallel R-L network).
(a)
(b)
Figure 1.15: Impedance spectra of parallel passive networks
The mathematical derivation to show that the impedance spectrum of a parallel
RC network is a semicircle is given below,
Figure 1.16 is redrawn from Figure 1.15 (b) for better clarity and ease of understanding
Figure 1.16: Impedance spectrum of a network consisting of capacitor and

resistor in parallel
19
The total impedance (Z) for a network with resistor (Rp) and capacitor (Cp) connected in
parallel is given by,
Z=
R p ( jX p )
(1.25)
R p jX p
Separating the real and imaginary parts, impedance (Z) becomes,
Z=
R p X 2p
2
R p + Xp
R p Xp
R p + Xp
(1.26)
The Equation 1.26 is in the form,

Z = R s jX s
(1.27)
Consider the general equation for a circle,
(x a )2 + ( y b )2
= r2
(1.28)
where a, b are the co-ordinates of the center of the circle and r is radius.
Substituting a= Rp/2 , b= 0 and r= Rp/2 in Equation 1.28
2
R
R s p + (X s )2 = p
2
(1.29)
Simplifying
(R s )2 + (Xs )2 = R p R s
R +X =
2
s
2
s
R p2 X p2
(R
2
p
+ X p2
= R p Rs
(1.30)
(1.31)
It can be seen that Equations 1.31 and 1.29 are equivalent. This shows that the
radius of the impedance spectrum of the series equivalent circuit of a parallel RpCp
network is `Rp/2, where Rp is the parallel resistance.
20
Impedance spectrum of R-C-r network
For an `R-C-r network, the impedance spectrum is a semi circle in fourth

quadrant, with a radius equal to half the value of the resistance (R/2) as shown
Figure 1.17. The semicircle is shifted away from the origin by a distance equal to
resistance (r). Many devices have

equivalent circuits consisting of
two
parallel
RC
networks
connected with a series resistor (r).

The impedance spectrum of such
devices is as shown in Figure 1.18,
Figure 1.17: Impedance spectrum of a R-C-r

network
which consist of two semi circles.

Two semi circles are distinct as their time constants are quite apart. The offset from the
origin gives the value of the series resistor.
Thus the impedance spectrum gives details of the device under test. Information
such as capacitance (C), resistance (R) and series resistance (r) can be deduced easily.
The spectrum also shows the frequency dependence of the device parameters, if any, by
its shape. Hence, impedance spectroscopy method is the best suited for measurement of
AC parameters of a solar cell.
Figure 1.18: Typical Impedance spectrum of a network with two parallel RC and a
series resistor (r)
21
Impedance spectroscopy technique can be used to measure parameters of

non-linear devices like solar cell as it assumes piecewise linearity. Hence
instrumentation based on this technique has been developed as a part of this
research work.
1.4.2
Time domain technique (Charge accumulation measurement)
Time domain technique is a transient measurement technique, in which the cell

voltage varies form short circuit to open circuit or vice versa. Hence, the measured AC
parameters will be integral values from short circuit to open circuit or vice versa,
depending on the test conditions. Generally time domain techniques like open circuit
voltage decay (OCVD), short circuit current decay (SCCD), open circuit voltage build-up
(OCVB), etc., are used to measure the cell parameters such as minority carrier lifetime
(), surface recombination velocity (S), minority carrier diffusion length (Ld).
Often the solar cell is switched from short circuit to an operating point in a
switching voltage regulator. When such type of switching is done, the charge
accumulated in the solar cell is transferred to switch. Under these circumstances what is
relevant is a solar cell capacitance that represents the accumulated charge. Hence in this
technique the total charge accumulated in the solar cell is measured at different operating
voltages and then the solar cell capacitance is estimated.
1.4.2.1 Principle
Solar cell being a nonlinear device the total charge stored in a solar cell depends
on the cell voltage and is given by,
Vd
Q = C p dv
(1.32)
where,
Q
Cp
Vd
total charge stored

solar cell differential capacitance = dQ/dVd by definition.
voltage across solar cell
22
The current due to stored charge is,

i=
dQ
dV
= Cp
dt
dt
(1.33)
Equations 1.32 and 1.33 explicitly recognize the change in both capacitance and
voltage as a function of time. A linear capacitor (Cq), which stores the same amount of
charge as the nonlinear cell capacitor at the operating voltage (Vd) can be defined by
Equation 1.34. This is called charge equivalent capacitor of a cell and is given by,
Q
1
Cq =
=
Vd Vd
Vd
idt
(1.34)
also Cq is,
1
Cq =
Vd
Vd
C dv
p
(1.35)
A simple measurement set-up to measure solar cell capacitance using charge

accumulation measurement technique in time domain is developed.
23
Chapter 2
LITERATURE OVERVIEW
Historically solar cell AC parameters, particularly cell capacitance has been
measured for a variety of reasons. The most imporatant among them is determination of
minority carrier diffusion parameters such as diffusion length Ld, diffusion coefficient
Dc, surface recombination velocity S or carrier lifetime . It is from these parameters
the performance of a solar cell or the efficiency of the process is determined. To this end
several methods of measurement in time and frequency domain have been developed. As
the solar cell technology is developed, solar cell capacitance is seen as an opertional
parameter that need to be measured for efficient operation of switching voltage regulators
used in photovoltaic power system. This paradigm shift brought about certain new
definiations, new techniques and need for extensive characterization of the device. The
survey of literature presented here has taken cognizance of these developments and
fundamental requirements for the work under taken. Such of the works that are purely
measurements with well established techniques for material or process qualifications have
either been omitted or received cusory review. This review concentrates on literature that
either has stressed the technique of measurement, instrumentation for measurement,
measurements on solar cells and applications of solar cell parameters for design of
photovoltaic systems.
The literature survey is presented on four topics; 1) Measurement techniques, 2)
Measurements on solar cells, 3) Impedance measuring instruments and 4) Applications
of solar cell.
2.1
Measurement Techniques
Various investigators have adopted different measurement techniques to measure
solar cell AC parameters. As this involves measurement of nonlinear device parameters

24
under different conditions, it remains a challenging task in the field of measurement

science even today. As discussed in Chapter 1 the measurement technique is broadly
classified in to two domains of measurement such as time and frequency domains.
2.1.1
Time domain
The literature collected on time domain technique are reviewed and the summary
is presented.
Stroke E D et al. (1977) measured the solar cell minority carrier diffusion length by
measuring the short circuit current as a function of wavelength of incident light.
John E Mahan, et., al.(1979) reported an experimental technique for determining the
minority carrier lifetime within the base region of p-n junction solar cell. They
measured the open circuit voltage decay by forward biasing the solar cell with a
flashlight. They reported that photo induced open circuit voltage decay technique
is a reliable and useful method to determine the base minority carrier lifetime ()
in solar cells.
Dhariwal S R, et al. (1981) carried out a detailed study on the measurement of carrier
lifetime in solar cells. They reviewed various measurement techniques like open
circuit voltage decay, reverse recovery, photoconductivity decay, spectral
response, short circuit capacitance measurement, impedance measurement, light
induced photovoltaic decay and open circuit and short circuit switching. They
developed a common mathematical algorithm, from which results of all these
techniques can be obtained. Even though they measured impedance and
capacitance of solar cell, their objectives was to get the diffusion parameters such
as carrier lifetime and not AC parameters of a solar cell and its application.
Dieter K Schroder et al. (1984) reported that the pulse MOS capacitor is routinely used to
measure generation lifetime. But they have developed a new technique where the
25
same device was used to obtain the recombination lifetime. The pulse C-t method
was used to measure the capacitance. From this the lifetime of the carrier was
calculated.
Rose. B.H (1984) calculated the effective back surface recombination velocity (S) and
minority carrier lifetime of silicon solar cells using time domain measurement
such as short circuit current decay and open circuit voltage decay. He developed a
measurement set-up and illustrated the practical use of this measurement with an
example.
Champness et al. (1993) measured the solar cell minority carrier diffusion length (Ld) by
invoking the relation between capacitance and diffusion length using photocurrent chopping.
Klaus Burgard et al. (1995) measured the solar cell diffusion length (Ld) and surface
recombination velocity (S) using Electrical Short Circuit Current Decay (ESCCD)
technique. They concluded that ESCCD technique is superior and reliable than
any of the other time domain techniques; such as, open circuit voltage buildup
(OCVB), open circuit voltage decay (OCVD), photocurrent response (PCR).
2.1.2
Frequency domain
The literature collected on the frequency domain measurements are presented in
brief in the following paragraphs.

Gerordo Gordillo (1985) measured the capacitance of Cu2S-Znx Cd1-x S solar cells using
general radio bridge -1615 with oscillator-1316 and detector-1238. The test signal
was 10mV at 100kHz. The measurements were conducted to under stand the
effect of doping concentration of different materials on the cell capacitance. This
technique has certain limitations like biasing the device under test, balancing the
26
bridge for both DC and AC conditions. Hence, it is not found suitable to measure
the AC parameters of nonlinear devices
Abdel Malik T G. (1991) reported a new technique called 'Oscillographic technique' to
measure solar cell capacitance in which the capacitance was measured using a
triangle wave. The solar cell was modelled as a simple parallel combination of
resistance and capacitance. The dynamic resistance (Rd) and series resistance (r)
were measured and reported. The study was done on and iron
phthalocyanines, to understand temperature dependence of low frequency
capacitance.
John H Scofield (1994) mesured the capacitance of Cu(ln,Ga)Se2 polycrystalline thin film
solar cell in terms of complex admittance in the frequency range 1kHz to
1000kHz. The measurement was carried out under dark condition at room
temperature with external bias voltage of -2V to 0.4V. He used frequency
dependance of capacitance and conductance data to derive informations about trap
distribution in the cell. However it was observed that the cell capacitance is
relatively independent of frequency and increases with cell voltage. He also
concluded that the cell resistance is a function of cell voltage.
Manohar lal et al. (1995) measured the complex impedance and AC conductance of
CuInSe2 solar cells using a sophisticated computer aided AC impedance analyzer
of EG&G make in the range of 5Hz to 100kHz. The meausrement was carried out
at different cell temperatures in the range of 263K to 298K, using impedance
spectroscopic technique. The measurements were carried out at a single bias
voltage and at different temperatures to characterize and optimize the solar cell
performance.
27
John H Scofield (1995) carried out measurements on copper indium gallium diselenide
(CIGS) polycrystalline thin film solar cell and reported the effects of series
resistance and inductance on measurement of solar cell AC parameters in terms of
complex admittance. The frequency range of measurement was 1 to 1000kHz. The
solar cell was externally biased with a voltage ranging from 2 to 0.2V, under
dark condition at room temperature. He recommended a measurement frequency
range from 10 to 50kHz for measurement of solar cell AC parameters.
Toufik Taleb et al. (1996) used oscilloscopic technique introduced by Abdel Malik T G
(1991) to measure the effect of temperature on capacitance of Al/microcrystalline
chlorophll a/Ag sandwich cells. The measurements were carried out at different
bias voltages varying from 0.7 to + 0.7V at 0.1Hz in the temperature range of
150 to 20oC. The study revealed the charactersics of traps and their effect on the
performance of the cell.
The above literature revealed that most of the measurements reported in time
domain were used to estimate the diffusion parameters (Ld, D, S, ) of solar cell, but
only one measurement in frequency domain used impedance spectroscopy technique.
2.2
Measurements on Solar Cell

As mentioned earlier the measurement of solar cell diffusion parameters indirectly
indicates the presence of solar cell capacitance. The AC parametrs, especially cell
capacitance was not considered as important at the system level earlier. Hence, direct
measurement of AC parameters of solar cell was not attempted.
James Lovelady and Youssef Kohanzadeh (1985) measured the Current-Voltage (I-V)
characterstics of large area BSFR silicon solar panels using Pulsed Solar
Simulator at M/s Spectrolab, Inc., USA. The solar cell was biased externally under
28
dark condition using a current source. The measurements were conducted close to
open circuit condition at a fixed frequency. They measured only parallel resistance
and not series resitance due to the limitations in measurement set-up.
R. Lenk (1992) of space systems, Loral Palo Alto, subsequently reported a correct
measurement technique, where the AC excitation signal is maintained at a value
less that the thermal voltage for better accuracy. The measurements were carried
out on a solar array string and also derived the cell capacitances such as charge
equivalent and energy equivalent capacitances.
Sharma. S K et al. (1992) carried out a theortical study on silicon (BSR and BSFR) solar
cell capacitance and its dependence on cell voltage and cell temperature. They
have concluded that solar cell capacitance is mainly due to diffusion capacitance
which is a function of cell voltage and cell temperature. They have shown that the
capacitance of silicon BSFR solar cell is about six times higher than that of silicon
BSR solar cell at the maximum power point voltage.
Robert L Mueller et al.(1994) measured the AC parameters of GaAs/Ge solar cell in
terms of complex impedance in the frequency range of 100Hz to 100kHz.
However, this study was limited to approximate estimate of cell capacitance and
scalability of cell capacitance to array capacitance. The measurements were
carried out in dark with external bias assuming the solar cell series resistance is
negligible. The results were compared with the silicon BSR and BSFR solar cells.
A large difference in impedance was observed among these solar cells.
Sharma S K. et al. (1996) carried out a theortical analysis of GaAs/ Ge solar cell
capacitance based on the design parameters provided by the manufacturer. They
reported that the typical value of GaAs/Ge cell capacitance is of the order of
10nF/cm2 as against 15F/cm2 for silicon BSFR solar cell, at room temperature.
29
Friesen et al. (1997) reported that the transient measurement of I-V characteristics of
solar cell could expose its capacitance effect. They concluded that it is
complicated to make accurate measurement of I-V characteristics for high
efficiency solar cells as the cell capacitance vitiates the results.
Blok. R et al. (2002) measured the capacitance of the new generation space quality GaAs
and silicon solar cells at low temperature and at low illumination intensity using
time domain technique. The large area sun simulator with pulsed illumination was
used and the transient response of the cell voltage when switched from short
circuit to open circuit was measured. From this time-voltage response the cell
capacitance was calculated. They reported that incorrect time base setting of
oscilloscope or usage of an oscilloscpe that does not have sufficient bandwidth
can introduce significant overestimation of capacitance value due to aliasing.
They also mentioned that transient measurement on a solar cell showed
oscillations as the wiring inductance is charged intially with magnetic energy.
This second order effect can be reduced by a low pass filter network, but
introduces a error in measurement.
Denis Schwander (2002) measured the solar cell capacitance using small signal
meausrement technique. He used the network analyzer over a wide range of
frequencies under dark at different bias volatges. Complex impedance measured
as a function of frequency is used to get a Bode plot. From this the cell
capaciatnce is computed.
It may be noted that the author of this thesis has published his work on the
measurement of silicon BSR, BSFR and GaAs/Ge solar cells using AC impedance
spectroscopy in 2000.
30
2.3
Impedance Measuring Instruments

The literature collected on the instruments developed to measure impedance using
different techniques by various rearchers are presented in brief.

Khalid M Ibrahim, et al. (1985) developed a digital instrument to measure the impedance
by genetarting the quadutarture components of a signal over a freqency range of
1Hz to 1MHz. They measured the voltage across a reference resistor and DUT. A
custom built digital processor is used in the instrument to convert the measured
complex impedance from rectangular to polar form. No bias facility is avaliable in
the instrument. They measured the impedance over 10 to 1M range with 0.5%
error below 1kHz frequency. The frequency response of the op-amps used limited
the measurement accuracy at higher frequencies.
Hartmut Schollmeyer (1985) developed an automatic digital AC bridge and used it as an
impedance to frequency converter. In addition to this, it was used as signal
conditioner to passive sensor. He reported that it works on AC bridge principle
and it can measure resistance, capacitance and inductance by varying the singal
frequency to balance the bridge.
Morgan F. D, et., al. (1986) developed an instrument to measure impedance in the range
of frequency 1mHz to 1kHz. It had three frequency sinusoidal AC sources with a
digital data acqusition. The multiple source frequency measurement reduced the
measurement time.The digital data acquision with a personal computer interface
and a provision for DC bias voltage make the instrument suitable for electro
chemical and corrosion measurements at very low frequencies of the order 103Hz
with a high frequency limit of 5kHz.
Saleem M R Taha (1989), developed a digital instrument to measure the impedance in
both polar and rectangular form. He used a hybrid processor to convert the data in
31
digital form. The instrument indicates the nature of impedance i.e., inductive or
capacitative. The basic system accuracy is reported as 0.2%. This instrument is
very similar to the one developed by Khalid M Ibrahim, et al. (1985) except for
minor differences.
Atmanand M A et al. (1995) developed a novel method for measuring inductance and
capacitance.The measurement is independent of the voltage across DUT and
current through the DUT, as it makes only one set of phase measurements. Device
under test (DUT) was connected in series with standared resistor and the applied
voltage was measured along with the voltage across device under test and the
standard resistor. From this the inductance and capacitance of the DUT were
calculated with an accuracy 2.0%..
Waltrip B C et al. (1995) developed a digital impedance bridge that measures the
impedance of DUT in the frequency range of 10Hz to 100kHz by comparing with
a standard inductors. A linear interpolation algorthim was used to calibrate the
bridge automatically. This employs digital wave synthesis and sampling and
signal processing to determine the impedance of DUT in terms of known
reference impedance.
Yoshitake Yamamoto et al. (1995) develpoed an automatic sensing device for tissue
electrical characterstics. It consists of low distortion sinusoidal waveform
oscillators, phase shifter and a voltage to current converter. It measured the
impedance of a tissue at eight frequency points in the range of 1kHz to 500kHz.
The real and imaginary parts of impednace measured were plotted in a cole-cole
plot.
Alessio Carullo, et al. (2000) developed an instrument to measure electrochemical
impedance using impedance spectroscopy technique. This instrument was used for
32
corrosion monitoring of metallic antiques. Digital signal processor chip was used
for control and processing. The instrument has facility to bias DUT with DC
voltage and the measurements can be made upto a maximum frequency of 10kHz.
Piotr Bilski et al. (2002) developed a virtual spectrum analyzer based on data acquisition
card. They have compared it with conventional DSP based system and concluded
that the virtual instrument is accurate, fast and is less expensive. Only AC signal
(1V) can be applied to the DUT but there was no provision to apply DC bias
voltage. The maximum frequency of measurement was 20kHz.
Even though the two instruments were developed based on impedance
spectroscopy technique they do not have either a DC biasing facility or wide frequency
range to use for measuring the AC parameters of solar cell.
2.4 Applications of solar cell
The literature collected on the applications of solar cells in switching regulators
are presented in brief.
Cho. B H et al. (1988) carried out the design and analysis of bus dynamics of spacecraft
power system using small signal dynamic parameters of solar array. The
performance of the power system was studied under various modes of operation
viz. array shunting, battery charging, etc., which are simulated and compared.
However, the analysis assumed fixed/constant capacitance rather than a nonlinear
capacitor. Also the effect of this nonlinear capacitance on the performance of
switching regulators in terms of bus ripple voltage, etc., was not carried out.
Patil A R et al. (1990), reported the analysis of sequential shunt regulator unit proposed
for space station and space platform. The output voltage ripple was calculated for
the shunt switching voltage regulator, assuming constant solar array capacitance.
Additionally the effect of output impedance of solar cell on the stability of the
33
regulator with proportional controller and proportional integral controller, was

studied and compared. However, the effect of solar cell capacitance was not
considered for estimating the output voltage ripple.
Patel A R et al. (1992), carried out experiments to study the effect of solar cell
capacitance on the shunt switching charge controllers analyzed in their earlier
paper. They concluded that due to array capacitance the shunt switching charge
controllers draw large pulsed current from the solar array when the switch was
closed. They reported that a large inductance was needed to limit this current to a
safe value, but their analysis showed that the use of large inductance affects the
stability of the system and causes oscillations in the solar array current. Later they
proposed to use a damping resistor to improve stability and supress oscillations
which results in additional power loss.
Delepaut. C et al. (1993) carried out study on sequential switching shunt regulator and
observed the impacts introduced by the parasitic harness inductance and array
capacitance, which produced a resonating current during ON and OFF of the
shunt switch. They reported three methods of controlling the peaking oscillatory
current in the shunt switch. The three techniques are a) adding series inductance to
limit inrush current, b) miller capacitor which delays turn ON of the shunt switch,
c) an active current limiter. They reported that active current limiter technique is
independent of harness inductance and solar array current.
Moon. M S et al. (1994) used an inductor enhancement active filter to reduce the
pulsating current in the shunt switch of the sequential shunt switchning unit. This
reduces EMI and also avoids bulky inductor. They reported that the inductance
enhancement is limited by the stability of the active compensation loop. They
34
have modelled the solar array as a current source with a fixed capacitor and
resistor in parallel.
Cho. B H et al. (1995) made measurements on single pulsewidth modulated shunt
switching unit used in multikiloWatt space power system. They reported that due
to solar cell capacitance the PWM section draws a pulsating current from solar
array. This needs to be supressed to reduce noise induced due to electromagnetic
induction and proposed to use large inductor as a filter. Later they proposed to use
active inductance enhancement filter and reported that this results in reduction of
size and weight.
Abdelhalim Zekry et al. (1996) developed a distributed SPICE model of solar cell. The
SPICE model data was compared with the measured data. They concluded that the
errors introduced in static characterstic due to lumped parameters model are not
significant when compared with the distributed parameter model. The modelled
solar cell using its small signal impedance, current-voltage and open circuit
voltage decay characterstics. However, discrepancy was observed in AC
characteristics which could be accounted by modelling the solar cell with two time
constants.
Pablo Rueda et al. (2002) measured the capacitance of multijunction solar cells and
reported its impact on solar array regulator. The scaling of cell to array and
relative capacitances are discussed in detail. However this study is more
qualatitive and does not mention clearly the effect of cell capacitance on bus
volatge ripple, stability and other parameters of the switching regulator. However,
they reported that the measured array capacitance is 20 % to 25 % higher than the
array capacitance calculated from a single cell capacitance.
35
From the literature survey it is observed that only in late 1980s, the effect and
importance of solar cell AC parameters on the design of switchning volrage regulator was
recognised. Hence the study on solar cell AC parameters came in vogue.
2.5
Conclusions
From the review of literature, the following conclusions are drawn;

i. The database avaliable on solar cells AC parameters (like cell transition and
diffusion capacitances, dynamic resistance, shunt resistance, series resistance)
under different conditions (temperature, illumination, etc.,) is not sufficient to
design a reliable and efficient switching voltage regulator.
ii. The measurement techniques reported in the literature cannot be used directly to
measure the AC parameters of solar cell under different conditions
iii. Non of the instruments reported in the literature are not suitable for measuring
solar cell AC parameters.
iv. Scaling of cell AC parameters to panel and its effect are not studied in detail.
v. Use of these AC parameters in design of switching voltage regulators and effect of
these parameters on the performance of switching voltage regulators are reported
sporadically. But they have not considered the non-linear nature of the cell
capacitance.
The literature survey revealed that there is a need to
1. Develop a dedicated instrument to measure all AC parameters of solar cell.
2. Generate database on AC parameters of widely used solar cells of different types.
3. Study the effect of solar cell AC parameters on the performance of switching
voltage regulators, particularly ripple and selection of shunt switch.
36
2.6
Scope and objectives of the present investigations
The present investigations involve:

1.
Study on the Origin of AC parameters in a solar cell.
2.
Study on different measurement techniques such as Frequency domain and

Time domain to measure AC parameters of solar cell
3.
Development of a dedicated instrument to measure solar cell AC parameters.
4.
Measurement of AC parameters of widely used solar cells
5.
Measurement of AC parameters of solar cells at different cell temperatures
6.
Measure AC parameters of solar cells under illumination and dark and

compare.
7.
Scaling of cell capacitance from cell to panel.
8.
Study the effect of solar cell capacitance on the performance and the design of
switching voltage regulators.
2.7 Thesis presentation

With these objectives, a dedicated instrument to measure solar cell AC parameters
has been developed and detailed investigations are carried out on Silicon and GaAs/Ge
solar cells. The AC parameters of solar cell measured are used for design of switching
shunt voltage regulator. This work is presented in the form of thesis. In Chapter 3 the
development of instrumentation is presented. Chapter 4 presents the measured data on
silicon and GaAs/Ge solar cells under various conditions. In Chapter 5 the applications of
solar cell AC parameters in design of switching shunt regulator are presented. Also
analysis on scaling of cell capacitance to array capacitance and the criteria for selection of
shunt switch are presented. Chapter 6 includes the conclusion drawn from this research
work.
37
Chapter 3
INSTRUMENTATION
Impedance spectroscopy is well suited for measuring the AC parameters of
nonlinear devices such as solar cells. Hence, an experimental set-up to measure solar cell
AC parameters using impedance spectroscopic technique is developed with the
commercially available instruments viz; Solartron electrochemical Interface (ECI) and
frequency response analyzer (FRA). As these instruments are designed to suit the
requirements electro-chemical and corrosion related measurements, they have certain
limitations for measuring the solar cell AC parameters. Further, they are very expensive.
Hence, a new instrument called SOLAR CELL IMPEDANCE ANALYZER is
developed, based on impedance spectroscopic technique, and it is tailor made to measure
solar cell parameters. This instrument is designed based on the concept of virtual
instrument and has some very novel features such as a user-friendly menu driven
operation, easy storage of data, software modifiable modules, and internal calibration
facility that enhance the measurement range of the instrument.
3.1
Experimental set-up
An
experimental
set-up
is
developed
with
the
SOLARTRON
make
Electrochemical interface (ECI) and Frequency Response Analyzer (FRA) to measure

solar cell AC parameters. It is shown in Figure 3.1. Figure 3.2 and 3.3 show the block
diagrams of ECI and FRA respectively. The detailed specifications of these instruments
are presented in Appendix 1. ECI is used to apply desired DC bias voltage along with
small AC signal across the device under test (DUT). It measures voltage across the DUT
and also the current through the DUT. FRA generates an AC signal of desired amplitude
and frequency, which is superimposed on the DC voltage. It also calculates the real and
imaginary parts of impedance from the resultant AC voltage and AC current. The features
and operation of ECI and FRA are explained in detail in the following subsections.
3.1.1
Electro-Chemical Interface (ECI)

ECI is a potentiostat that applies the desired bias voltage (DC) and the signal
voltage to the cell under test. One of the important features of this instrument is its ability
to make four terminal measurements. The current flow is between CE and WE but the
set voltage is maintained between RE1 and RE2. The set DC bias and the AC voltage
are also measured between RE1 and RE2. Hence, the magnitude and phase errors due
to resistance and inductance of the connecting leads are eliminated.
The input impedance between RE1 and RE2 is high (>10G). Thus, the current
that flows through the reference electrode is negligible. The voltage (DC and AC)
between RE1 and RE2 is measured by a 5 digit digital voltmeter to an accuracy of
+0.05% and the current in the cell is measured by a zero impedance ammeter by
measuring the voltage drop across the feedback resistor, whose value can be selected
between 0.1 to 10k depending on the DUT (solar cell) current. However, analog AC
voltages proportional to the voltage between RE1 & RE2 and the AC current in the cell
are fed to FRA for further processing.
The AC excitation signal from an external source (FRA) can be super imposed on
the DC voltage between CE & WE through a summing amplifier. The AC voltage
however, is measured between RE1 & RE2.
A potentiostat of this kind is a feedback power amplifier, which could become
unstable depending on the impedance and the frequency response of the connected
device. Hence, ECI is provided with a filter whose bandwidth range is from 8Hz to
1MHz and a suitable filter is selected to ensure feedback stability of the ECI.
Figure 3.1: Schematic of experimental set-up
Figure 3.2: Block diagram of ECI
3.1.2
Frequency Response Analyzer (FRA)

The Frequency response analyzer generates the excitation signal (from 0.1mV to
15Vrms) in the frequency range of (10Hz to 65kHz), which is applied to the solar cell
under test through ECI. The distortion in the generated signal is less than 1% and the
instrument sweeps the frequency range between preset limits in equal logarithmic or
linear steps.
Two signal analyzers (1 and 2) measure in-phase and quadrature components of
voltages applied to channel 1 and 2 simultaneously. The input signal is divided into 104
equally spaced intervals over one full wave. Instantaneous measurement of signals is
made at each of the 104 points by a digital voltmeter. Each of these measurements are
time tagged and stored in a random access memory for further computation.
From the data stored in the memory the FRA calculates the in-phase and
quadrature components of the voltages by numerical integration.
V ( inphase
V( qudrature )
2
=
TP
TP
2
=
TP
TP
V ( t ) sin ( t )dt
(3.1)
V( t ) cos(t )dt
(3 . 2 )
where,
Tp is the period of the applied signal.
The above equations are evaluated using numerical integration technique, by the
FRA in order to compute the amplitude of the in-phase and quadrature components of the
voltages applied to the channels 1 and 2. FRA calculates impedance in polar or
rectangular form. It also computes the ratio of voltages at channel 1 and 2. In the
present measurement this gives the impedance of the solar cell under test, as one of the
channels measure voltage and the other current.
Figure 3.3: Block diagram of FRA
3.1.3
Noise reduction
The following precautionary steps are implemented in the measurement setup to reduce
noise.
a.
Shielding of cables: As a primary step towards noise reduction, the cables are
shielded and the shield is connected to the instrument ground.
b.
Signal amplification: The amplitude of the excitation signal generated by the

FRA is 10 times the required amplitude (100mV). The signal is subsequently
attenuated to 10mV by the ECI. Thus the signal level is kept high during
generation and transmission to ECI, which improved the signal to noise ratio of
the excitation signal. Similarly, the amplitudes of the voltage and the current
(voltage proportional to current) measured by the ECI are amplified 10 times
before being fed to FRA. This again improved the signal to noise ratio during
transfer of signal between the instruments.
c.
Bias compensation: The cell voltage and current contain AC & DC components.
As stated earlier, bias compensation is applied to cancel the DC component. The
DC current is measured and stored in the memory before application of AC signal.
It is subtracted from the cell current (AC and DC), thus the DC current component
is removed.
d.
Averaging: Measurements are started after 20 seconds of the application of

excitation signal to the cell to ensure that the AC transients die down and a steady
state is reached. The measurements made are averaged over several cycles
(5 cycles at the lowest frequency of 1Hz) and the results are considered to be valid
only when running average of the last three measurements is within 1%. FRA is
programmed to indicate error when this condition is not satisfied. Thus, the
measurement accuracy is improved.
e.
Reduction of harmonic noise: Another important feature of this set-up is its

immunity to harmonic noise. The response of the solar cell may contain
harmonics of the excitation frequency due to its non-linearity. The harmonics are
removed during the measurement, as these are orthogonal to the fundamental
T
V (t)I
Sin ( m t ) dt = 0
for
m >1
( 3.3)
wave i.e.,
Thus, on integrating over a complete cycle the harmonic components averaged to

zero. So, the measurement is oblivious to the presence of the harmonic noise.
The noise reduction techniques employed in the present study, as enumerated
above, ensure that the measurements are with better accuracy.
3.1.4
Calibration of the Experimental Set-up

The experimental set-up is calibrated using a passive electrical network. The
different parameters set on the instruments are the same as those used for the
measurement of solar cell impedance. These are listed in Table 3.1 The frequency range
covered is 1Hz to 10kHz with a sinusoidal excitation signal of 10mV (p-p) super imposed
over a DC bias voltage of 1V. The measurements are performed on the electrical network
Figure 3.4: Solartron calibration network

shown in Figure 3.4. The measured values of real and imaginary components of
impedance at various frequencies from 1Hz to 10kHz with 10 steps/decade are tabulated
in Table 3.2. Figure 3.5 shows the impedance spectrum plotted from the measured data.
For the convenience, the positive Y axis is considered as the negative imaginary (Z). It
is observed that the impedance spectrum consists of two distinct semicircles indicating
two RC networks with different time constants. The offset of the semicircles from the
origin indicates the presence of a resistance in series with the two RC networks. This
offset from the origin to the first (small) semicircle indicates the value of series resistance
r directly. From this impedance spectrum, the values of circuit / network parameters
(R,C,r) are calculated as follows,
At point c the magnitude of the imaginary (Z) is equal to the magnitude of
Real (Z) i.e., |Xs2| = Rs2, the line cb represents Xs2 and ab represents Rs2. From the
measured data (refer Table 3.2) and the impedance spectrum the value of Rs2 is
3.36k (=6.15k2.79k) and Xs2 is 3.40k. At this Xs2 the corresponding signal
frequency f2 is 5.08 Hz (refer Table 3.2). The Rs2 and Xs2 are series equivalent circuit
parameters of the network. Using Equation (A2.6) (Appendix 2), the series equivalent
values are converted into parallel circuit parameters and their values are,
Parallel resistance (Rp2) = 6.81k,
Parallel reactance (Xp2) =6.80k.
From this parallel reactance (Xp2), the parallel capacitance (Cp2) is calculated as,
Cp2 (measured)=4.6635F.
Similarly, from the small semi circle (shown in Figure 3.5) the values of R and
C in the electrical network are calculated. The line 'ef' gives the real (Z), equal to
Rs1 = 0.52k (= 2.32k1.8k) and line gf gives the magnitude of Imaginary (Z) equal
to Xs1 = 0.52k, at signal frequency of f1 = 1584.9Hz (refer Table 3.2). From these series
equivalent circuit parameters the parallel circuit elements are calculated and are,
Rp1(measured)=1.047k,
Xp1(measured)=1.030k,
Cp1(measured)=0.0975F
The line he i.e. line connecting origin to first semi circle will directly give the value of
the series resistance r. Its value is 1.8k.
Table 3.3 compares the actual value with the measured value of the various circuit
elements. The percentage of error is calculated as,
% error =
Actual value Measured value

100
Actual value
(3.4)
Table 3.1 (a): Setting of different parameters of ECI during measurement

Sl.
No.
1.
Description of the
parameters
DC bias voltage,
Set Value
Remarks
1V
2.
Current measuring resistor
1 to 1 k
Value depends on the

requirements
Depending on the cell
impedance
3.
DC bias voltage rejection
4.
DC bias current rejection
Equal to bias
voltage
Auto
5.
Output Voltage and Current

amplification
Signal attenuation
Digital voltmeter resolution
6.
7.
Current just before

application of AC signal is
recorded and subtracted
10
0.1
5 digits
Auto ranging
Table 3.1 (b): Setting of different parameters of FRA for measurement

Sl.
No.
1.
Description of the
parameters
AC signal amplitude
Set Value
Remarks
100 mV (p-p)
Signal is attenuated to 1 mV
by ECI before applying to
device under test.
2.
3.
4.
Signal frequency range

Waveform
Signal integration time
1 Hz to 10 kHz
Sinusoidal
5 cycles
5.
20 s
6.
7.
8.
Time to start measurement

after application of signal
Frequency sweep mode
Number of steps per decade
Direction of sweep
9.
Display parameters
10
Display mode
Logarithmic
10
Both up and
down
Impedance (ratio
of channel 1 and
channel 2)
Rs+ jXs
If the averaging of three

consecutive measurements
are within 1% measurement
the integration is stopped.
From high frequency to low

frequency and vice versa
Table 3.2: Impedance of calibration setup as a function of frequency

Specimen: standard calibration network (Figure-3.4)
VDC: 1 V
IDC: 0.086 mA
RS: 1 k
o
VAC: 10 mV
Room Temperature: 22 C
Frequency
Real Z
Imaginary Z
(Hz)
(k)
(k)
1.00
9.35
1.34
1.26
9.22
1.64
1.58
8.95
2.00
1.99
8.63
2.38
2.51
8.18
2.75
3.16
7.62
3.08
3.98
6.91
3.30
5.08
6.15
3.40
6.31
5.39
3.30
7.94
4.70
3.05
10.00
4.14
2.70
12.59
3.72
2.32
15.85
3.40
1.94
19.95
3.19
1.60
25.12
3.05
1.30
31.62
2.96
1.06
39.81
2.91
0.86
50.12
2.86
0.70
63.09
2.84
0.57
79.43
2.82
0.47
100.00
2.81
0.40
125.00
2.81
0.34
158.49
2.79
0.31
199.52
2.79
0.29
251.19
2.78
0.29
316.22
2.76
0.30
398.10
2.74
0.32
501.18
2.71
0.35
630.95
2.66
0.40
794.30
2.62
0.45
1000.00
2.53
0.49
1258.90
2.43
0.51
1584.90
2.32
0.52
1995.00
2.20
0.50
2511.00
2.10
0.46
3162.20
2.02
0.41
3981.00
1.95
0.35
5011.80
1.91
0.29
6309.40
1.88
0.23
7943.00
1.85
0.19
10000.00
1.84
0.15
Figure 3.5: Impedance spectrum of Calibration setup
Table 3.3: Comparison of Actual and measured values of network components

Circuit parameters /
Elements
Series resistance
r
Parallel Resistance
Rp1
Parallel Resistance
Rp2
Parallel Capacitance
Cp1
Parallel Capacitance
Cp2
Actual Value
Measured Value
% Error
1.8 k
1.8 k
1 k
1.05 k
-5
6.8 k
6.81 k
-0.15
0.1 F
0.1 F
4.7 F
4.66 F
0.85
(Tolerance + 0.5 %)
The maximum error observed is around +5%. The advantages of this technique of
measurement are as follows,
1. The measurements are quite accurate.
2. The measurements can be carried out under steady state. i.e. at a particular
operating condition
3. All the circuit parameters can be measured.
From the above investigations it is concluded that the impedance spectroscopy
method to measure AC parameters of nonlinear devices is quite accurate.
3.1.5
Limitations of the measurement setup
The ECI & FRA used with the measurement setup have certain limitations for the
measurement of solar cell AC parameters and they are,
Most of these instruments are designed to suit electrochemical impedance

measurements and hence, their upper frequency range is limited to 60kHz to
100kHz with a lower frequency range of mHz or Hz. Hence, for devices
whose time constant is less than 15s the impedance spectrum will not be a
complete semicircle. Hence, series resistance has to be estimated by
extrapolating the spectrum. However, for solar cell measurements the
frequency range required is 10Hz to 1MHz or more as the time constants
involved are smaller.
The new generation developmental lab scale solar cells are small in size
(approximately 1 to 2cm2 in cross section), whose capacitance value is in the
order of nF and generally their time constant is small. Hence, the frequency
range of the instrument should be sufficiently large (say 1MHz)
If the spectrum is incomplete, the information about frequency dependence of

resistance and capacitance of nonlinear device such as solar cell cannot be
estimated.
Generally, the inductance of a solar cell is very small and this can be seen only
at higher frequencies, as resistor-inductor time constant is very small.
The post measurement data processing is quite cumbersome and requires more
time and effort. The instrument stores the measured data in binary format,
which has to be transferred to personal computer and the data has to be
converted to suitable format such as MS word or excel. With online display of
the data, measurement is easy, comfortable and fast.
The test set-up and data cannot be stored in the instrument. The instrument
needs to be programmed every time the test is started. These additional
features may be available at extra cost in recent versions of the instruments.
Generally these instruments are designed for electrochemical applications,

where the time constants of the measuring device are large (order of ms to
seconds) and are designed to operate at low frequencies. During measurements
to avoid instability filters are added (which are programmable and in built)
whose cut-off frequencies are 8Hz to 1MHz. For high stability measurement
these filters are added which limits the maximum measurement frequency and
if the instrument is set for high frequency mode the system can be unstable
and lead to undue oscillations damaging the device under test.
A definite need of a dedicated instrument for measuring the solar cell AC

parameters using impedance spectroscopy technique is highlighted in the abovementioned shortcomings of the existing instrumentations. Hence, as a part of this research
work, a new instrument is developed to enhance the range of measurement and accuracy,
which over comes the limitations of the exiting instrumentation for solar cell applications.
The instrument is developed using the concept of virtual instrument with custombuilt hardware and dedicated software. The new instrument is called SOLAR
CELL IMPEDANCE ANALYZER.
3.2 Solar Cell Impedance Analyzer

In this section the details about the development of solar cell impedance
analyzer are presented. This section describes the design requirements, hardware
realization, software development, techniques employed to reduce noise and errors,

software range extender or internal calibration to improve virtually the frequency
response of hardware through software, calibration and testing.
3.2.1
Design requirements
The following guidelines and design specifications to develop a dedicated

instrument for measuring solar cell AC parameters are prepared based on the previous
experience.
a)
The impedance of a solar cell is to be measured by applying a small sinusoidal

signal (10mV) to the solar cell. The in-phase and quadrature components of the
current response are measured and the impedance is computed. It is known that
the solar cell AC parameters are a function of the cell operating conditions and
hence an external DC source should be available to apply the required DC bias
voltage to the cell. In order to avoid errors in measurement, the bias voltage must
be stable with time and over the temperature range of operation. Normally, a bias
voltage, in the range of 0V to 2.5V (depending on the type of solar cell), which
can be set with a resolution of 0.01V, is adequate. The biasing source used should
be able to drive a current of around 1A (depending on the type of solar cell and
size), without distorting the excitation signal.
b)
The errors due to resistance and inductance of connecting wires are to be

minimized.
c)
The measurements have to be carried out over a range of frequencies from 10Hz
to 1MHz. Therefore, the signal source should be able to generate sinusoidal
signals over a wide range of frequencies and it should be able to set the desired
frequency and amplitude.
d)
The instrument should measure in-phase and quadrature components of current,

its response with respect to the excitation signal with good accuracy.
e)
The AC signal amplitude should be less the thermal voltage (VT), about
26mV at 25oC, to ensure that the response of the system is piecewise linear to a
good approximation. As mentioned earlier this AC signal is super imposed on a

DC bias voltage (0V to + 2.5V) and therefore, the instrument should be capable of
measuring small AC signals in the presence of large DC bias voltage.
f)
The input impedance of the instrument at the measurement point must be very
high (> 1M) in order to ensure that cell is not loaded while making
measurement.
g)
Reduction of noise: Solar cell, whose impedance has to be measured, could be

located at a distance from the instrument. In such a situation, long cables connect
solar cell and the instrument, which pick-up noise generated by other equipments
in an industrial environment. For accurate measurement at low signal levels, it is
essential that the instrument incorporate special methods to reduce noise. In
Section 3.2.4 the details about the noise reduction methods and technique
incorporated in solar cell impedance analyzer are presented.
h)
Rejection of harmonics: When biased and excited even by a small AC voltage, the
resultant AC current may contain harmonics of the excitation voltage, as the solar
cell is a non-linear device. These harmonics introduce error in the measurement of
phase angle between the AC voltage and current. Hence, suitable technique has to
be incorporated to reduce the error due to harmonic noise over the operating range
of frequency.
i)
The instrument should be able to calculate impedance (magnitude, real and

imaginary parts), from the measured voltage, current, and its phase angle.
j)
The instrument should display online the impedance spectrum and impedance
(both real and imaginary), phase angle etc., as a function of frequency.
k)
The instrument should have a facility to store the test specifications / set-up and
the measured results.
l)
The instrument should be capable of archiving results and should have provision
for offline data processing.
Based on these design requirements the solar cell impedance analyzer is developed.
3.2.2
Description of the Instrument
Of-late, the development in computer and its accessories has made practical
realization of the virtual instruments. The most important features of virtual instruments
are multi-platform compatibility, flexibility, improved system performance, improved
programming efficiency, Internet connectivity, low design development and fabrication
time, low cost, and provision of a total solution. Today, there are virtual instruments
available in the market such as oscilloscope, multimeter, waveform generator, function
generator, spectrum analyzer, etc., which are based on readily available data acquisition
cards, but an impedance analyzer based on impedance spectroscopy technique is not
available.
Figure 3.6 shows the block diagram of the solar cell impedance analyzer, which is
developed as a combination of custom built wide band amplifier with a control card, a
personal computer and add on cards viz high-speed data acquisition card (NI5112) and
arbitrary function generator (NI5401) from M/s National Instruments. The application
specific software is developed using graphical programming language LABVIEW6i. The
details of the software are presented in the latter part of this chapter.
3.2.2.1 Arbitrary function generator card (NI5401)
An arbitrary function generator and high-speed data acquisition cards sit on PCI
bus of personal computer. The specifications of these cards are presented in Appendix 3.
Arbitrary function generator card is used to generate a small AC sinusoidal signal of
varying frequency and required DC bias voltage.
It is a single channel, 12-bit
programmable function generation card, with 40MHz update rate. This can generate
sinusoidal signals from 1Hz to 16MHz in the voltage range of 0 to 5V, with an accuracy
of 0.1dB and resolution of 0.001dB steps. Additionally through software, the output
impedance can be set to 50 or greater. The sine wave spectral purity of -60dbc up-to 1
MHz is available. Frequency locking range of 100ppm ensure stable and reliable
sinusoidal signal. Hence, this card is chosen to generate required small signal sinusoidal
AC voltage from 10mV to 25mV (can be varied with 1mV resolution) in the frequency
range of 10 Hz to 1 MHz along with DC bias voltage of + 5V (can be varied with 10 mV
resolution), which is fed to the power amplifier. Wideband power amplifier can source or
sink current up to 1A at the maximum voltage of + 5V. Figure 3.7, shows the detailed
circuit diagram of the wideband power amplifier and control card.
3.2.2.2 Power amplifier with control circuit (custom built)
The power amplifier is a complementary symmetry wide band precision amplifier

using bipolar transistors (Q1 to Q4) at output in darlington configuration and an op-amp
(U3) preamplifier. The internal feedback circuit within the power amplifier ensures
constant AC/DC voltage across the device under test (DUT). The voltage across DUT
available at terminals J10 is measured by one of the channels of data acquisition card
(NI5112) and the current though the device is measured by the voltage drop across a noninductive precision sense resistor available at terminal J9. Four-probe technique is used
to sense current, which reduces error due to lead inductance and lead resistance of the
sense resistor. The voltage drop across the sense resistor (R1 to R5) acquired through a
differential amplifier (U4) with unity gain is connected to the second channel of the data
acquisition card (NI5112). A microcontroller (U2) is used to control the relay logic that
selects sense resistors (0.1 to 1k in steps of decade) for measuring a wide range of
currents through DUT. The relays (Rly1 to 5) are controlled through the microcontroller
(89C51) to select the precision sense resistor (0.1 to 1k, + 0.05%) for current
measurement through device under test. Relays (Rly6 and 7) are used to isolate the device
under test and connect a calibration resistor (R6 = 1+ 0.05%) internally. This is used for
internal calibration. The internal calibration procedure is explained in section 3.2.5. The
microcontroller is interfaced to a personal computer through serial port (RS232) using
level converter integrated circuit (U1- MAX 232), which in turn controls the relay. The
microcontroller is programmed and the custom-built software is written in assembly
language. Light emitting diodes LED1 to LED5 indicate the status of the sense resistor
selected, where as LED6 indicates the instrument under calibration. LED7 to LED9
indicate the DC power to instrument. The custom-built regulated DC power supply with
+15V and +5V is used, which operated on 220V, 50Hz AC supply, whose circuit details
are not shown in Figure 3.7. The personal computer with Windows 2000 operating
system and INTEL Pentium processor operating at 400MHz with 512MB operating
memory (RAM) is used.
Specifications of the precision wide band power amplifier are given below,
a.
b.
Input
AC signal
Amplitude
Frequency range
Gain
DC Signal
Amplitude
Current
Gain
Measurement
AC signal
Voltage
Current
DC signal
Voltage
Current
10mV to 25mV (peak to peak)

10Hz to 1MHz
Unity
0 to + 2.5V
+ 1A
Unity
0 to 25mV (max)
0 to 25mV (max) measured across
resistor
0 to +2.5V
0 to + 1A
c.
Current sense resistor selectable from 0.1 to 1k in decades.
d.
Connection to DUT through shielded cable- four terminals.
A double-sided printed circuit board is designed with all the standard and
necessary precautions to reduce noise and errors. Figure 3.8 shows the photograph of the
developed instrument solar cell impedance analyzer. In Figure 3.9 the interior of the
solar cell impedance analyzer is shown. The raw signals from the power amplifier are fed
to high-speed data acquisition card.

3.2.2.3 High-speed data acquisition card (NI5112)
High-speed data acquisition card is programmed to measure voltage across the

DUT at channel 1 and current through DUT, by measuring voltage across sense resistor at
channel 2. It has two channels, which sample signal simultaneously at 100MS/s in real
time mode and 2.5GS/s for continuous signal in random interleaved sampling mode. The
onboard 16MB memory per channel helps in continuous acquisition of data. The 3dB
bandwidth of data acquisition card is 100MHz
The voltage is measured over a range varying from 25mV to 25V, which is
software selectable with 8-bit resolution. In the solar cell impedance analyzer 25mV
ranges are used and can measure a voltage as low as 200V, with an accuracy of 2.5%.
The input impedance is software selectable 1M or 50 range with AC or DC coupling.
The AC coupling eliminates DC component in the signal. The 3dB frequency bandwidth
of 1.1Hz / 11Hz to 100MHz suits the requirement of solar cell impedance analyzer. The
card is provided with necessary driver software, which is used in the custom-built
program. This card is chosen as it measures AC voltage, current and phase angle in the
presence of DC voltage and current with good accuracy.
3.2.2.4 Testing of hardware
The power amplifier is tested for its frequency response characteristics at different
bias voltages. Figure 3.10 shows the block diagram of the test setup. It consists of a DC
power supply (APLAB 0 to +30V, 2A), AC/DC signal source (Instek programmable
arbitrary function generator), oscilloscope (Tektronix TDS220), precision resistor of 1

(+ 0.5% tolerance). The output voltage across device under test is measured by giving a
constant AC voltage of 20mV (in presence of 0.2V DC bias voltage) by varying
frequency from 10Hz to 1MHz. The magnitude and phase of the impedance over a wide
band of frequency are measured and shown in Figure 3.11. Figure 3.12 shows (for better
clarity) the deviation of the impedance of a standard resistor from (1 +j0). It is observed
that the power amplifier has a flat response from 50Hz to 50kHz range. Beyond this, the
deviation in impedance measurement is large. Below 50Hz, the deviation in real and
imaginary part of impedance is around 5% and at 1MHz, the real impedance deviates
around 30%. The response of the power amplifier is poor and the bandwidth is smaller
than required. To overcome this a novel technique called software range extender (which
virtually enhances the amplifier bandwidth from 50kHz to 1MHz) is developed, as a part
of this research work and the same is implemented as a procedure of internal calibration.
Apart from getting the benefit of virtual range extension form internal calibration, the
errors that occur due to ageing of components and temperature changes, can be removed.
The details of software range extender or internal calibration are presented in
Section 3.2.5.
3.2.3
Software
Most of the advance features of the instrument are implemented through software.
The software is written in graphical language LABVIEW 6i. LABVIEW together with
National Instruments hardware such as high-speed data acquisition and arbitrary function
generator cards allow to create virtual instrument, which uses personal computer platform
and latest internet technology thus making the measurements easy and automated.
LABVIEW is easy to use, fast to develop; has good graphical user interface (GUI) and
graphical source code. This makes it modular, easy to develop, easy to upgrade and debug
and common applications can be built and reused in different modules as well. In
addition, this is compatible with most of the operating systems such as Microsoft
window, Linux, Sun micro system, etc. In addition the third party software like MS
Excel, WORD, ACROBAT, HTML, MATLAB, and C can be used with LABVIEW.
Hence, LAWVIEW with National Instruments cards is selected to develop the solar cell
impedance analyzer to measure solar cell AC parameters.
The raw signals are fed to high-speed data acquisition card and the fundamental signal
is extracted by eliminating noise and harmonics using software. This facility reduces the
hardware complexity and cost. The following advance features are incorporated in the
instrument.
o
o
o
o
o
Measurement is automated
Computes the impedance parameters of DUT and display data online in
graphical form
Stores test specifications and measured data
Offline data processing is possible
Internal calibration to reduce error and virtual extension of hardware range
possible
Total 250 subroutines are developed which include potentiostat, frequency response
analyzer, defining test specifications, save test set-up, save test, etc for sub-modules. The
overall flow-chart (main module) indicating the operation and working of the solar cell
impedance analyzer is shown in Figure 3.13. It interconnects all the sub-modules. The
graphical user interface (GUI) of main module (Front panel) of solar cell impedance
analyzer is shown in Figure 3.14.
In the front panel of the solar cell impedance analyzer the login, help and exit keys are
highlighted. On click of login key, the instrument goes into login procedure, where user
has to enter user identification and password to use the instrument. Figure 3.15 shows the
flow diagram of login subroutine and Figure 3.16 shows GUI of the login module. On
login, the main control panel of the instrument pops up as shown in Figure 3.17 where the
help, offline, test specifications, select test, save test and exit keys are highlighted. On a
click, the user can get into online help to use the instrument. The Offline` subroutine,
flow chart is shown in Figure 3.18, which provides a facility to retrieve the test data
stored in the data bank, process it and to take a hard copy. Figure 3.19 shows the snapshot
of the Offline GUI.
A
ENTER USER
NAME
CHANGE
PASSWORD
ENTER NEW
PASSWORD
ENTER
PRESENT
PASSWORD
RETURN
Figure 3.16: Login GUI
Figure 3.17: Main control panel
SELECT
FILE NAME
PLOT GRAPH
DISPLAY DATA
AND GRAPH
PRINT GRAPH
PRINT TABLE
RETURN
Figure 3.18: Flow chart for Offline Process
Figure 3.19: Snap shot of the Offline GUI
The test specifications have a provision to define test specifications and save it. In
Figures 3.20 (a) and (b), flow diagrams of select test specifications with save and define
test specifications are shown. The following are the inputs that the user needs to key-in to
define test specifications as shown in Figure 3.21.
AC signal wave shape
Sine / Triangle / Square
AC signal amplitude
10 mV (1mV -- 100mV)
Frequency range
o Starting
Minimum
10 Hz
o Ending
Maximum
1 MHz
Number of points
10 (min) to 50 (max) (log sweep)
Number of test samples
1 (min) to 20 (Max). At each frequency
DC bias voltages
+ 2.5V (can be set in steps of 0.05V)
Current Sense resistor
0.1 /1 /10/ 100/ 1000 can be set
On completion of this procedure, the system is programmed to make an internal

self-calibration. It is explained in
detailed later. Figure 3.22 shows
SELECT TEST SPEC
the flow diagram of internal
calibration subroutine, which is

interlinked with sense resistor
selected
through
the GUI of internal calibration.

completion
of
internal
calibration, the instrument is

ready for measurement.
SELECT
EXISTING TEST
SPECIFICATION
ENTER TEST
NAME
micro-
controller. Figure 3.23, shows
On
SELECT TEST NAME
RETURN
RETURN
Figure 3.20 (a): Flow diagram of Selecting the

test specifications
D E F IN E T E S T S P E C
ENTER START
FREQ UENCY
ENTER END
FREQUENCY
SELECT
NUMBER OF
P O IN T /D E C A D E
SELECT
NUMBER OF
SAM PLES FO R
A V E R A G IN G
SELECT SENSE
R E A S IS T O R
VALUE
SELECT
W AVEFO RM
TYPE
RETURN
Figure 3.20 (b): Flow chart for Defining test specifications
Figure 3.21: Snap shot of the Define test specifications
In addition, the instrument is programmed to save the test and measured data along
with the results and remarks. Figure 3.24
shows the GUI to save test. Here the user
can review the test specifications and
INTERNAL CALIBRATION
G
SET DC VALUES
IN NI5401
remarks. The details on the events, test

references, etc., can be keyed in. This
information will be printed in the results
sheet
subsequently.
DEFINE CALIBRATION
TEST PROCEDURE
SELECT SENSE
RESISTOR AND
CALIBRATION RELAYS
Potentiostat
subroutine pops up, where the DC bias

voltage is applied, and the actual voltage
across the device under test is measured
RETURN
Figure 3.22: Flow diagram of Internal

calibration,
on-line along with the current through it.

Figure 3.25 shows a snapshot of Potentiostat GUI. This is displayed in real time and the
average value of multiple measurements is stored in a file. The resolution of voltage and
current measurement is set at this stage.
On proceeding to next step the Frequency response analyzer GUI pops up, which
is the main, and most complex subroutine. Flow chart of FRA subroutine is shown in
Figure 3.26. It is programmed to provide an internal delay of 30s before starting the test
after applying DC bias voltage (as shown in Figure 3.27). This is done to ensure that the
system attains steady state, which reduces error due to transients. Figure 3.28 shows a
snapshot of frequency response analyzer GUI, which is programmed to test automatically
as defined in the test specifications. The specified signal (AC+DC) is applied to the
instrument through the arbitrary function generator card at pre-calculated frequency
points. The high-speed data acquisition card measures the AC voltage across the device
and AC current (in form of voltage drop across sense resistor) through the device.
Figure 3.29 shows part of the source code for the measurement and processing of the
signals. From the acquired data, harmonic noise and residual noise are removed and the
peak-to-peak values of AC voltage, current are estimated along with phase relation
between voltage and current. The real and imaginary parts of the impedance are
calculated and stored in the file on-line. The history of the measurement and events are
also recorded in the file. Figure 3.30 shows snapshot of typical data file stored containing
test specifications and results. The instrument is programmed to display the data online in
the form of an impedance spectrum (in complex plane) as shown in Figure 3.28 and Bode
plots of impedance (real and imaginary part, verses frequency) are shown in Figure 3.31.
Apart from these main subroutines there are other subroutines, which are critical and
function in the background. They are, calculation of frequency points, data storage,
calculation of impedance parameters from measured data, error correction from internal
calibration procedure, etc.
Figure 3.23: Internal calibration GUI
Figure 3.24: snap shot of the Save test GUI
Figure 3.25: Potentiostat to apply DC bias to DUT (GUI)
S e le c t D C
m e a s u re m e n t
ra n g e fo r
N I5 1 1 2
S e t s e rie s
re s is ta n c e
v a lu e
S e le c t D C
c o u p lin g
N I5 1 1 2
Channel 1
o f N I5 1 1 2
Channel 2
o f N I5 1 1 2
M e a s u re
D C V a lu e
M e a s u re D C
V a lu e
D iv id e b y
sense
r e s is t o r v a lu e
S t o r e D C v a lu e
a n d d i s p la y
S t a r t in g o f
Test
L
Figure 3.26 (a)
Generate the frequency from

arbitrary function generator
NI5401
J
AC Measurement Start
DC Blocking
(Coupling)
Channel 1
DC Blocking
(Coupling)
Channel 2
Extract fundamental
signal
Channel 1
Extract fundamental
signal
Channel 2
Measure Peak-Peak
Value
Measure Peak-Peak
Value
Measure
Frequency
Select
waveform
Measure phase angle

between two signals
BB
Figure 3.26 (b)
Channel 1
Display
Channel 2
Display
BB
Check if
number of
samples are
over
Yes
Find average of the measured
parameters
Calculate Z
Real Z & Imaginary Z
Yes
If
Calibration
Mode
Store
data
Calibration file
in
No
Apply correction
Store data in file
Display on-line
CC
Figure 3.26 (c)
No
K
Apply Next
Frequency
Is the
frequency the
end of
N
L
Ye
Stop the Test
Return
Figure 3.26 (d)
Figure 3.26: Flow diagram for Data acquisition and online plotting
Figure 3.27: GUI of the Frequency response analyzer (Warming up)
Impedance
spectrum
Figure 3.28: GUI of the Frequency response analyzer (Test under progress) with online display of impedance spectrum
Figure 3.29: Part of Source code in graphical language (LABVIEW-6i) for Frequency Response analyzer
Figure 3.30: Typical data file saved after test.
Bode plot
Figure 3.31: GUI of the Frequency response analyzer (Test under progress) with online display of bode plot
The flow diagram for RS232 communication and help menu are shown in
Figure 3.32. RS232 subroutine configures RS232 port such as setting BAUD rate, parity,
number of bit etc. This should be compatible to the microcontroller to have a proper
communication and control action. The help menu opens an acrobat format file, which
consists of instruction to use instrument, procedure for testing, etc.
RS232
COMMUNICATION
HELP
CONFIGURE
RS232 PORT
WRITE DATA
TO RS232
PORT
OPEN ACROBAT
HELP FILE
RETURN
RETURN
Figure 3.32: Flow chart of RS232 communication and Help
Setting AC
signal to zero
Arbitrary function
generator virtual
module
Figure 3.33:Source code of Exit
Setting DC bias
voltage to zero
In file Exit.vi, the arbitrary function generator is disabled and exits, which
ensures safe operation and avoid accidental damage of the device under test. Figure 3.33,
shows the source code of the exit panel
3.2.3.1 Testing of software
The software is tested by a closed loop test. The output of the arbitrary function
generator card is fed to both the channels of the high-speed data acquisition card, which
simulates a condition where the voltage and current of the DUT are equal (gives an
impedance of (1 + j0)) . The measurement is carried out with different test
specifications over wide range of frequencies. Figure 3.34 shows the impedance spectrum
obtained during software testing. It is observed that the impedance spectrum is a dot on
real axis at unity, as would be expected for equal AC current and voltage input.
Figure 3.34: Impedance Spectrum of software close loop test
3.2.4
Techniques employed to reduce noise and errors
The most important feature of this instrument is the noise and error reduction
techniques applied to get high quality and accurate measurement. Noise may be inherent
or picked up from external sources, which introduces error. Additionally errors in the
instrument are introduced due to temperature variations, deviation in component values,
hardware / software limitations, and non-linear characteristics of the devices. Each of
these sources of noise and errors have been identified and are either avoided or
compensated in the software.
As a primary step, the following care is taken in the hardware design of the instrument.
Hardware
a) Shielding and guarding of low signals to reduce error due to capacitive coupled
noise
b) In the printed circuit board design a star ground is used to reduce the errors due to
ground loops
c) The circuit is designed with a differential amplifier to reduce error due to common
mode noise and ground loop noise
d) Power supply decoupling filters are used to reduce the error due to conducted
noise
e) Four-probe technique is employed for the measurement of voltage and current to
reduce errors due to resistance and inductance of connecting cables
f) Non-inductive, precision sense resistors with good tolerance (+ 0.05%) are used to
reduce errors due to temperature change and aging.
g) The path of low level signal is reduced and confined to the instrument as far as
possible to get higher signal to noise ratio.
Software
a) Harmonics are eliminated in the measurement through software to reduce errors

due to harmonics
b) Instrument is programmed to start measurement after 30 seconds of the
application of bias voltage and signal to the DUT. This ensures that the errors due
to transients are eliminated, as sufficient time is given for the device to reach
steady state
c) The DC bias voltage is removed before measurement (software programmable) to
improve the resolution of AC signal measurement
d) The instrument is provided with a facility to calibrate internally, which is
programmed to execute automatically. This reduces errors due to temperature
change, ageing, and device response. A detailed description of this feature is
explained later as this is a very important feature that enhances the accuracy of
instrument and extends its frequency range
e) Software is written such that multiple measurements and average values can be
recorded.
3.2.5
Software range extender and Internal calibration
This procedure of internal calibration does three things. i) The magnitude and
phase errors due to the response of the power amplifier is compensated so that its
frequency range is virtually extended; ii) it compensates for change in values of
components due to change in temperature and ageing; and iii) any specific type of noise
injected from the environment is taken out. After implementing the above, measurements
are made on an externally connected 1, non-inductive resistor and it is shown in
Figure 3.35. They are compared with the value measured software extension (refer
Figure 3.11), and found that the frequency range of the instrument is increased from
50KHz to 1M Hz, about 1.5 decades, which is extremely difficult with hardware methods.
The instrument is programmed to go for internal calibration, whenever the
instrument is switched ON or if the test specifications (especially frequency range and
number of point) are changed. In internal calibration mode, a precision, non-inductive
resistor (1 + 0.05%) is used internally as the DUT and the external device is isolated.
The current sense resistor of 1 is automatically selected and calibration in progress is
indicated on the front panel of the solar cell impedance analyzer. The measurement is
carried out on the precision 1 resistor over the specified frequency range with the
specified number of points. From the measured values of voltage, current and phase, real
and imaginary parts of the impedance are calculated over the selected range of
frequencies for which source code is shown in Figure 3.36. Figures 3.37 and 3.38 show
the source code for internal calibration. The measured impedance is subtracted online
from (1+j0) and the deviation is generated which is saved in a file Calibration.xls as
shown in Figure 3.37. Subsequently during the measurement, the deviation is subtracted
from the measured impedance at each frequency on-line as shown in Figure 3.38. As
mentioned earlier the software extender or internal calibration virtually extended the
frequency range from 50kHz to 1MHz on the higher side and 50Hz to 10Hz on the lower
side, which is essential requirement for measuring the solar cell AC parameters. Hence
this is a powerful feature in this instrument and not reported by any other researchers.
This technique has extended frequency range of the instrument; otherwise it requires a
wide band power amplifier. This feature is called a software frequency range extender
which permits the use of simple and low cost amplifiers for higher end applications. This
technique removes amplitude and phase errors caused due to the amplifier frequency
response.
Figure 3.36: Source code to calculate impedance from measured value
Computes Real and

Imaginary part of
impedance
Source code shown
in Figure 3.30
Figure 3.35: Measured value of 1 over a wide range of frequency with internal calibration
Measured data
Computes Real and
Imaginary part of
impedance
Source code shown
in Figure 3.30
Error at particular
frequency taken
from calibration file
Measurement of DC
values
Figure 3.38: Source code to eliminate error in actual measurement
3.2.6
Calibration of solar cell impedance analyzer
The solar cell impedance analyzer is calibrated end-to-end using passive electrical
components. A passive resistor (1.012 + 0.05%) and a passive capacitor (1.10F+0.5%)
connected in parallel as shown in Figure 3.39, is used as DUT and the measurements are
carried out with a DC bias of 0.2V and frequency range varying from 10Hz to 1MHz with
50 points distributed uniformly on a logarithmic scale. Table 3.4 shows the measured data
and Figure 3.40 shows the impedance
spectrum plotted from the measured
data. It is observed from Figure 3.40, the
network
semicircle
impedance
spectrum
indicating
is
single
time
constant; with a resistor and a capacitor

connected
in
parallel.
From
the
Figure 3.39: Calibration network with

precision resistor and
capacitor in parallel
impedance spectrum and the measured data, the values of circuit parameters are
calculated and are shown in Table 3.5. The maximum deviation observed between the
measured and actual values is + 3%.
Table 3.4: Measured Data for calibration network shown in Figure 3.38
Test Date: Sunday, February 22, 2004
Test Time: 5:02:08 PM
Waveform Type: SINE
Start Frequency: 10.00 Hz
End Frequency: 1000000.00 Hz
Amplitude: 0.01 V
DC Bias Voltage: 0.20 V
No of Points: 50
No of Samples: 30
Sense Resistor: 1Ohms
1 parallel with 1F at room temperature
DC Voltage: 0.2092 V
DC Current: 0.2082 A
Frequency (Hz)
Real Z (Ohm)
-Imaginary Z (Ohm)
10
1.059307
7.47E-05
12.648
1.05892
9.44E-05
15.998
1.058644
0.000119
20.236
1.058142
0.000151
IZI (Ohm)
1.059307
1.05892
1.058644
1.058142
25.595
32.375
40.949
51.794
65.513
82.865
104.81
132.57
167.68
212.1
268.27
339.32
429.19
542.86
686.64
868.51
1098.5
1389.5
1757.5
2223
2811.8
3556.5
4498.5
5689.9
7196.9
9103.1
11514
14564
18421
23300
29470
37276
47149
59636
75432
95409
120680
152640
193070
244210
308880
390690
494170
625060
790600
1000000
1.058036
1.057928
1.057649
1.057451
1.057334
1.056961
1.056786
1.056786
1.056674
1.056613
1.056499
1.05637
1.056285
1.055942
1.05566
1.055576
1.055325
1.055181
1.054746
1.053559
1.052718
1.057267
1.056279
1.054697
1.05495
1.051412
1.048112
1.047626
1.036686
1.029125
1.010508
0.989239
0.952076
0.898908
0.825468
0.729957
0.615204
0.49105
0.372721
0.269227
0.184981
0.124137
0.080864
0.051874
0.033284
0.021036
0.00019
0.000241
0.000304
0.000385
0.000487
0.000615
0.000777
0.000983
0.001243
0.001572
0.001988
0.002513
0.003178
0.004016
0.005076
0.006419
0.008113
0.010259
0.012961
0.016341
0.020626
0.026442
0.033376
0.042076
0.053361
0.067019
0.084378
0.107437
0.133246
0.168199
0.207513
0.258831
0.314488
0.37532
0.436509
0.487391
0.521605
0.527549
0.504941
0.460029
0.401869
0.340239
0.281117
0.228604
0.184545
0.147609
1.058036
1.057928
1.057649
1.057451
1.057334
1.056961
1.056787
1.056787
1.056674
1.056614
1.056501
1.056373
1.05629
1.055949
1.055672
1.055595
1.055356
1.055231
1.054825
1.053685
1.05292
1.057597
1.056807
1.055536
1.056299
1.053546
1.051503
1.053121
1.045214
1.042779
1.031595
1.02254
1.002672
0.974115
0.933776
0.877717
0.806566
0.720721
0.627604
0.53302
0.442398
0.362178
0.292516
0.234416
0.187523
0.149101
Figure 3.40: Impedance spectrum of network shown in Figure 3.39
Table 3.5: Comparison between actual measured values of network components
Actual Measured % Deviation

1.0589
-3.74
Capacitance (F) 1.1
4.45
Resistance () 1.012 1.0570
A non-inductive resistor is used for internal calibration. Generally, the device
under test is capacitive, resistive, or inductive or a combination of these. The op-amp
response may depend on the type of load. As this effect is not reflected in the calibration.
A slightly larger error in measurement is possible at higher frequencies (>1MHz),
limiting the high frequency response. Even with this limitation, the measurement upto 1
MHz has deviation less than 5%.
3.2.7
Repeatability
In order to investigate the reliability of experimental data, same experiments are

repeated on different days of the calendar. Figure 3.41 (a), (b) and (c), shows the
impedance spectra of calibration resistor-capacitor network measured on different days
over a period of four to five months. It is observed that they are in good agreement with
each other. Thus, instrument has shown excellent repeatability in measurement.
September 2003
Figure 3.41 (a)
November 2003
Figure 3.41 (b)
January 2004
Figure 3.41 (c)

Figure 3.41: Impedance spectrum of the network measured at different time
3.2.8
Summary
Impedance spectroscopy technique is well suited for measuring the AC parameters

of non-linear devices such as solar cells, as it measures all AC parameters
assuming piecewise linearity.
The measurement setup developed using Solartron ECI and FRA has certain
limitations to measure solar cell AC parameters.
The personal computer based solar cell impedance analyzer has overcome all the
limitation of earlier measurement setups and it measured solar cell AC parameters
with deviation less than + 4%.
With this instrument, the AC parameters of different types of solar cells namely
silicon and GaAs/Ge solar cells are measured at different temperatures. The obtained
results are presented in detail in the next chapter
Figure 3.11: Impedance of I non- inductive precision resistor measured at different

frequencies
Figure 3.12: Deviation from (1+j0) at different frequencies (response of amplifier)
Cable
termination
box
Figure 3.8 (a): Solar cell impedance analyzer
GUI
Solar cell
impedance
analyzer
Solar
cell
Figure 3.8 (b): Solar cell impedance analyzer in the measurement set-up
Power
supply with
torridial
transformer
Power amplifier
card (shielded)
DUT port
Figure 3.9: Photograph showing internal details of solar cell impedance analyzer
Figure 3.10: Block diagram of set-up to test hardware
S T AR T
LO G IN
SELECT
TEST SPEC
D E FIN E
TEST SPEC
O F FL IN E
PLOT
HELP
NO
C H AN G E IN
TEST SPEC
Y ES
G
IN T E R N AL S E L F C AL IB R AT IO N
S AV E T E S T N AM E
S T AR T
TEST
Figure 3.13: Flow chart of Main module
Figure 3.14: Front panel of the instrument
STOP
Channel 1
Channel 2
Figure 3.6: Block diagram of the solar cell impedance analyzer.
Figure 3.7: Circuit diagram of the power amplifier with control circuit
Chapter 4
MEASUREMENTS
It has been shown in the previous chapters that AC parameters of a solar cell are
very important in design of photovoltaic system. These parameters are highly dependent
on operating point and temperature. Hence, it is necessary to create a database of AC
parameters for commonly used solar cells such as silicon and GaAs/Ge. Also it is shown
in Chapter 3, the impedance spectroscopy technique gives maximum information and
suitable for measuring AC parameters of nonlinear devices such as solar cells. Hence
using impedance spectroscopy technique the AC parameters of GaAs/Ge solar cell are
measured under dark and illumination at 298K with Solartran ECI and FRA. The obtained
results are presented in the first part of this chapter. The AC parameters of GaAs/Ge and
silicon BSRF solar cells under dark at different temperatures are measured both in reverse
and forward bias conditions using the solar cell impedance analyzer. The results are
presented in the second part of this chapter. The AC parameters of silicon solar cell
(widely used for terrestrial applications) under dark at 22oC are also measured, which
measured values are used for the design and analysis of switching shunt voltage
regulators in Chapter 5.
4.1
Solar Cell Measurements under dark and illumination

Generally the solar cells are under illumination during operation. Hence, AC
parameters of GaAs/Ge solar cell (40mm x 20mm) are measured at different cell voltages
under illumination and are compared with the dark measurements made on the same solar
cell under the same conditions to evaluate a relation between them. The static (DC)
characteristics of GaAs/Ge solar cell at room temperature (298K) are presented in
Table 4.1.
Table 4.1: Static parameters of GaAs/Ge (20mm x 40mm) cell at 298K

Open circuit
voltage
Voc (V)
1.02
Short circuit
current
Isc (mA)
255
Maximum power
point voltage Vmp
(V)
0.87
Maximum power
point current Imp
(mA)
232
The solar cell acts as a source when it is under illumination because the current
flows out of the solar cell to the external circuit. The solar cell in dark acts as load
because the solar cell is biased externally using a suitable voltage source and the current
flows into the solar cell. The equivalent circuit of a solar cell under illumination and dark
are shown in Figure 4.1. The voltage across solar cell diode (Vji) under illumination is,
Vji = Vt + I L r
(4.1)
Vt = Vji I L r
(4.2)
Similarly the voltage across solar cell diode (Vjd) under dark is,
Vjd = Vt + I d r
(4.3)
Vt = Vjd + I d r
(4.4)
I L = I ph I d
(4.5)
and,
By equating the Equations 4.2 and 4.4 and substituting for IL from Equation 4.5, the
voltage across solar cell diode under illumination can be written in terms of voltage
across solar cell diode under dark as,
Vji = Vjd + I ph r
(4.6)
where,
Vt
Id
Vjd
Vji
r
IL
Iph
Solar cell terminal voltage

Solar cell current
Solar cell diode voltage under dark
Solar cell diode voltage under illumination
Solar cell series resistance
Load current
Photo-induced current
From Equations 4.6 it is seen that for a given cell terminal voltage (Vt), the
junction voltages are different under dark and illumination conditions, because of the
voltage drop across series resistance (r).
Vji Vt Vjd
(4.7)
It is observed that under illumination the current sourced by the solar cell is larger
than the current drawn from the external source under dark condition. In dark the solar
cell draw only diode current, but in illumination the photo-generated current is sourced
out. Hence large DC bias current has to be factored out for measurement under
illumination.
(a)
Illumination
(b)
Dark
Figure 4.1: Solar cell equivalent circuit
4.1.1
Experimentation
Figure 4.2 shows the schematic of the measurement setup. The solar cell under
test, reference solar cell and thermocouple probe are mounted on the same brass fixture.
Water is circulated through the brass block, using chiller to maintain the cell temperature
constant. The solar cell under test is connected to measurement setup consisting of
Solartron ECI and FRA using four probes. Reference solar cell is connected to a milliammeter to measure its short circuit current. The brass block with both solar cells and
thermocouple probe are place under sun simulator (ORIEL) and is illuminated. The
intensity of illumination is set to AM0 by adjusting the simulator lamp current and also
by measuring the short circuit current (255mA at 298K) of the calibrated reference solar
cell. The intensity and temperature are maintained constant throughout the
experimentation.
The measurements on GaAs/Ge solar cell are carried out at different bias voltages
starting from 0.6V to 0.93V at 299K. An AC signal of amplitude 25 mV of varying
frequency from 1Hz to 60kHz is applied to the solar cell. Since the DC current under
illumination is large, the AC signal amplitude is increased from 10mV to 25mV in order
to improve its signal strength. Measurements are repeated on the same solar cell under
dark at the same cell terminal voltages as done under illumination. The cell is completely
covered with black box in dark measurements.
Figure 4.2: Schematic of the measure set-up used to measured solar cell AC
parameters in illumination
4.1.2
Results and Discussion
The impedance spectra of GaAs/Ge solar cell at different terminal voltages

(0.6 V to 0.93 V) under illumination and dark conditions are shown in Figure 4.3 and 4.4
respectively.
a)
c)
b)
d)
e)
f)
g)
h)
i)
j)
60kHz
60kHz
k)
l)
a)
c)
b)
d)
e)
g)
f)
h)
60kHz
i)
j)
60kHz
k)
The following observations are made from the Figures 4.3 and 4.4.
1) At all bias voltages, the cell impedance spectra (either in dark or under
illumination) are nearly a semicircle indicating that the solar cell has only one
time constant consisting of an 'Rp' and a 'Cp' in parallel.
2) In some cases the spectra stops before reaching real axis near origin (high
frequency end) as shown in Figures 4.3 (j) and (k) and 4.4 (k) and (l). It shows
that the measurements at higher frequencies (>60kHz) are necessary to complete
the spectrum. In such cases the impedance spectrum has to be extrapolated upto
real axis to calculate cell parameters. The accuracy suffers due to extrapolation.
3) It is observed that the impedance spectra under illumination are distorted below
0.8V (Refer Figures 4.3 (a) to (e)) particularly at low frequencies. As described
earlier, the solar cell DC current (Iph) is large under illumination and most of the
current flows out at lower terminal voltages. Hence at terminal voltages below
0.8V, the cell capacitance and hence its AC current is small compared to DC
current when illuminated and the potentiostat selects a small current measuring
resistance (0.1) (depending on the total cell current (Iac+Idc)) sacrificing the
accuracy of AC current measurement. This introduces large errors in the
impedance spectrum, especially at low frequencies where capacitive reactance is
high. Unlike this, in dark measurements Iph is zero and the DC current at a given
terminal voltage is small compared to DC current under illumination, which
allows potentiostat to use higher current measuring resistance (1k) improving
the accuracy of AC measurement, which allows impedance measurements at
lower terminal voltages and frequencies.
From the impedance spectra the cell capacitance and cell resistance at different
cell terminal voltages are calculated and presented in Table 4.2. Figure 4.5 shows the
variation of cell capacitance measured in dark and illumination conditions for
different cell terminal voltages (Vt). It is observed that the cell capacitance measured
under illumination is higher than that measured under dark as the solar cell diode
voltage (Vji) under illumination is greater, than that of cell diode voltage (Vjd) under
dark for a given cell terminal voltage (refer Equation 4.6). In Figure 4.6 the cell
capacitance values measured under dark and illumination are compared for the same
cell diode voltages. It is observed that the deviation between the cell capacitance
values measured is within +5%. This apparent difference in cell capacitance between
illumination and dark condition is due to change in the diode voltage for a given cell
terminal voltage.
Table 4.2: Measured cell capacitance and resistance at different bias voltages (both dark
and illumination)
Cell Voltage (V)
Capacitance (F)
Cell Resistance ()
Dark
Illumination
Dark
Illumination
0.6
0.65
0.7
0.73
0.75
0.77
0.8
0.83
0.85
0.87
0.9
0.93
0.95
1.4961
1.5694
1.6237
1.6661
1.6849
1.71
1.7561
1.8118
1.8425
1.883
1.9609
2.0956
2.2435
1.74176
1.7988
1.8324
1.8614
1.9634
2.1736
2.608
1255.02
616.4
276.52
173.44
126.49
92.011
52.643
30.528
20.6566
13.679
6.867
3.1193
1.6765
33.217
20.063
11.3062
7.4651
4.7403
2.3736
0.9316
Figure 4.5: Variation of cell (GaAs/Ge) capacitance with cell terminal voltage in dark
and illumination
Figure 4.6: Variation of cell capacitance with cell diode voltage in dark and illumination
The variation of cell resistance with cell terminal voltage is shown in Figure 4.7.
It shows that the cell resistance measured in dark is greater than that of illumination
condition at all cell terminal voltages. This difference is due to variation in cell diode
voltage for same cell terminal voltage in dark and illumination. Figure 4.8 shows the
variation of cell resistance with cell diode voltage (Vj) for both dark and illumination
conditions. They are in good agreement with each other.
Figure 4.7: Variation of cell resistance with different cell terminal voltage both in dark
and illumination
Figure 4.8: Variation of cell resistance with cell diode voltage in dark and
illumination
The solar cell diode voltage (Vj) under illumination for different cell terminal
voltages can be calculated using Equation 4.6, illuminated and dark I-V characteristics.
From this the cell capacitance under illumination is estimated. In Figure 4.9 the cell
capacitance directly measured under illumination is compared with the cell capacitance
(under illumination) calculated from the dark data. They are in good agreement with each
other.
Figure 4.9: Comparison of cell capacitance measured in illumination and derived form
dark data at different cell voltage
4.1.3
1)
Summary on illumination and dark measurements
The measurements made in dark and illumination show that the cell
capacitance and resistance do not depend on the condition of measurement i.e,
either dark or illumination
2)
Measurements in dark are accurate and simple compared to illumination
3)
From application point, the cell parameters under illumination at different cell
terminal voltages are important, which can be computed from the dark data
with reasonably good accuracy.
4)
The measurements at high frequency (>60 kHz) are necessary to complete the
impedance spectrum in order to calculate cell parameters accurately.
5)
Hence, the solar cell impedance analyzer is used to measure GaAs/Ge and
Silicon (BSFR) solar cell AC parameters at different temperatures under dark.
The solar cell impedance analyzer (presented in Chapter 3) developed as a
part of this research work, can measure upto 1MHz.
In previous section the AC parameters of GaAs/Ge (40mm x 20mm) solar cell are
measured under dark and illumination condition at room temperature. It revealed that the
measurements made under dark are quite accurate than under illumination. Hence, further
measurements are done using solar cell impedance analyzer on both space solar cells
such as GaAs/Ge and silicon BSFR solar cells and terrestrial silicon solar cells.
4.2
Measurements on Different Types of Solar Cells
The GaAs/Ge and Silicon BSFR solar cells are used in space where, the
temperature of the solar panel varies from 190K to 325K. As mentioned in Chapter 1
(section 1.2.2.3.2), increase in cell temperature causes a small increase in the cell short
circuit current (Isc) but significant decrease in the cell open circuit voltage (Voc)
[Fahrendruch A et. al.]. Thus variation in temperature for a given operating voltage
results in change of the operating point and consequently in its AC parameters. Hence, in
the present investigations, the AC parameters of GaAs/Ge and Silicon BSFR solar cells
are measured at different temperatures.
In general, several solar cells are connected in series and parallel combination to
achieve required power at the desired operating voltage. In such cases if the solar panel is
operated under partial shadow the cells in shadow shift their operating point from forward
to reverse bias as shown in Figure 4.10. The cells under reverse bias act as load on
illuminated cells [R J Pinkerton (2000)]. Baron W R et al, (1987) reported that GaAs/Ge
solar cells shows a limited reverse voltage capability when compared to the silicon solar
cells. Iles P A et al (1990) reported that GaAs/Ge solar cells degrade when exposed to
high reverse currents. Hence, it is a common practice to use bypass diodes across solar
cells in an array. The bypass diode limits the reverse bias voltage around 0.6V at room
temperature and at extreme temperature it may vary from 1.1V to 0.4V. To have a
thorough understanding of solar cell characteristics, the AC parameters of the solar cells
are to be measured both in forward and reverse bias. Hence, the measurements are carried
out on GaAs/Ge and silicon BSFR solar cells of size 40mm*20mm at different
temperatures from 198K to 348K in steps of 25K and by varying the bias voltage of
GaAs/Ge solar cell from 1.15V to +1.15V and of Silicon BSFR solar cell from 0.95V
to +0.79V under dark. The measurements are also made around the maximum power
voltage as most of the time the solar cells are operated at this point.
Figure 4.10: Operating point of a cell in shadow
4.2.1
Experimentation
Figure 4.11 shows the measurement set-up, which, consists of a solar cell
impedance analyzer, a temperature controlled hot and cold chamber (Climate 540h70/3)
and a thermocouple based digital thermometer and the solar cell under test. The solar cell
is mounted on a brass fixture, which is kept in a hot and cold chamber. Nitrogen gas is
purged into the chamber to avoid condensation at low temperatures. A thermocouple is
also mounted close to the solar cell on the fixture as shown in Figure 4.12. The
temperature of the hot and cold chamber is maintained constant with in 0.5K of the set
value by a computer controlled PID temperature controller. The solar cell inside the
chamber is under dark condition. The solar cell is connected to the solar cell impedance
analyzer using shielded cables and four probes are used as described in Chapter 3
(Section 3.2.2.1(a)).
Figure 4.11: Set-up to measure solar cell AC parameters
Thermocouple
GaAs/Ge
Solar
Cell
Figure 4.12: Brass mounting block with solar cell and

thermocouple
The chamber temperature is set to a temperature say 190K and the measurements
are started after the solar cell attains the desired temperature and stabilizes. At low
temperature even the bias current affects solar cell temperature. Hence, the cell
temperature is maintained within 1K of the set value throughout the experiment. At a
given bias voltage the solar cell impedance analyzer applies a 10mV sinusoidal signal
over a wide range of frequencies (10Hz to 1MHz) and measures real and imaginary parts
of the impedance. The solar cell impedance analyzer plots the impedance spectrum and
using these AC parameters of the solar cell are calculated as described in Chapter 3
(Section 3.2.2.4). By keeping the temperature constant, the measurements are carried out
at different bias voltages both in forward and reverse bias. The measurement procedure is
repeated at different temperatures.
4.2.2
Measurement on GaAs/Ge Solar Cell
The AC parameters of GaAs/Ge (40mm*20mm) solar cell are measured under

dark at different temperatures ranging from 198K to 348K in steps of 25K over a wide
range of bias voltages (reverse and forward) using solar cell impedance analyzer. The
measured data are presented in this section. In the first part of this section the data
measured at room temperature (298K) is presented along with the detailed discussion on
the obtained results. In the latter part the result obtained with variation of temperature, is
presented.
The static characteristics of the GaAs/Ge (40mm*20mm) solar cell at 298K are
shown in Table 4.1. AC parameters of GaAs/Ge solar cells are measured under dark
condition at different bias voltages (-1.05V to +1V) and at 298K. Figures 4.13(a) to (g)
show the impedance spectra drawn from the measured data under reverse bias and
Similarly
Figure 4.14(a) to (g) show the impedance spectra with forward bias at the
same temperature 298K.
a)
a)
b)
d)
e)
g)
f)
h)
a)
c)
b)
d)
e)
f)
464.1kHz
g)
h)
The following observations are made from the impedance spectra presented in Figures
4.13 and 4.14
1) At all bias voltages the impedance spectra are single semicircle indicating that
the solar cell has only one time constant consisting of an Rp and a Cp in
parallel.
2) Impedance spectra of GaAs/Ge solar cell obtained at reverse bias voltages
(refer Figures 4.13 (a) to (g)) are perfect semicircle.
3) Beyond 'Vmp' (0.87V) of the cell (Figure 4.14 (f), (g)) the spectra is slightly
flattened semicircle. This indicates that distributed parameter modeling is
necessary to accurately describe the spectrum [Abdelhalim Zekry, et al.
(1996)] rather than lumped 'RC' model.
4) Close to Voc the impedance spectra (Figure 4.14 (g) and (h)) are away from
the origin indicating that the cell has series resistance (r).
5) In Figure 4.14(h) the impedance spectra extends into the positive imaginary
axis showing the cells have inductance in series with resistance (r).
From the impedance spectra, the cell capacitance and resistances are calculated at
different bias voltages and are shown in Table 4.3. It is observed that cell capacitance
(Cp) varies from 0.833F to 2.018F whereas the cell resistance (Rp) varies from
10054.67 to 1.35 for the same variation in bias voltage from 1.05V at +1V. This
variation is quite large.
4.2.2.1.1
The variation of cell capacitance with cell voltage is shown in Figure 4.15. It is
observed that the cell capacitance varies nonlinearly with cell voltage.
Table 4.3: AC parameters of GaAs/Ge solar cell at different cell bias voltages
Cell Voltage
(V)
-1.05
-1
-0.97
-0.95
-0.9
-0.85
-0.8
-0.75
-0.7
-0.65
-0.6
-0.5
-0.4
-0.3
-0.2
0.5
0.55
0.6
0.65
0.7
0.75
0.8
0.83
0.85
0.87
0.9
0.93
0.95
Cell Capacitance
(F)
0.833
0.838
0.844
0.847
0.857
0.867
0.877
0.884
0.895
0.906
0.921
0.944
0.967
0.996
1.03
1.254
1.262
1.327
1.368
1.423
1.497
1.556
1.6
1.635
1.672
1.819
1.886
1.975
Cell resistance
()
1054.67
1208.66
1305.56
1378.17
1595.59
1856.49
2188.82
2605.13
3121.77
3805.04
4676.3
7392.1
12626.7
23961.01
52766.84
5285.28
2791.09
1372.5
641.933
285.55
124.59
50.62
28.27
18.8
12.08
5.82
2.54
1.35
Figure 4.15:Variation in cell capacitance with voltage at 248 K
At voltages well below 'Vmp' and the reverse bias one would expect that the cell
capacitance is due to charge separation or transition layer. This capacitance follows the
equation given below as described in Chapter 1
Ct =
dQ
B
=
dVd (Vo Vd )1 / m
(4.8)
and
1
V
V
= mo md
m
Cp B
B
(4.9)
The value of 'm' varies depending on the type of junction; for abrupt junction, the
value of m is 2, and for linear graded junction value of m is 3. To determine the
nature of 'p-n' junction a plot of 1/Cpm for m= 2, 3 and 4 was made as shown in
Figure 4.16, curves 1 to 3. It may be observed that curve 1 is a straight line indicating that
m=2 and the solar cell junction is an abrupt junction.

The constants (B) and junction voltage (Vo) are calculated theoretically from the
doping levels. The doping concentrations are taken from manufactures data as below.
NA
ND
Ni
r
A
1 1024 /m3
5 1023 /m3
1.79 1012 /m3 at 25C
13.1
8 10-4 m2
The theoretically calculated value of Vo is 1.34 V and B is 1.41*10-6.

In Figure 4.17, a graph of 1/Cp2 at 298 K is replotted. To have a better accuracy a
straight line is fit around to the measured of 1/Cp2 values using ORIGIN software. The
details are given in the inset of Figure 4.17. From the slope and the 'Y' intercept of the
line the calculated value of B is 1.34 x 10-6 and Vo is 1.53 V. The difference between
theoretical values of 'Vo' and 'B' from the experimental values is probably due to variation
of NA, ND and Ni from batch to batch of the solar cells.
Figure 4.16: 1/Cpm verses cell voltage of GaAs/Ge solar cell at 298 K
Figure 4.17: 1/Cp2 verses cell voltage of GaAs/Ge solar cell at 298 K
It is observed from Figure 4.17 that around open circuit voltage the slope of plot
1/Cp2 increases and deviates from the straight line. This is due to existence of diffusion
capacitance beyond Vmp.
4.2.2.1.2
Cell Parallel Resistance (Rp)
The other important AC parameter of a solar cell is its parallel resistance (Rp),
which is a parallel combination of dynamic resistance (Rd) and shunt resistance (Rt)
[Refer Chapter-1 section 1.2.32]. In general the value of Rt is very large compared to
Rd around and beyond 'Vmp' making Rp approximately equal to Rd. However, near
short circuit region Rd becomes larger and Rp is nearly equal to Rt. From the
impedance spectra, the cell parallel resistance Rp is calculated for both forward and
reverse bias voltages (Typical calculations are shown in Chapter 3 section 3.2.2.4), which
are shown in Table 4.3 along with the cell capacitance. Figure 4.18 shows the variation in
Rp with bias voltage. It is observed that in forward bias voltage the cell resistance
decreases with increasing in cell voltage, where as in reverse bias the cell resistance
increases as the voltage tend to zero.
4.2.2.1.3
Cell Series Resistance (r) and Cell Inductance (L)
It is observed from Figure 4.14(h) at 298K the impedance spectrum is shifted

along the positive real axis away from the origin. As discussed in Chapter 3, the offset
from the origin indicates the presence of series resistance (r) and its value is 0.15.. At
cell voltages closer to Vmp and beyond, the dynamic resistance Rp is comparable to
series resistance (r) and hence, is observable in the plots. At voltages closer to short
circuit Rp is very large compared to r and hence 'r' is not observable. Also it is
observed from Figure 4.14(h) that the impedance spectrum extends to positive imaginary
axis at higher frequencies showing that the cell has some inductance in series with r. At
the point of crossing the real imaginary axis the inductive reactance (L) is equal to
series resistance (r), which is 0.06. Therefore inductance (L) is given by,
L=
r
r
=
2f
(4.10)
Where, f is frequency at crossover point (464.1kHz (measured)). The value of inductance

is calculated as 0.051H.
Figure 4.18: Variation in cell resistance with voltage at 248 K
The measurements are made at different cell temperatures ranging from 198K to
398K insteps of 25K. The measurements spanned over 7 temperatures between 198K to
348K and 61 bias points between -1.15V to + 1.15V amounting to 181 impedance
spectra being drawn, amounting to 9000 measurements just on GaAs/Ge solar cell. This
mammoth data are analyzed to get cell capacitance (Cp), dynamic parallel resistance (Rp)
and cell series resistance (r) at each bias point. Due to constraints of space and
complexity, only a part of the data that represent the behavior of the cell in general are
presented in this section. Figures 4.19 to 4.24 show the impedance spectra in reverse bias
and Figures 4.25 to 4.30 shows impedance spectra in forward bias at different
temperatures.
b)
b)
c)
d)
Figure 4.19: Impedance spectra of GaAs/Ge solar cell at different bias at190K
e)
f)
g)
h)
a)
d)
b)
d)
e)
g)
f)
h)
a)
e)
b)
d)
e)
g)
f)
h)
a)
f)
b)
d)
e)
g)
f)
h)
a)
g)
b)
d)
e)
g)
f)
h)
a)
c)
b)
d)
e)
g)
f)
h)
a)
c)
b)
d)
e)
g)
f)
h)
a)
c)
b)
d)
e)
g)
f)
h)
a)
c)
b)
d)
e)
g)
f)
h)
a)
c)
b)
d)
a)
c)
b)
d)
e)
f)
g)
a)
c)
b)
d)
e)
g)
f)
h)
From Figure 4.25 to 4.30, it is observed that at all temperatures and bias voltages the
spectra are nearly a semicircle indicating that the solar cell has only one time constant
consisting of an 'Rp' and a 'Cp' in parallel. Also following observations are made,
1)
Impedance spectra of GaAs/Ge solar cell in reverse bias voltage at all

temperatures (refer Figures 4.19 to 4.24) are semicircles.
2)
Beyond 'Vmp' of the cell the spectra is slightly flattened semicircle. This
indicates that distributed parameter modeling is necessary to accurately
describe the spectrum [Abdelhalim Zekry, et al. (1996)] rather than lumped
'RC' model.
3)
Close to Voc the impedance spectra are away from the origin indicating the
cell has series resistance (r). The resistance value is 0.15 at all temperatures.
4.2.2.2.1
Cell Capacitance
different temperatures both in forward and reverse bias. Cell capacitance (Cp) at different
cell temperatures and bias voltages are tabulated in Table 4.4 and are plotted in Figure
4.31. The variation in cell capacitance with cell voltage is re-plotted at temperatures 198,
298 and 348K for better clarity and is shown in Figure 4.32.
Table 4.4: Cell Capacitance at different cell voltage and temperature
Cell Voltage
(V)
-1.15
-1.13
-1.1
-1.07
-1.05
-1.03
-1
-0.97
-0.95
-0.93
-0.9
-0.87
Cell Capacitance (F)

198 K
0.8131
0.8162
0.821
0.8317
0.8323
0.8403
0.8463
0.847
223 K
0.804
0.8085
0.8118
0.8161
0.8161
0.82
0.8268
0.8339
0.8375
248 K
273 K
298 K
0.818
0.8224
0.8276
0.832
0.838
0.8419
0.8459
0.8497
0.833
0.8272
0.8352
0.836
0.8396
0.8453
0.838
0.844
0.847
0.857
323 K
348 K
0.817
0.8454
0.8519
0.855
0.8657
0.8584
0.8699
0.8761
-0.85
-0.83
-0.8
-0.77
-0.75
-0.7
-0.65
-0.6
-0.5
-0.4
-0.3
-0.26
-0.2
-0.16
0.45
0.47
0.5
0.53
0.55
0.57
0.6
0.63
0.65
0.67
0.7
0.73
0.75
0.77
0.8
0.83
0.85
0.87
0.9
0.93
0.95
0.97
1
1.01
1.02
1.03
1.04
1.05
1.07
1.1
1.11
1.12
1.13
1.14
1.15
0.8566
0.8481
0.8537
0.8609
0.867
0.8728
0.876
0.857
0.8636
0.87
0.877
0.8825
0.8853
0.8947
0.871
0.8762
0.8874
0.8726
0.8873
0.8946
0.904
0.9262
0.9553
0.8803
0.8899
0.884
0.895
0.906
0.921
0.944
0.967
0.996
0.8964
0.9075
0.8824
0.8853
0.8917
0.8985
0.9029
0.913
0.9287
0.9543
0.9804
1.0138
0.9401
0.9624
0.9824
1.017
1.03
1.0274
1.0454
0.912
0.9345
0.9625
0.9847
0.9842
1.005
1.27
1.34
1.254
1.275
1.289
1.262
1.331
1.307
1.352
1.327
1.348
1.371
1.405
1.368
1.403
1.398
1.444
1.423
1.457
1.465
1.497
1.52
1.556
1.6
1.635
1.672
1.819
1.886
1.975
1.627
1.676
1.735
1.872
1.925
1.581
1.627
1.67
1.768
1.37
1.355
1.494
1.45
1.5
1.54
1.55
1.59
1.65
1.516
1.6969
1.74
1.834
1.833
1.88
1.982
2.044
2.115
2.175
2.468
2.55
1.904
1.96
2.272
1.6001
1.506
1.537
1.597
1.644
1.705
1.779
1.862
1.863
1.899
2
2.1
1.604
1.645
1.769
1.802
1.86
2.018
Figure 4.31: Variation of solar cell capacitance with voltage at different temperatures
Figure 4.32: Variation of cell capacitance with voltage at different temperature
It is observed that for a given cell voltage in forward bias, the cell capacitance
decreases as the cell temperature decreases. However, the variation in the cell capacitance
with cell temperature in reverse bias is very small and tends to same value around 1V
irrespective of temperature. As discussed earlier, the cell capacitance is mainly due to
transition capacitance throughout except at voltages close to Voc.
Figure 4.33 shows the variation of cell capacitance at maximum power voltage for
different cell temperatures. The variation of cell capacitance with temperature is marginal
and falls within the measurement error (5%). This is an important observation made in
the present investigation and it is very useful for a system designer.
Figure 4.33: Capacitance of GaAs/Ge solar cell at Vmp for different temperatures
4.2.2.2.2 Cell Resistance
From the impedance spectra, the cell parallel resistances (Rp) are calculated at
different cell voltages and at different temperatures. The obtained results are tabulated in
Table 4.5. Figure 4.34 shows the variation of cell resistance with cell voltage at different
temperatures.
Table 4.5: Cell resistance at different cell voltage and temperature
Cell Voltage
(V)
-1.15
-1.13
-1.1
-1.07
-1.05
-1.03
-1
-0.97
-0.95
-0.93
-0.9
-0.87
-0.85
Cell resistance ()
198 K
1741.14
1829.9
1973.5
223 K
248 K
273 K
298 K
1315.22
1054.67
3638.28
1267.11
1367.33
1441.46
1522.75
1522.75
1614
1802.65
2017.62
2140.85
1502.01
1627.08
1713.47
1823.96
1985.5
1182.125
1243.8
1351.13
1462.7
1550.65
1647.95
1745.4
4384.25
2579.21
2310.21
2096.34
2352.05
2382
2729.17
3109.69
323 K
348 K
1106.12
1595.59
1061.49
1109.08
1204.49
1278.148
1465.49
1856.49
1620.4
1208.66
1305.56
1378.17
1282.67
1409.79
1554.87
-0.83
-0.8
-0.77
-0.75
-0.7
-0.65
-0.6
-0.5
-0.4
-0.3
-0.26
-0.2
-0.16
0.45
0.47
0.5
0.53
0.55
0.57
0.6
0.63
0.65
0.67
0.7
0.73
0.75
0.77
0.8
0.83
0.85
0.87
0.9
0.93
0.95
0.97
1
1.01
1.02
1.03
1.04
1.05
1.07
1.1
1.11
1.12
1.13
1.14
1.15
5221.25
2991.91
2722.28
2453.62
2188.82
1901.8
6321.45
7827.2
3600.48
4279.64
5299.34
3235.91
3826.12
4715.8
5781.61
9145.84
15608.32
2917.13
3468.5
2605.13
3121.77
3805.04
4676.3
7392.1
12626.7
23961.01
2381.81
2879.12
1580.46
1741.47
1924.93
2064.5
2469.37
4324.13
6842.58
11841.98
22610.15
3731.73
5819.92
9857.81
18676.89
52766.84
50714.18
40030.43
5252.56
8347.72
14255.11
27233.62
39981.18
98386.53
1669
1985.26
5285.28
2117.28
876.96
2791.09
1075.89
442.32
3238.59
1372.5
517.7
210.12
1563.242
641.933
231.31
91
602.2
285.55
104.51
38.01
124.59
43.68
50.62
28.27
18.8
12.08
5.82
2.54
1.35
16.31
8.33
5.1
2.96
1.28
14.25
9.15
4.4
2.01
904.65
914.53
820.73
387.45
448.9
234.25
165.64
111.57
60.18
157.1
60.336
29.02
10.546
19.964
12.53
5.974
4.535
3.42
2.58
1.844
1.3
6.406
3.64
1.6921
21.103
155.81
107.9
60
32.83
21.65
13.65
6.47
4.8
3.65
2.67
1.82
53.98
19.743
9.83
5.82
3.24
1.19
Figure 4.34: Cell resistance at different cell voltages and cell temperatures
It is observed from Figure 4.34 that the cell resistance decreases with temperature
at a given cell voltage and peaks near short circuit. For large junction currents i.e. near
open circuit condition, Rd is given by [Millman J et al. (1979)],
Rd
VT
Id
(4.11)
where,
Id Solar cell junction current (by experiment)
Diode or Ideality factor
Using Equation 4.11 and the measured solar cell junction current the diode factor is
calculated at the maximum power point voltage and also at different temperatures. The
details are given in the next subsection.
4.2.2.2.3
Diode Factor and Parallel Resistance at Vmp
The diode factor () is calculated at different cell temperatures at the maximum

power point voltage (Vmp), which is shown in Figure 4.35 along with Rd. varies
from 3 to 1.5 as the temperature varies from 198K to 348K and Rd decreases from 30
to around 5 as temperature is increased from 198K to 348K.
Figure 4.35: Variation of diode factor and cell resistance with cell temperature at Vmp
4.2.2.3 Summary
1)
The cell capacitance and resistance are nonlinear and vary with bias voltage
and temperature
2)
The p-n junction of GaAs/Ge solar cell is an abrupt junction
3)
The cell capacitance increases with cell voltage and is mainly due to transition
capacitance at all cell bias voltages
4)
Cell resistance in forward bias decreases with increasing cell bias voltage,
where as in reverse bias cell resistance increases, as cell voltage reaches zero
volts.
5)
Cell capacitance in Forward bias increases with temperature at any bias

voltage, whereas cell resistance decreases with increase in temperature at any
bias voltage.
6)
In reverse bias cell capacitance is insensitive to variation in temperature.
7)
Cell capacitance at Vmp is constant at different temperatures, whereas at

Vmp the cell resistance and diode factor decreases with increase in
temperatures.
8)
At all temperatures cell series resistance is 0.15 and cell series inductance is
0.051H.
4.2.3
AC Parameters Silicon BSFR Solar Cell
The AC parameters of silicon BSFR (40mm x 20mm) solar cell is measured under
dark at different temperatures ranging from 198K to 348K in steps of 25K over a wide
range of bias voltages (reverse and forward) using solar cell impedance analyzer. The
measured data is presented in this section. In the first part of this section the data
measured under room temperature (298K) is presented with the detailed discussion. In the
subsequent part the variation of solar cell AC parameters with temperature is discussed.
The static characteristics of silicon BSFR (40mm x 20mm) solar cell at 298K are
shown in Table 4.6.
Table 4.6: Static parameters of Silicon (BSFR) (20mm x 40mm) cell at 298K
Voc
0.60V
Isc
330 mA
Vmp
0.51V
Imp
300 mA
AC parameters of silicon BSFR solar cells are measured under dark condition at
different bias voltages (-0.53 to +0.58V) and at 298K. Figures 436 (a) to (g) show the
impedance spectra drawn from the measured data under reverse bias and Figure 4.37 (a)
to (g) show the impedance spectra with forward bias at 298K.
a)
b)
c)
d)
e)
f)
g)
a)
c)
b)
d)
Figure 4.37: Impedance spectra of Silicon (BSFR) solar cell at different forward bias voltage at 298 K
e)
f)
g)
Figure 4.37: Impedance spectra of Silicon (BSFR) solar cell at different forward bias voltage at 298K
The following observations are made from the impedance spectra presented in
Figures 4.36 and 4.37
1) At all bias voltages the impedance spectra are single semicircle indicating single
time constant indicating that the solar cell has only one time constant consisting of
an Rp and a Cp in parallel.
2) Impedance spectra of BSFR silicon cell in reverse bias voltage (refer
Figures 4.36 (a) to (g)) are semicircle.
3) In forward bias, at 0.4V (Figure 4.37 (b)) and at 0.45V (Figure 4.37 (c)) the
impedance spectra deviate from semicircle to a straight line with a slope of 45 to
50 degrees at high frequencies.
4) At Vmp and very near to Voc the impedance spectra (Figure 4.37 (e), (f) and
(g)) are again semicircle.
5) Close to Voc the impedance spectra (Figure 4.6 (e), (f) and (g)) are shifted from
the origin indicating the cell has series resistance (r).
6) In Figure 4.37 (e), (f) and (g) the impedance spectra extend into the positive
imaginary axis showing the cells have inductance in series with resistance (r).
different bias voltages and are shown in Table 4.7. It is observed that cell capacitance
(Cp) varies from 0.0801F to 304.43F whereas the cell resistance (Rp) varies from
27.24k to 0.21 for variation in bias voltage from 0.53V at +0.58V. This variation is
quite large.
4.2.3.1.1
The variation of cell capacitance with cell voltage is plotted on a semi log scale,
which is shown in Figure 4.38. It is observed that the variation of cell capacitance has
two regions (a and b) with a very small slope in region a and avery large slope in
region b. The variation in region bis linear on log scale.
Table 4.7: AC parameters of silicon (BSFR) at different cell bias voltages
Voltage (V) Cell capacitance (F)
-0.53
0.0801
-0.50
0.0862
-0.47
0.0871
-0.45
0.0879
-0.43
0.0887
-0.40
0.0901
-0.30
0.0947
-0.20
0.1002
-0.10
0.1066
0.20
0.1362
0.25
0.1456
0.30
0.1612
0.35
0.1953
0.40
0.4820
0.43
1.2230
0.45
2.4530
0.47
5.8940
0.50
18.91
0.53
53.31
0.55
109.02
0.57
222.81
0.58
304.43
Cell resistance ()
27247
20587
20515
20432
20238
19993
19333
18683
17181
1072.84
608.5
315.258
127.75
33.43
12.773
7.299
4.48
2.125
1.0166
0.5489
0.2814
0.2064
Figure 4.38: Cell capacitance verses cell voltage (Silicon BSFR solar cell) at 298 K
At voltages well below 'Vmp' and reverse bias one would expect the cell
capacitance to be due to charge separation or transition layer. This capacitance follows
the Equation 1.5
Ct
dQ
dVd
B
(Vo Vd )1 / m
(4.12)
and
1
V
1
= mo m Vd
m
Cp B
B
(4.2)
The value of 'm' varies depending on the type of junction; for abrupt junction the
value of m is 2, and for linear graded junction the value of m is 3. To determine the
nature of 'p-n' junction a plot of 1/Cpm for different values of m (2, 3 and 4) are plotted
as shown in Figure 4.39. It is observed that the curve with m equal to two has a smaller
standard deviation (2.41) indicating its closeness to a straight line. Hence, the silicon
BSFR solar cell junction is an abrupt junction.
The constants (B) and junction voltage (Vo) can be calculated from doping
constants. The doping concentrations of the solar cell taken from the manufacturers data
and are shown below.
NA
ND
Ni
r
A
1 x 1021 /m3
1 x 1025 /m3
1.45 x 1016 /m3 at 25C
11.9 for silicon semiconductor
8 x 10-4 m2
Using Equations 1.6, 1.7 and 1.8, the values of Vo (0.7V) and B (8x10-8) are calculated
theoretically. In Figure 4.39, for the plot 1/Cp2 verses cell bias voltage the straight line is
fit around the negative bias voltage using ORIGIN software for better accuracy. From the
slope (-121.72x012) and the 'Y' intercept (74.831x1012) of the line the value of B
(1/B2 = slope) and Vo (Y intercept = Vo/B2) are calculated and they are B= is 9x10-8 and
Vo=0.62V. The theoretical and experimental values of B and Vo are in good agreement
with each other.
Figure 4.39: Variation of 1/Cpm at different cell voltages for BSFR silicon solar cells
As mentioned earlier, the capacitance in region b (refer Figure 4.38) varies

exponentially (linear in log scale) with cell voltage. From Equation 1.13, the diffusion
capacitance (Cd) can be written as,
Vd
Cd =
Io e VT
2VT
(4.14)
and
I 2.3
ln(Cd ) = ln o +
Vd
2VT VT
Equation
4.15
represents
straight-line
(4.15)
equation
with
slope
of
(1/(VT)), where diode factor and VT is thermal voltage (kT/q = 26mV at 298K).
This shows that the cell capacitance in the region b is entirely due to diffusion
capacitance. From the slope (36.38) of the straight line (region b) the value of diode
factor () is calculated as 2.1, which is close to value of 2 reported by Millman et al.,
(1972).
4.2.3.1.2
Cell Resistance (Rp)
As discussed in Chapter 1 the cell resistance (Rp) is a parallel combination of

shunt resistance (Rt) and the dynamic resistance (Rd). The shunt resistance can be
calculated from the static characteristics of the solar cell. Rt is normally large when
compared to Rd near open circuit region and hence, the cell resistance (Rp) is
approximately equal to the dynamic resistance (Rd). But, near the short circuit region Rd
becomes very large and Rp is nearly equal to Rt. The cell resistance measured at
different bias voltages are shown in Table 4.7 along with the measured cell capacitance
values. Figure 4.40 shows the variation of Rp with bias voltage. It is observed that the
variation in cell resistance in reverse bias is very small, but in forward bias the cell
resistance decreases with cell voltage.
Figure 4.40: Variation in cell resistance with different bias voltages
4.2.3.1.3
Cell Series Resistance (r) and Cell Inductance (L)
It is observed from Figure 4.37(g) the impedance spectrum is shifted along the
positive real axis away form the origin. As discussed in Chapter 1, the offset from the
origin indicates the presence of a series resistance (r) and its value is 0.06. At cell
voltages closer to Vmp and beyond, the cell resistance (Rp) (0.2) is comparable and
hence, series resistance is observable in the impedance spectrum. At voltage closer to
short circuit or reverse bias Rp (1.07k) is very large compared to r and hence r is
not observable in the impedance spectrum. Also it is observed from Figure 4.37(g) the
impedance spectrum extends to positive imaginary axis at higher frequencies showing

that the cell has some inductance in series with r. At the point of crossing the real
imaginary axis the inductive reactance (L) is equal to series resistance (r), which is
0.06. Therefore inductance (L) is given by,
L=
r
r
=
2f
(4.16)
Where, f is frequency at crossover point = 34.10kHz (measured)

The value of inductance is calculated as 0.28H.
4.2.3.1.4
Deviation of Impedance Spectrum
It is observed from Figure 4.37(b) and (c) that the impedance spectrum at higher
frequencies has deviated form semicircle and tends to a straight line. Theoretically at
frequencies (>>1), cell capacitance (diffusion capacitance (Cd)) is given by, (refer
Chapter 1)
1
1 2
Cd =
R do 2
(4.17)
and its reactance Xc is

1
1
2 2
Xc =
= R do
C d

(4.18)
and dynamic resistance Rd is given by,

1
2 2
R d = R do

(4.19)
Since the reactance is equal to resistance (as per Equations 4.18 and 4.19), the locus will
be a straight line at 45o on the impedance plane. Hence, deviation of impedance spectrum
from semi circle to a straight line indicates that the cell capacitance and resistance are
afunction of frequency at these bias voltages and beyond (>>1).
The mean carrier lifetime () is calculated from Rd and Cd in diffusion region
[Millman , et al.],
R d Cd
2
(4.20)
where Rd and Cd are the cell resistance and capacitance respectively close to open
circuit.
From the measured data (refer Table 4.2) the mean carrier lifetime is calculated using
Equation 4.20 as 62.7s. In Figure 4.41 the impedance spectrum at 0.45 V is redrawn
showing the frequency at point a and point b. At point a (f= 7.55kHz) and is
2.97. Similarly at point b (f= 23.9kHz) and is 9.41, which is far greater than 1.
Hence, beyond point b impedance spectrum is a straight line with an angle of 45o
Figure 4.41: Impedance spectrum deviated from semicircle
Similarly the measurements are made at different cell temperatures ranging from
198K to 398K insteps of 25K.
The measurements spanned 7 temperatures between 198K to 348K and 55 bias
points between -0.9V to +0.9V amounting to 161 impedance spectra being drawn,
amounting to 8800 measurements just on silicon BSFR solar cell. This mammoth data is
analyzed to get cell capacitance (Cp), dynamic parallel resistance (Rp) and cell series
resistance (r) at each bias voltage. Due to constraint of space and complexity only a part
of the data is presented that represents the behavior of the cell in general. Data showing a
particularly interesting behavior is included.
Figures 4.42 to 4.46 show the impedance spectra in reverse bias and Figures 4.47
to 4.52 shows impedance spectra in forward bias at different temperatures.
a)
b)
c)
d)
e)
f)
g)
h)
a)
b)
c)
d)
Figure 4.43: Impedance spectra of Silicon (BSFR) solar cell at different bias voltage at 223K
e)
f)
g)
h)
a)
c)
b)
d)
e)
f)
g)
h)
a)
b)
d)
c)
e)
f)
g)
h)
a)
b)
c)
d)
e)
g)
f)
h)
a)
c)
b)
d)
e)
f)
g)
h)
a)
c)
b)
d)
e)
f)
g)
h)
a)
c)
b)
d)
e)
f)
g)
h)
a)
c)
b)
d)
e)
f)
g)
h)
a)
c)
b)
d)
e)
f)
g)
h)
a)
c)
b)
d)
f)
e)
g)
h)
Figures 4.42 to 4.52
1) At all temperatures in reverse bias voltages (refer Figure 4.42 to 4.46), the
impedance spectra are nearly a semicircle indicating that the solar cell has only
one time constant consisting of an Rp and a Cp
2) In forward bias at most of the bias voltages the impedance spectra are
semicircular. But, in a small region of bias
(0.35 to 0.7V depending on
temperature) the high frequency end of the spectrum deviates to a straight line
with a slope of 45 to 50 degree, similar to the observations made at 298K.
3) The impedance spectra (Figures 4.47(h), 4.48(h), 4.49(h), 4.50(h), 4.51(h),
4.52(h)) returns to near semicircular shape close to Voc. This is because <<1.
4) Closer to 'Voc' the cell series resistance is comparable to the dynamic resistance as
spectra are shifted in the real axis (refer Figures 4.47(h), 4.48(h), 4.49(h), 4.50(h),
4.51(h), 4.52(h)). At these biases the spectra extends to the positive imaginary axis
showing that the cell has inductance in series with resistance 'r'. The value of
inductance is around 0.28H and is nearly constant with temperature as expected.
The impedance spectra at different temperatures and at 0.5V bias voltage are
compared in Figure 4.53. It is observed that at 198K impedance spectra is a perfect semi
circle. As the temperature increases towards 273K the impedance spectrum tends to a
straight line deviating from semi circle at higher frequencies. Further as temperature
increases to 323K, the impedance spectrum is again a semi circle, but extends to the
positive imaginary axis indicating the presence of inductance and shift of the impedance
spectrum from the origin on positive real axis indicates existence of series resistance.
a)
b)
c)
d)
Figure 4.53: Impedance spectra of Silicon (BSFR) solar cell at 0.5V and different temperatures
4.2.3.2.1
Cell Capacitance
different temperatures both in forward and reverse bias. Cell capacitance (Cp) at different
cell temperatures and bias voltages are tabulated in Table 4.8 and plotted in Figure 4.54.
The variation in cell capacitance with cell voltage is re-plotted on semi log scale at
temperatures 198, 298 and 348K for better clarity in Figure 4.55.
Table 4.8: Silicon (BSFR) Cell capacitance at different cell voltage and temperature
Voltage
(V)
-0.95
-0.93
-0.90
-0.87
-0.85
-0.83
-0.80
-0.77
-0.75
-0.73
-0.70
-0.67
-0.65
-0.63
-0.60
-0.55
-0.53
-0.50
-0.47
-0.45
-0.43
-0.40
-0.35
-0.30
-0.25
-0.20
-0.10
0.15
0.20
0.25
0.27
0.30
198 K
0.0671
0.0687
0.0691
0.0699
0.0700
0.0705
0.0713
0.0721
0.0726
0.0726
0.0735
0.0744
0.0747
0.0752
0.0763
223 K
Cell Capacitance (F)

248 K
273 K
298 K
0.0651
0.0676
0.0714
0.0713
0.0728
0.0723
0.0722
0.0744
0.0754
0.0759
0.0770
0.0778
0.0774
0.0737
0.0748
0.0763
0.0774
0.0796
0.0837
0.0834
0.0855
0.0878
0.0873
0.0919
0.0918
0.0947
0.0933
0.0969
0.1002
0.1066
0.0815
348 K
0.0770
0.0784
0.0789
0.0795
0.0805
0.0821
0.0801
0.0862
0.0871
0.0879
0.0887
0.0901
0.0803
323 K
0.0838
0.0827
0.1351
0.1362
0.1456
0.1434
0.1612
0.0776
0.0897
0.0925
0.0952
0.0966
0.1003
0.1039
0.1102
0.1480
0.1688
0.1855
0.2393
0.1546
0.200
0.466
0.7707
1.6986
0.33
0.35
0.37
0.40
0.43
0.45
0.47
0.50
0.53
0.55
0.57
0.58
0.60
0.63
0.65
0.67
0.69
0.70
0.73
0.74
0.75
0.77
0.79
0.1422
0.1545
0.1953
0.1421
0.1525
0.1411
0.1519
0.1509
0.1649
0.1705
0.1645
0.1705
0.1839
0.1942
0.1672
0.1765
0.2017
0.2730
0.4124
1.0663
0.1730
0.1984
0.2374
0.3233
0.9867
3.717
8.207
19.35
0.4820
1.2230
2.4530
5.8940
18.91
53.31
109.02
222.81
304.43
0.1822
0.1971
0.2261
0.2858
0.2979
0.6840
1.8813
5.2228
0.8938
5.0230
25.606
137.84
212.17
4.3719
18.109
97.669
97.669
301.53
0.3882
0.8163
1.6643
4.2710
12.570
25.723
50.885
101.87
337.85
4.433
8.411
15.59
41.30
104.33
183.74
301.38
65.77
224.03
19.253
60.173
236.09
It is observed that in the reverse bias the capacitance variation is nominal with
temperature and in the forward bias, especially close to 'Voc', ln(Cp) is linear with respect
to cell voltage. As discussed earlier, beyond 0.6Voc the cell capacitance is due to
diffusion capacitance and below it is due to transition capacitance. At a given bias voltage
the cell capacitance increases with cell temperature. From the slope of the ln(Cp) graph
(diffusion capacitance region) the diode factor is calculated as described earlier (section
4.3.1.2) at different temperatures and it is shown in Figure 4.56. It is observed that the
diode factor increases from 1.8 to 2.4 with cell temperature, which can be treated as
nearly constant around two over the entire temperature range of measurement.
Figure 4.54: Silicon (BSFR) Cell capacitance at different temperatures
Figure 4.55: Cell capacitance verses cell voltage (Silicon BSFR solar cell)
Figure 4.56: Variation of diode factor with temperature
Figure 4.57: BSFR silicon cell capacitance at the maximum power point for different
temperatures
To understand the AC parameters at the maximum power point, the cell

capacitance as a function of cell temperature at maximum power voltage is plotted in
Figure 4.57. It is observed that the silicon BSFR solar cell capacitance increases with
temperature It is because, the cell capacitance at the maximum power point is mainly due
to diffusion capacitance and is proportional to Id/T (refer Equation 4.14, where
VT=KT/q) [Millman J et. Al (1972)]. At Vmp diode current Id increases exponentially
with temperature T. Hence Cd increases with temperature at Vmp [Sharma S K et al.
(1992)].
4.2.3.2.2
Cell Resistance
From the impedance spectra, the cell parallel resistances (Rp) are calculated at
different cell voltages and at different temperatures. The obtained results are tabulated in
Table 4.9. Figure 4.58 shows the variation of cell resistance with cell voltage at different
temperatures. It is observed that in forward bias, the cell parallel resistance decreases with
increase in cell temperature. But in reverse bias the cell resistance is nearly constant with
bias voltage at all temperatures.
Table 4.9: Cell dynamic resistance at different cell voltage and temperature
Voltage
Silicon (BSFR) solar cell resistance ()
(V)
198 K
223 K
248 K
273 K
298 K
323 K
348 K
-0.95
-0.93
-0.9
-0.87
-0.85
-0.83
-0.8
-0.77
-0.75
-0.73
-0.7
29334
31346
31562
31415
31399
31305
31338
31549
31749
31612
31888
36095
29669
30323
29417
30737
29614
31181
30673
30656
30710
31046
29833
29825
24745
-0.67
-0.65
-0.63
-0.6
-0.55
-0.53
-0.5
-0.47
-0.45
-0.43
-0.4
-0.35
-0.3
-0.25
-0.2
-0.1
0.15
0.2
0.25
0.27
0.3
0.33
0.35
0.37
0.4
0.43
0.45
0.47
0.5
0.53
0.55
0.57
0.58
0.6
0.63
0.65
0.67
0.69
0.7
0.73
0.74
0.75
0.77
0.79
31819
31835
31897
32189
29992
30048
31298
30910
31419
31346
25194
25201
25209
24965
24988
30734
32020
24528
27247
20587
20515
20432
20238
19993
31338
32995
24334
19333
33894
24311
18683
17181
30546
31596
24732
31775
791.75
708.04
781.41
498.59
526.76
274.05
198.04
104.117
43.312
21.207
9.736
496.16
327.83
225.04
327.35 156.68
264.53 101.341
176.85
97.95
57.171
28.114
40.56
12.237
5.1714
2.423
7.1296
1.7439
0.775
0.2025
0.1262
0.7148
0.2574
0.0753
3.547
1.3794
0.6859
0.3203
0.1269
24418
18606
18640
18151
17646
17339
16757
14609
1072.84 562.05
1121.34 608.5 264.07
182.59
690.29 315.258 96.579
44.435
408.33 127.75 24.816
14.28
199.98 33.43 5.6166
107.24 12.773 3.13037
63.477 7.299 2.0559
34.478
4.48
1.2458
12.111 2.125 0.60322
5.0759 1.0166 0.32083
3.0636 0.5489
1.7721 0.2814
0.2064
0.6753
0.2223
489.32
209.07
69.614
41.116
18.45
8.268
5.0828
3.1632
1.7123
0.8299
0.4846
0.2818
Figure 4.58: Silicon (BSFR) cell parallel resistance at different temperatures
The cell resistance at the maximum power point is shown as a function of

temperature in Figure 4.59. It is observed that the cell resistance peaks around 248K. Rd
is given by,
Vmp
VT VT VT
=
Rd =
e
Id
Io
(4.21)
The above equation has three temperature dependent terms, 'VT', 'Vmp' and 'Io'. At 'Vd'
close to 'Vmp', 'Io' is small compared to 'Id' and the variation of 'Io' with temperature can be
neglected. However, exact temperature at which 'Rd' peaks could not be determined
theoretically, but qualitatively it can be recognized that 'Rd' at 'Vmp' should have a peak.
Figure 4.59: Variation of cell parallel resistance (Rp) with cell temperature at Vmp
4.2.3.2.3
Mean Carrier Lifetime
The mean carrier lifetime () is given by [Dhariwal S R et al. (1981)],
R d Cd
2
for << 1
(4.22)
From the measured AC parameters (cell diffusion capacitance Cd and dynamic

resistance Rd at Vmp and beyond); the mean carrier lifetime is calculated using
Equation 4.22 at different cell temperatures and is as shown in Figure 4.60. It is observed
that the mean carrier lifetime increases from 7.4s to 41.2s with increase in temperature
from 198 K to 348 K, which compares well with the literature [Martti Palo Kangas et al.
(2003)].
Figure 4.60: Mean carrier lifetime verses cell temperature for silicon (BSFR) solar cell
4.2.3.3 Summary
(1) The silicon BSFR solar cell capacitance and resistance are nonlinear and vary with
bias voltage and temperature
(2) The p-n junction is an abrupt junction
(3) The cell capacitance increases with cell voltage and the region where the cell
capacitance due to transition and diffusion are distinct.
(4) Cell resistance in Forward bias decreases with increasing cell bias voltage, where as
in reverse bias cell resistance is fairly constant with change in bias voltage.
(5) Cell capacitance in Forward bias increases with temperature at any bias voltage,
whereas cell resistance decreases with increase in temperature at any bias voltage.
(6) In reverse bias cell capacitance is insensitive to variation in temperature.
(7) Cell capacitance at Vmp increases with increase in temperature, whereas cell
resistance at Vmp peaks at 248K.
(8) At all temperatures cell series resistance is 0.06 and cell series inductance is
0.28H.
(9) Variation in diode factor with temperature is small.
(10)
The mean carrier lifetime increases with temperature.
(11)
At frequencies >>1 the impedance spectrum deviates from semicircle to a
straight line with a slope of 45o, indicating the cell capacitance and resistance are a
function of frequency.
4.2.4
Comparison of AC Parameters between GaAs/Ge and Silicon BSFR Solar Cells
The data on the AC parameters of GaAs/Ge and silicon BSFR solar cell are
compared in this section. The cells used are of same size (40mm*20mm). For ease of
understanding the parameters of both cell measured at 298K are compared.
Figure 4.61 shows cell capacitance verses cell voltage (expressed as a percentage
of open circuit voltage of corresponding solar cell) for GaAs/Ge and silicon BSFR
solar cells. Figure 4.62, shows the cell resistance verses cell voltage for both the solar
cells.
1)
It is observed from Figure 4.61, in GaAs/Ge solar cell the variation in cell
capacitance between 1.05V to 0.95V (0.93Voc) is 0.83F to 1.975F, and mainly
due to transition capacitance. In silicon BSFR solar cell variation in cell
capacitance between 0.53V to +0.58V (0.966Voc) is 0.081F to 304.43F. The
most remarkable thing is that in silicon BSFR solar cells transition region and
diffusion region are distinct.
2)
In GaAs/Ge solar cells the transition capacitance is about 10 times that of BSFR
silicon solar cell. This clearly indicates that the junction width in GaAs/Ge solar
cells is very small compared to silicon solar cells.
3)
The capacitance of GaAs/Ge solar cell at 'Vmp' does not vary appreciably with
temperature while that of BSFR silicon solar cell increases from 5F to 50F over
the temperature range of interest.
4)
In the reverse bias capacitance is insensitivity to variation of temperature in both

GaAs/Ge and silicon solar cells.
5)
The parallel resistance in forward bias shows similar trends in all cells; reduces
with increasing temperature and forward bias.
6)
In reverse bias the GaAs/Ge cell resistance decreases with increase of bias varying
from 52766 at -0.2V to 1054 at -1.05V peaking around zero volt. However, for
BSFR silicon solar cells the resistance is fairly insensitive to reverse bias.
Figure 4.61: Comparison of GaAs/Ge and Silicon BSFR solar cells capacitance
Figure 4.62: Comparison of GaAs/Ge and Silicon BSFR solar cells resistance
4.2.5
Measurements on Silicon Solar Cell
The AC parameters of silicon cell used for terrestrial applications (100mm

diameter) are measured using the solar cell impedance analyzer under dark at different
bias voltages and at room temperature (298K). The Static (DC) parameters of silicon
terrestrial solar cell at 298K are given in Table 4.10.
Table 4.10: Static parameters of Silicon terrestrial (100mm diameter) cell at 298 K
Open circuit
voltage
Voc (V)
0.55V
Short circuit
current
Isc (mA)
1.08A
Maximum
power point
voltage Vmp (V)
0.40V
Maximum
power point
current Imp (mA)
2.0A
Figures 4.63(a) to (d) shows the impedance spectra measured at different bias
voltages.
Figure 4.63 (a): Impedance spectrum of Silicon (terrestrial) solar cell at 298K
(b)
(c)
Figure 4.63: Impedance spectra of Silicon (terrestrial) solar cell at different bias voltage
at 298K
(d)
Figure 4.63: Impedance spectra of Silicon (terrestrial) solar cell at different bias voltage
at 298K
Figure 4.63 (a) to (d). They are,
1)
At all bias voltages the impedance spectra are single semi circular indicating
that the solar cell has only one time constant consisting of Rp and Cp in
parallel. It is similar to silicon (BSFR) and GaAs/Ge solar cells.
2)
In forward bias, beyond Vmp and close to open circuit (refer Figure 4.63 (c)
and (d)) the impedance spectra deviates from semi circle to a straight line at
high frequencies. This is similar to that observed in silicon (BSFR) solar cell.
As explained earlier, it is also due to the fact that cell capacitance and
resistance are a function of frequency at higher frequencies (>>1)
3)
The impedance spectrum (refer Figure 4.63(d)) is shifted from origin on real
axis showing the cell series resistance. The value of this cell series resistance
is 0.116.
4)
In Figure 4.63 (d), the impedance spectrum has extended to positive

imaginary axis showing that the cell has inductance in series with resistance
(r). The inductive reactance (XL) is equal to series resistance (0.116) at the
real axis crossing point. The frequency at this point is 95.41kHz and the
inductance value is 0.193H.
From impedance spectra, the cell capacitance at different bias voltages and
temperatures are calculated and tabulated in Table 4.11. In Figure 4.64, the variation of
cell capacitance with cell voltage is plotted. It is observed that the cell capacitance has
two regions a and b, like silicon BSFR solar cell. As discussed earlier the cell
capacitance in region b varies exponentially (linear in Log scale) with cell voltage,
which is attributed to diffusion capacitance. The capacitance in region a is due to
transition capacitance, similar to silicon BSFR solar cell.
Table 4.11: Capacitance at different cell voltages for terrestrial silicon solar cell
Cell Voltage
(V)
-1
-0.8
-0.6
-0.5
-0.4
-0.2
0
0.2
0.3
0.4
0.45
0.5
0.55
Cell capacitance Cp
(F)
1.47
1.58
1.72
1.89
1.91
2.16
2.56
3.31
3.80
5.77
11.3
68.8
124.0
Figure 4.64: Variation of Cell capacitance with cell voltage (terrestrial silicon solar cell)
Table 4.12 shows the cell resistance at different cell bias voltages and
temperatures calculated from impedance spectra. Figure 4.65 shows the variation in cell
parallel resistance with cell voltage is shown. The behaviour is similar to that of BSFR
silicon solar cell.
Table 4.12: Resistance at different cell voltages for terrestrial silicon solar cell
Cell Voltage
(V)
-1
-0.8
-0.6
-0.5
-0.4
-0.2
0
0.2
0.3
0.4
0.45
0.5
0.55
Cell resistance Rp
()
88.3
88.8
90.15
86.49
86.89
85.11
8.66
2.557
0.637
0.2449
0.063
-
Figure 4.65: Variation of cell resistance capacitance with cell voltage

(Terrestrial silicon solar cell)
The experiments are conducted using this solar cell to study the effect of cell AC
parameters on design and performance of shunt switching regulator. The measured cell
AC parameters are used to study the scaling of cell capacitance to that of array. The
details are presented in the next chapter.
4.2.5.1 Summary
In general the terrestrial silicon solar cell behaviour is similar to that of BSFR
silicon solar cell.
The variation in capacitance is similar to that of silicon BSFR solar cell. The
transition and diffusion capacitance are distinct.
On a semi log plot the variation of Cp with voltage is linear.
Parallel resistance in reverse bias is nearly constant
4.2.6
Charge Accumulation Measurement
Often the solar cell is switched from short circuit to an operating point in any
switching voltage regulators. When such switching is done the charge accumulated in the
solar cell is transferred to switch. Under these circumstances what is relevant is the solar
cell capacitance that represents the accumulation of charge. Hence the total charge
accumulated in the solar cell is measured at different operating voltages and then the solar
cell capacitance is estimated. GaAs/Ge solar cell (40mm x 20mm) capacitance is
measured under dark 298K. The measurements are carried out at different bias voltages
ranging from 0.3V to 0.9V in steps of 0.1V and also at 0.87V (maximum power point
voltage) and 0.95V. At each voltage, multiple measurements are made and the average
value of cell charge equivalent capacitance is estimated. Even though the principle of
measurement technique is presented in Chapter 1, the experimentation details are
presented below.
The experimental set-up shown in Figure 4.66 consists of a DC power supply, a

digital multimeter, a digital storage oscilloscope interfaced to a personal computer (PC),
custom-built shunt switch and the solar cell whose capacitance is to be measured. The
solar cell is kept under dark condition and is biased by the DC power supply, as measured
by a digital multimeter (Make: Fluke Model; 111). A pulse generator (Make: Instek) with
a driver circuit is used to switch ON the MOSFET, which shunts the solar cell. The
MOSFET (IRFZ44) from M/s International Rectifier is chosen whose ON resistance is

0.08, which ensures small voltage drop across the MOSFET and voltage across solar
cell is close to zero when shorted. The current through the solar cell is measured by the
voltage drop across the non-inductive precision sense resistor (Rsen) of 1 (+0.05%
tolerance) and acquired through the digital storage oscilloscope (Make: Tektronix, Model:
TDS220). The resistor (R1) limits the power supply current when the electronic switch
(MOSFET) is closed and the blocking diode (D1) blocks the discharge of the solar cell
capacitor through the power supply. The digital storage oscilloscope interfaced to the
personal computer (PC) through RS-232 communication port acquires the transient
current verses time data when the switch is closed. From this data, the solar cell
capacitance (charge equivalent) is estimated / calculated. To minimize error due to noise,
the measurements at a particular voltage are repeated several times and the average value
is taken. In order to reduce errors due to lead resistance and inductance, a shielded coaxial cable of small length is used for connecting the solar cell.
Figure 4.66:Charge accumulation measurement set-up

4.2.6.2 Calibration of experimental set-up
The test set-up is calibrated using passive electrical network simulating solar cell
electrical equivalent as shown in Figure 4.67. Bias voltage from 0.2V to 1V in steps of
0.2V is applied and measurements are carried out. The variation in current with time at
different bias voltages when the electronic switch is closed is measured using an
oscilloscope. Figure 4.68 (a & e) shows the variation of current with time for network 1
at different bias voltages and similarly Figure 4.69 (a to e) shows the variation of current
with time for network 2 at different bias voltages. It is observed that the current peaks to a
finite value in a finite time after the switch is closed. This is due to inductance and
resistance along the discharge path. If the inductance and resistances are zero then the rise
time tends to zero and the peak current tends to infinity. Further current decays as the
charge stored is depleted. However in this measurement the shape, peak value, rise time
and fall time are not important, but the area under the curve, which gives the total charge
stored, is of importance. The area under curve is calculated by numerical integration
using ORIGIN software. With several iterations it is found that the integration time equal
to the time taken by the current to reach 10 % of its peak value, gives good and accurate
estimate of the charge accumulated. From the total charge (Q) accumulated the value of
the capacitor (C) is estimated as,
Cq =
Q
Vd
(4.24)
where Vd is the change in voltage across the cell.

The measured values are
compared with the actual capacitor
values of network 1 and network 2
in
Table
4.13
and
4.14
0.1
+ 0.1%
0.1
+ 0.1%
10k
+ 0.1%
0.1F
+ 1%
10k
+ 0.1%
1F
+ 1%
respectively. It is observed that the

error is more at low capacitor value
(a) Network-1
(b) Network -2
Figure 4.67: Standard network for calibration
and also at low bias voltage since the charge accumulated is small.
Figure 4.68 (a): Variation in current with time for network 1 at different bias voltages
Figure 4.68 (b): Variation in current with time for network 1 at different bias voltages
Figure 4.68 (c): Variation in current with time for network 1 at different bias voltages
Figure 4.68 (d): Variation in current with time for network 1 at different bias voltages
Figure 4.68 (e):Variation in current with time for network 1 at different bias voltages
Figure 4.69 (a): Variation in current with time for network 2 at different bias voltages
Figure 4.69 (b): Variation in current with time for network 2 at different bias voltages
Figure 4.69 (c): Variation in current with time for network 2 at different bias voltages
Figure 4.69 (d):Variation in current with time for network 2 at different bias voltages
Figure 4.69 (e): Variation in current with time for network 2 at different bias voltages

Cell
Voltage
Volt
1
0.8
0.6
0.4
0.2
% Error
Capacitance
Time domain
(F)
Standard Capacitor
Value
(F)
0.117
0.118
0.122
0.127
0.136
0.10
-17
-18
-22
-27
-36

Cell
Voltage
Volt
1
0.8
0.6
0.4
0.2
Capacitance
Time domain
(F)
1.087
1.088
1.09
1.09
1.20
% Error
Standard Capacitor
Value
(F)
1.04
-4.5
-4.6
-4.8
-4.8
-15.3

Figure 4.70 (a) to (i) shows the variation in cell current with time measured on
GaAs/Ge cell at different cell voltages. The finite and measurable rise time of the current
indicates the existence of inductance in the cell discharge path. However, this does not
affect the measured capacitance. The area under the curve gives the total charge (Q)
accumulated in the solar cell and dividing it with the corresponding cell voltage gives the
cell capacitance (charge equivalent). This is compared with the charge equivalent
capacitance derived from the impedance spectroscopy technique at different cell voltages,
in Figure 4.71. It is observed that the deviation is with in +5%.
(a)
(b)
(c)
(d)
(e)
(f)
(h)
(i)
Figure 4.71: Cell Capacitance at different cell voltage (GaAs/Ge)
4.2.6.4 Summary
This time domain technique measures only the voltage dependent capacitance of
any non-linear devices like solar cell in terms of charge equivalent capacitance. The
measured charge equivalent cell capacitance can be used for the design of switching
charge controllers suitable for photovoltaic power systems. However this technique has
the following limitations.
1. This technique measures only capacitance and not other parameters like
resistance, etc.
2. If the capacitor is non-linear in nature and voltage dependent like solar cell
capacitance then it measures only integral value.
3. The effect of frequency on capacitance and cell resistance cannot be determined.
4. It is easy to calculate integral value from the differential value. Hence, it will be
difficult to calculate differential value from integral value measured here.
5.
The errors are more if the charge accumulated is small i.e. if cell capacitance is
small.
Chapter 5
APPLICATIONS OF SOLAR CELL AC PARAMETERS
In this chapter applications of solar cell AC parameters, especially solar cell
capacitance is discussed. In general the solar cells are connected in series and parallel in
order to generate the required power at the desired voltage. It is easy to measure single
solar cell AC parameters when compared with solar array AC parameters. Hence an
analysis on scaling solar cell capacitance to a panel is presented in the first part of the
chapter. The effect of solar array capacitance on the design and performance of switching
shunt voltage regulators is presented in the second part of this chapter.
5.1 Scaling of Single Cell Capacitance to Array Capacitance

A typical solar array with 11 silicon solar cells of 100mm diameter connected in
series is shown in Figure 5.1. It is practically difficult to have identical cells with exactly
same short circuit current. In general, the solar array cells may have the deviation in their
short circuit current (upto +20%). For the analysis, it is assumed that 10 cells (2 to 11
shown in Figure 5.1) are identical and are having the same short circuit current (Isc)
Figure 5.1: Solar cells connected in series

whereas cell 1 has a short circuit current of 20% more or less than the other solar cells.
The static characteristics of both solar cell and array in forward and reverse bias are
shown in Figure 5.2. Plot 1 shows the I-V characteristics of a single solar cell with short
circuit current of 2A as measured at AM1.5. Plots 2 and 3 are with short circuit current of
20% less and 20% more respectively. Plots 4 and 5 show the illuminated I-V
characteristics of 10 and 11 identical cells connected in series respectively, derived from
Plot 1. Plot 6 shows power verses array voltage for 11 identical cells connected in series.
The effective array capacitance is estimated as follows.
Case-1: Cell 1 with 80% Isc (20% less)
The Isc of 10 identical solar cells (cell 2 to 11) is 2 A, whereas for cell 1 Isc is 1.6
A. The solar array operating voltage is chosen as 5.5V(Point f in Figure 5.2, Plot 5),
which is the maximum power point voltage of the solar array with identical cells. Since
all cells are connected in series, the current passing through all the solar cells must be
equal at any operating point. However, the operating point of each cell shifts to fulfill the
array condition of short or operating voltage. When the solar array is shorted, cell 1 will
be at 0.5V (Point a on Plot 2 in Figure 5.2) as the current through the series connected
solar cells should be same. The Cells 2 to 11 will be at voltage 0.05V so that the algebraic
sum of all cell voltages, which is the array voltage, is zero (-0.5 +10*0.05 = 0).
When the array is at operating voltage of 5.5V, the cell 1 will be at 0.2V (Point b
on Plot 2) and the other solar cells will be at 0.53 V (((5.5 0.2)/10)= 0.53). When the
solar array is switched from operating voltage (5.5V) to short circuit voltage (0 V) the
voltage of Cell 1 varies from 0.2 V to 0.5 V whereas voltages of other solar cells vary
from 0.53 V to 0.05 V. This condition is imposed on individual cells, as their currents
have to be same irrespective of variation in their characteristics.
Note that cells 2 to11 operate with small forward bias voltage, so that the same
current can be driven into cell 1, which is in reverse bias when array voltage is zero
(shorted). Similarly, when operating at 5.5V cells 2 to 11 are operated above the normal
voltage of 0.5V (0.53V) to make up for the lower voltage operation (0.2V) of cell 1.
Because of the difference in the operating voltage range between short circuit and
operating point of array, the charges exchanged are different in cell 1 and in cells 2 to 11.
This results in different effective capacitance of these cells, which is calculated by
integrating the dynamic value of capacitance (Cp) between these voltages.
The silicon solar cell capacitance Cp measured using impedance spectroscopy
technique over wide range of operating voltages (refer Chapter 4, Section 4.3) are
represented in Table 5.1 The charge equivalent capacitance between any two voltages of
operation is derived from these values by numerical integration. When the Cell 1 is
switched from 0.5V to +0.2V its charge equivalent capacitance is 2.36F. The other ten
cells (cell 2 to 11) switch between +0.05V to +0.53V and their charge equivalent
capacitance is 15.75F per cell and 1.57F for the 10 solar cells in series. The net
capacitance of 11 solar cells connected in series is series combination of 2.36F and
1.57F, which is 0.95F. If all eleven solar cells were identical, each cell would have
switched from 0V to +0.5V when the array is switched between 0V to 5.5V and their
charge equivalent capacitance would be 7.68F per cell making the capacitance of the
solar array 0.7F. Thus, the capacitance of a mismatched (20 % less in Isc) array is about
1.35 times (0.95F/0.7F) the capacitance of the perfectly matched array of cells.
Case 2: Cell 1 with 120% Isc (20% more)
Cells 2 to 11 are with short circuit current of 2A, where as Cell 1 has short
circuit current of 2.4A (20 % more) with the solar array operating point at 5.5V. The
behaviour of the array / cell is shown in Figure 5.2. When solar array is shorted the
voltage across Cell 1 is 0.375V (Point h on Plot 3) and the Cells 2 to 11 are at 0.037V
(0.375 /10), which is close to zero. Under operating conditions the voltage across the Cell
1 is 0.5V (Point i on Plot 3) and the voltage across other cells (Cell 2 to 11) is 0.498V
((5.5 0.52)/10). When solar array is switched from operating point to short circuit, the
Cell 1 voltage varies from 0.52 V to 0.375V whereas voltage of other cells vary from 0.49
V to zero. From Table 5.1 the charge equivalent capacitance of Cell 1, between voltages
0.52 to 0.375V is calculated to be 24.24F and for Cells 2 to 11 the charge equivalent
capacitance is 7.68 F per cell. The net solar array charge equivalent capacitance is
0.75F. As discussed earlier the charge equivalent capacitance of array derived from
single solar cell capacitance is 0.7F, which is less than the array capacitance when one
solar cell is having 20% higher Isc. Thus, the capacitance of a mismatched (20 % less in
Isc) array is about 1.07 times (0.75F/0.7F) the capacitance of the perfectly matched
array of cells.
The above investigation revealed that the actual solar array capacitance is 7.5% to
35% higher than the value calculated from a single cell capacitance. The value of solar
array capacitance mainly depends on the dispersion of short circuit current from cell to
cell connected in series and their I-V characteristics. Hence, to derive the array
capacitance, a typical value of 7.5% to 35% of equivalent capacitance derived from single
cell has to be considered.
Table 5.1: Capacitance of silicon solar cell at different bias voltages
Cell Voltage
Cell capacitance
(V)
Cp (F)
-1
1.47
-0.8
1.58
-0.6
1.72
-0.5
1.89
-0.4
1.91
-0.2
2.16
0
2.56
0.2
3.31
0.3
3.80
0.4
5.77
0.45
11.3
0.5
68.8
0.55
124.0
Consider another case where 11 cells mentioned above are connected in parallel as
shown in Figure 5.3. The mismatch in the short circuit current does not affect the
effective capacitance value, because the operating voltages are same and hence the
capacitances simply add up. Therefore the effective array capacitance will be eleven
times that of a single cell capacitance. It is assumed in the above analysis that the solar
cell capacitances are equal irrespective of their short circuit current as their physical sizes
are equal.
Figure 5.3: Solar cells connected in parallel
Figure 5.2: Static characteristics of silicon solar cell and array
5.2 Effect of Solar Array Capacitance on the Performance of Switching Shunt

Voltage Regulator
Switching shunt voltage regulators are commonly used in photovoltaic power
generators. Figure 5.4 show the schematic of a fixed frequency pulse width modulated
(PWM) switching shunt voltage regulator. The solar array is represented with equivalent
circuit consisting of charge equivalent capacitance Cqa; parallel resistance Ra and
series resistor r. Here the current source is the photo-generated current whose value is
taken as equal to short-circuit current for all practical purpose. The other basic
components of control circuit such as output filter/bus capacitor CBus and isolation diode
Figure 5.4: Schematic of a fixed frequency PWM shunt switching voltage regulator
D1 are also shown in Figure 5.4. The comparator generates error by comparing
regulator output voltage with the reference signal Vref. The error is amplified and
compared with a ramp, to generate pulse width modulated (PWM) signal, which drives
the shunt switch S1 (MOSFET) ON and OFF. The power delivered by the solar array is
regulated by the pulse width modulated (PWM) shunt switch. When the shunt switch
turns OFF, the array voltage does not rise to its operating point instantaneously because
it has to charge its capacitance to the operating voltage before delivering power to the
load. Figure 5.5 shows a typical ripple generated in the bus voltage due to array
capacitance when the shunt switch is opened.
Whenever the shunt switch (S1) turns ON, it shorts the solar array and
consequently discharges the charge stored in the solar array capacitance. A typical
waveform of the current through the shunt switch is shown in Figure 5.6. The energy
stored in the array capacitance is dissipated through the shunt switch when it is closed.
Hence, care has to be taken in selection of shunt switch. The energy pumped into the
shunting device and the peak current in the shunt switch depend on,
The amount of charge stored in the capacitance

The amount of energy stored in the capacitance
Interconnecting wire resistance and inductance.
Resistance of the shunting device.
The solar cell/array capacitance being non-linear; the energy stored in this capacitor is,
Vs
E n = C p Vdv
(5.1)
The energy stored in solar cell capacitance is,
En =
1
C e Vs2
2
(5.2)
where,
Vs
change in voltage across the solar array
Ce
Energy equivalent capacitance
The energy equivalent capacitance (Ce) is,
1
Ce = 2
Vs
Vs
VC
dv
(5.3)
The capacitance (Ce) is used to calculate the energy stored in the solar cell
capacitance, which is useful for calculating the additional power loss in the switch. A
solar array is operated around its maximum power point where the solar array capacitance
is considerable (0.05F/cm2 for silicon solar cell refer Figure 5.7) which rapidly
increases towards open circuit voltage. Hence, the influence of solar array capacitance on
the performance of shunt regulator should be considered in designing the solar
photovoltaic power conditioning systems.
V1
V2
Figure 5.5: Typical Bus voltage ripple
Due
to
charge
accumulated
in
the
capacitance of solar
array and
Due
to
parasitic inductance in
the circuit
Figure 5.6: Typical current through shunt switch S1 at the instant of its closure
5.2.1 Ripple Voltage at the Output Due to Solar Cell Capacitance
It is shown that the ripple voltage depends on the array capacitance. Hence a
quantative analysis is made to determine the relation between the ripple voltage and the
array capacitance.
5.2.1.1 Steady State Analysis
Often, switching shunt regulators are designed without taking into account the
solar cell AC parameters particularly, solar cell / array capacitance [Patel. A.R et. al.
(1990)]. For a fixed frequency shunt voltage regulator shown in Figure 5.8 (a) along with
timing diagram the output voltage ripple is given by (neglecting array capacitance),
I D(1 D)
ILD
= SC
C B us f s
C Bus f s
V1 =
(5.4)
Where
IL
ISC
CBus
fS
D
load current
solar array short circuit current
bus capacitance
switching frequency
duty cycle
The expected waveforms of current (Ic) through the bus capacitor and output
voltage (VB) when solar array is switched ON and OFF are shown in Figure 5.8 (b) to
5.8 (d). If equivalent series resistance (Rc) of the bus capacitor is also taken into account,
the output voltage ripple is given by,

V1 = I SC R C +
I SC D(1 D)
C Bus f S
(5.5)
where,
Rc
series equivalent resistance of bus capacitor
As the solar cell capacitance is large and increases exponentially with operating
voltage, it is essential to consider the solar cell capacitance in the design of switching
voltage regulators. Considering the solar cell capacitance the output voltage ripple at the
bus is given by,
VT = I SC R C +
I SC D(1 D) (Vo + V )C a (1 D )
+
CBfS
CB
where,
VTR
Total ripple (V1 +V2)
diode forward voltage drop
The detailed derivation of Equation 5.5 is given in Appendix 4.
(5.6)
Figure 5.7: Variation of cell capacitance, current and power as a function of cell voltage
Figure 5.8: (a) Equivalent circuit of shunt regulator, (b) switch status, (c) current
through bus capacitor and (d) output voltage ripple
The Equation 5.6 is written with an assumption that the solar array series
resistance and the ON resistance of the switch are negligible. This shows that the output
voltage ripple due to array increases with increase of array charge equivalent capacitance
(Cqa) and decrease of duty cycle (D) of the switch.
The switching waveforms,
extra/additional ripple voltage due to array capacitance is shown in Figure 5.9. When the
switch is opened at time t3 the time taken (t4 t3) by the array voltage to increase to
voltage Vs, which is equal to (Vo + V). It is determined by the array capacitance and its
short circuit current.
t 4 t 3 =
C qa (Vo + V )
ISC
C qa Vs
I sc
C qa Vo
(5.7)
ISC
The slow raise of array voltage causes an extra output ripple (V2) and is given by,
V2 =
C qa I L (Vo + V )
C Bus I SC
C qa Vs (1 D)
C Bus
C qa Vo (1 D)
C Bus
(5.8)
The derivation details of extra ripple voltage (V2) are given in Appendix-5.
The variation of extra ripple (V2) due to array capacitance as a function of
operating point for a typical solar array is shown in Figure 5.10. Observe that the extra
ripple (V2) increases rapidly as the operating point shifts towards open circuit voltage
(Voc) of the array.
The above discussion is valid not only for a fixed frequency shunt-switching
voltage regulator but also for a variable frequency shunt-switching voltage regulator. The
governing equations are same as that for fixed frequency shunt switching regulators.
The voltage regulator is designed to work close to maximum power point (Vmp,
Imp) of the solar cell/array. Hence, the most relevant operating point at which capacitance
has to be measured is Vmp. The solar array works normally at varying temperatures
between 20oC to +60oC in terrestrial and 100oC to +100oC in space applications. As
solar cell capacitance at Vmp increases with temperature it is necessary to consider the
solar array charge equivalent capacitance (Cqa) at Vmp and at the expected maximum
operating temperature to design a reliable switching shunt voltage regulator. At all
temperatures lower than the maximum expected operating temperature. The regulator will
be operating at and below Vmp and the Cqa will be lower.
Figure 5.9 (a): Shunt switch status, (b) Voltage across shunt switch, (c) Output voltage
ripple with extra ripple due to array capacitance
CBus is choosen equal to Cqa at Voc
Figure 5.10: Extra ripple versus array voltage
A fixed frequency pulse width modulated (PWM) switching shunt regulator

(shown in Figure 5.4) is designed, developed and tested with an array consisting of
27 silicon solar cells each of area 78.5 cm2 connected in series. The charge equivalent
capacitance (Cqa) of this solar cell array is measured at different bias voltages (around
Vmp) using time domain technique (refer Chapter 4 Section 4.3). The measured array
capacitance is shown in Figure 5.11. The array operating voltage of 10.5V chosen, which
is close to Vmp (10.3V) giving the voltage across load (Vo) of 9.8V (after diode forward
voltage drop). The array is illuminated by a set of halogen lamps located in such a way to
give uniform illumination on the entire solar array. The measured short circuit current of
solar cell array is 1.05A as the intensity of illumination is less than AM1.5. However, the
cell capacitance does not depend on intensity. The switching voltage regulator is operated
at different load currents (0.1A to 0.6A in steps of 0.1A) and at different switching
frequencies ranging from 20kHz to 80kHz. The regulator output voltage ripple and
voltage waveforms at the shunt switch are monitored on a digital storage oscilloscope
(Tektronix: TDS 2012).
Figure 5.11 shows the variation in array capacitance measured with array voltage
and it is observed that the solar array capacitance is 0.166F at Vmp (10.3V). The actual
array capacitance (0.166F at 10.3V) is 30% more than the solar array charge equivalent
capacitance (0.127F at 10.3V), derived from single cell data, which is presented in
Table 5.1. Snapshots of ripple voltage at load currents of 0.12A to 0.6A are shown in
Figure 5.11: Variation of array capacitance with array voltage
Figure 5.12 to 5.17 for a switching frequency of 20kHz. Figure 5.18 shows an expanded
view of the output voltage ripple at 0.6A load current. It is observed that the solar array
voltage took around 2.5s to rise from zero to 10.5V (refer waveform 1) resulting in an
extra ripple of 27.2mV (refer waveform 2). Extra ripple voltage (V2) measured for load
current varying from 10% (0.1A) to 60% (0.6A) of load is compared with calculated
values in Figure 5.19, which shows a very close match between the calculated and
measured values. The total ripple (V1+V2) measured is shown in Figure 5.20 at different
load currents along with theoretically calculated total ripple using Equations 5.6 and 5.8,
which are in good agreement with each other.
Array voltage (Vs)

5V/div
10.5V
Output ripple voltage

20mV/div
Array voltage (Vs)

5V/div
10.5V
50mV/div
Array voltage (Vs)

5V/div
10.5V
50mV/div
Array voltage (Vs)

5V/div
10.5V
50mV/div
Array voltage (Vs)

5V/div
10.5V
50mV/div
Array voltage (Vs)

5V/div

50mV/div
Due to array capacitance
Figure 5.18: Measured extra ripple at load current of 0.6A and 20 kHz
Figure 5.19: Variation of extra ripple with load current
Figure 5.20: Variation of total ripple with load current
By maintaining the load current constant at 0.305A, the switching frequency is

varied from 20kHz to 80kHz in steps of 20kHz and the output voltage ripple is measured.
Figures 5.21 to 5.24 show snapshots of the output voltage ripple at different frequencies.
The total ripple (V1+V2) and extra ripple voltage (V2) measured as a function of switching
frequency for a given (fixed) bus capacitance are shown in Figure 5.25. It is observed that
the total ripple voltage decreases with the increase in switching frequency but additional
ripple voltage (V2) is constant as expected for a given CBus. This implies that, as the
switching frequency of the regulator increases, the ripple due to array capacitance
dominates the total output ripple more and more.
Note: At higher frequencies there are several small oscillatory voltages, which are not
considered here as not relevant to the discussion.
Array voltage (Vs)

5V/div
10.5V
50mV/div
Array voltage (Vs)

5V/div
10.5V
50mV/div
Array voltage (Vs)

5V/div
10.5V

10mV/div
Array voltage (Vs)

5V/div
10.5V

10mV/div
CBus is fixed
Figure 5.25: Variation of extra ripple and total ripple with switching frequency
5.2.1.4 Design Considerations
The present trend in the design of switching regulators is to achieve higher

switching frequency, which will result in higher power density. For a given switching
frequency (fs) the ripple voltage is maximum when duty cycle (D) is equal to 0.5 and
Equation 5.5 can be re-written as,
V1(max) = ISC R C +
0.25ISC
C Bf S
(5.9)
The minimum bus capacitance required is calculated from Equation 5.9 as [Patel. A. R, et
al. (1990)],
C Bus (min)
0.25I SC
f S (V1 (max) I SC R C )
(5.10)
The total output voltage ripple (VTR) is given by,

VTR = (V1 + V2 ) =
C qa Vo (1 D)
I sc (1 D)D
+ I SC R C +
C Bus f s
C Bus
(5.11)
At higher switching frequency, a lower value of CBus is sufficient to maintain the

total ripple at the desired level. However, V2 increases with frequency as CBus decreases
with frequency (from Equation 5.10). The two parts of the ripple voltages are equal when
fs is equal to fo,
fs = fo =
I sc D
ILD
ILD
D
=
=
(Vo + V )C qa Vs C qa (1 D) Vo C qa (1 D) R L C qa (1 D)
where,
if D=0.5,
Vs = (Vo+V) ~ Vo, because V is very small compare to Vo

load resistance = Vo/IL
RL
fo =
1
R L C qa
(5.13)
(5.12)
Keeping the value of total ripple (V1 +V2) fixed at 25mV (as a design
specification), the variation of bus capacitance with switching frequency is calculated
using Equation 5.9 and is shown in Figure 5.26. Additionally, extra ripple voltage (V2)
due to array capacitance (using Equation 5.8) and ripple voltage (V1) due to bus
capacitance using Equation 5.6 is calculated for different switching frequencies and are
shown in Figure 5.26. It is observed that the required value of bus capacitor decreases
rapidly with the switching frequency. The extra ripple voltage (V2) due to array
capacitance increases with the switching frequency, as the value of bus capacitance
reduces and at switching frequency fo = 294.2kHz (point A in Figure 5.26) both the
ripple voltages (V1 and V2) become equal. Beyond fo the ripple voltage due to array
capacitance dominates the total ripple. This limits the maximum switching frequency of
the regulator and also if the operating voltage of the array goes beyond Vmp, Cqa
increases rapidly and fo decreases correspondingly. Hence, it is necessary to select the
operating point such that it does not cross Vmp at the maximum expected operating
temperature.
Figure 5.26: Variation of bus capacitance, ripple voltages with switching frequency (Theoretical estimate)
5.2.2 Current peaking
Another important parameter to be considered in the design of switching voltage

regulator is the peak current in the shunt switch. As discussed earlier (refer Figure 5.6),
when the shunt switch is closed the current through the shunt switch increases from zero
to Isc but additionally the current peaks because of the charge stored in the array
capacitance which discharges into the shunt. This current peak has to be accounted for a
reliable device operation. This peak current with large rate of change of current also
causes the electro magnetic interferences (EMI). Hence the EMI and problems associated
with the current peaking should be reduced.
The peak value of current depends on the following,
Rate at which the shunt switch is closed
The value of charge equivalent capacitance
The value of cell shunt resistance and the inductance in the circuit
Neglecting the values of resistance and inductance, the peak current lies, between the two
limiting values given below,
i p (min) = C qa
dv
dt
(5.14)
and
i p (max) = C Pa
Vs
dv
or i p (max) =
, which is lower
dt
R dsON + ra
(5.15)
where
dv/dt is the rate at which the voltage across the array changes. it depends on the
turn ON of the switch.
Figures 5.27(a) to (e) show snapshots of the peak current in the shunt switch
during turn ON time for 0.1A to 0.5A load currents.
Peak current due to

array capacitance
3A
1.05A
Figure 5.27 (a): Shunt switch current during turn-ON
Array voltage (Vs)

5V/div
3A
1.05A
Current in shunt
switch measured as
voltage across 1.
500mV/div
Figure 5.27 (b): Shunt switch current during turn-ON
3A
Array voltage (Vs)

5V/div
1.05A
Current in shunt
switch measured as
voltage across 1.
500mV/div
Figure 5.27 (c): Shunt switch current during turn-ON
3A
1.05A
Array voltage (Vs)

5V/div
Current in shunt
switch measured as
voltage across 1.
500mV/div
Figure 5.27 (d): Shunt switch current during turn-ON
3A
Array voltage (Vs)
5V/div
1.05A
Current in shunt
switch measured as
voltage across 1.
500mV/div
Figure 5.27 (e): Shunt switch current during turn-ON
It is observed that the peak current (3A), is around thrice the steady state current
(Isc=1.05A). Also it is observed that the peak current is same at all load currents, which
indicates the peak current is independent of load current. The oscillations in the current
are due to interconnecting lead and stray inductances. Cho. B. H, et al, (1995) suggested
to use an inductor in series with the solar array to limit the peak current but it affects the
stability of the regulator. To overcome the problem of peaking current, it is attempted to

increase the turn ON time of the shunt switch is increased, which will reduce the peak
current to a safe value, but increases the power loss. Hence, a study on power loss in the
shunt switch is presented in the subsequent sections.
5.2.3 Power Loss in Shunt Switch
The power loss in the shunt switch depends on the following
Energy stored in the solar array capacitance.

Switching frequency.
ON resistance of the shunt switch.
Turn ON and OFF time of the shunt switch.
Duty -cycle of the shunt switch ON/OFF operations.
5.2.3.1 Power loss due to energy stored in the capacitance of the solar array
The energy (Eac) stored in the capacitance of the solar array discharges into the shunt
switch when it is closed. It is given by,
E ac =
1
C ea Vo2
2
(5.16)
where,
Cea
Energy equivalent capacitance of solar array
Vo
Array operating voltage
The average power loss (Pa) in shunt switch due to array capacitance is given by,
Pa = f s E ac =
1
C ea Vo2 f s
2
(5.17)
5.2.3.2 Power loss due ON resistance of the shunt switch
When the shunt switch is ON the solar array is shorted and the current through the
shunt switch is its short circuit (Isc) current. The average power loss (Prd) due to ON
resistance of shunt switch is,
Prd = I sc2 R dsON D
(5.18)
where,
RdsON
ON resistance of the shunt switch
5.2.3.3 Power loss due to Turn ON and OFF time of the shunt switch
The power loss due to turn ON time of the shunt switch is discussed here.
Figure 5.32 shows the graph of gate voltage, source drain voltage, and drain
current during turn ON time of the shunt switch (MOSFET). The total turn ON time is
from t0 to t4. At the time t0 the drive voltage is made high. From t0 to t1 the gate voltage
increases and reaches to VTH (threshold voltage). From time t1+ the drain source current
starts increasing and reach a peak value at time t3 and at the same time the drain source
voltage remains unchanged at Vo. From time t3+ the drain source voltage reduces to zero
linearly and the current remains constant at Isc.
Excluding energy in the solar array capacitance, the energy dissipated in the shunt
switch during turn ON is,
t4
E ON = vidt =
t1
Vo I SC TON
2
(5.19)
where
TON
time between t1 to t4
Hence average power loss (PTON) is given by,

PT ON =
Vo ISC TON f s
2
(5.20)
It is observed from Equation 5.20 that the power loss in shunt switch increases
with turn ON time and switching frequency. It is observed that with slow turn ON the
peak value of current in shunt switch reduces and power loss in the shunt switch
increases. Hence it is a trade off between these two parameters to choose a suitable shunt
switch. In Figure 5.33 the turn OFF characteristics are shown. At the time t0 the gate
source voltage starts going low. From time t0 to t2 the drain source current is constant at
ISC, which from t2 to t3 deceases linearly to zero. The drain source voltage is zero from t0
to t1 and later it increases linearly and at time t4 it reaches Vo. Similar to turn ON, the
average power loss in the shunt switch during turn OFF is given by,
PT OFF =
Vo ISC TOFFf s
2
(5.21)
The total average power loss in the shunt switch is sum of the power losses and is,
PT = Pa + Prd + PTON + PTOFF
PT =
(5.22)
VI T f
VI T f
1
2
C ea Vo2 f s + I sca
R dsON D + o SC ON s + o SC OFF s
2
2
2
(5.23)
The selection of the switch depends on the total power loss in the shunt switch and
the allowable peak current, which depends on the turn ON time. It may be seen that the
loss due to array capacitance and increase of TON and TOFF to reduce Ipeak introduces
additional power loss in the circuit.
Figure 5.32: Turn ON characteristics of

MOSFET
Figure 5.33: Turn OFF characteristics of

MOSFET
5.2.3.4 Power loss estimation
As an example the power loss in the shunt switch due to array capacitance, switch
ON resistance Turn ON and OFF time of the shunt switch is estimated at different
switching frequencies ranging from 10kHz to 1MHz.
The power loss is estimated for the solar array and the shunt switching voltage
regulator used for studying the effect of cell capacitance on the ripple voltage as
described earlier. The solar array energy equivalent capacitance calculated is 0.12F for
silicon solar cell at 10.3V. The measured solar cell array short circuit current is 1.05A and
the power generated by the solar array at 10.3V is 10.8W. The shunt switch used is
MOSFET (IRFZ44), whos ON resistance RdsON=0.028 and TON +TOFF is 261ns. Using
Equation 5.23, the power loss is calculated at switching frequency of 20kHz as,
Power loss due to array capacitance (Pa)

Power loss due to RdsON (Prd)
Power loss due ON and OFF time of the switch (PTON+PTOFF)
Total power loss in shunt switch (PT)
Voltage regulator efficiency
=0.106W
=0.015W
=0.0280W
=0.1494W.
= 98.6%
It is observed that the power loss due to charge stored in solar array capacitance
dominates. Figure 5.34 shows the power loss in shunt switch and the efficiency of the
switching voltage regulator at different switching frequencies. It is observed that the
power loss due to array capacitance increases, whereas the power loss due to RdsON of
shunt switch is constant. Observe the major portion of total power loss is due to array
capacitance.
Figure 5.34: Power loss in the shunt switch at different switching frequencies
5.2.3.5 Comparison of power loss in shunt switch with silicon and GaAs/Ge solar cell
arrays
GaAs/Ge and silicon solar cell arrays with operating voltage of 10.5V and
maximum array current of 1.05A, which can deliver power of 10.8W are used for
estimation of power loss in shunt switch as a function of switching frequency.
As mentioned earlier the silicon solar cell array energy equivalent capacitance is
0.12F at 10.5V. The GaAs/Ge solar array energy equivalent capacitance is extrapolated
from the single cell data assuming that all cells in the array are identical and have same
short-circuit current. The value of energy equivalent capacitance of GaAs/Ge solar cell
array is 0.5F at 10.5V. Using these capacitance values in Equation 5.17 the power loss
in shunt switch due to array capacitance at different switching frequencies for both silicon
and GaAs/Ge solar cell arrays are calculated and shown in Figure 5.35. As other power
loss such as due to ON resistance and turn ON and OFF time being constant are not
calculated.
Figure 5.35: Power loss in shunt switch due to array capacitance
It is observed that for a given switching frequency the power loss in shunt switch
due to GaAs/Ge solar cell array is approximately three times more than the power loss in
shunt switch due to silicon solar cell array. This analysis reveals that for this GaAs/Ge
solar array the power loss is 100% if it is switched at 400kHz. Hence, the switching
frequency of the shunt switching voltage regulator is limited by the solar array energy
equivalent capacitance.
5.3
Effect of cell parallel resistance on design and performance of shunt
switching voltage regulator.
In Equation 5.8 the extra / additional ripple voltage V2 is derived by neglecting

array parallel resistance (Rpa). From the measurement it is observed that cell parallel
resistance (Rp) is larger compared to the ON resistance of shunt switch upto Vmp.
Beyond Vmp and close to Voc the shunt resistance is comparable with ON resistance of
shunt switch. When the shunt switch is opened, the voltage across solar array rises from
zero to operating voltage Vo in time ta (refer Figure 5.9). As time ta increases, the
additional /extra ripple voltage increases. When the solar array parallel resistance is
considered, it provides an additional path to discharge the array capacitor, thus increasing
time ta.
Till the array voltage
increases to operating voltage
Vs (=Vo+V), the current from
solar array to load is zero and
hence it is virtually open
circuit. Under this condition the
Figure 5.36: Equivalent circuit of solar array
solar array is represented as shown in Figure 5.36.

The solar cell array output current (IL) is zero. The photo-generated current
(Iph ~ Isc) is given by,
I sc = I r + I c
5.24
The current through solar array capacitance (Cpa) is given by,
I c = C pa
dVs
dt
5.25
and current through solar array resistance is given by,

Ir =
Vs
R pa
5.26
It is to be noted that the solar array parallel resistance (Rpa) is not the resistance
measured using impedance spectroscopy technique earlier. It is the Thevenins equivalent
resistance of the solar array at the operating point as shown in Figure 5.37. The minimum
value of Rpa is Voc/ISC.
Figure 5.37: Illuminated I-V characteristics defining Rpa
From Equation 5.24, Isc is given by,

I sc = C pa
dVs
V
+ s
dt
R pa
5.27
By solving Equation 5.27, the solar array operating voltage Vs is given by,
t
tI sc
R p a C pa
Voc C pa
Vs = I sc R a 1 e
= Voc 1 e
5.28
Calculating time ta required to reach voltage Vs,
ta =
- Voc C pa
I sc
V
ln 1 s
Voc
5.29
The time ta (refer Figure 5.9(c)) is the time taken to charge solar array
capacitance when shunt switch is opened considering the effect of array parallel
resistance.
If Vmp = 0.8 Voc = Vs (design specifications assumed)
Then maximum time ta will be,
t a (max) = 2.01
Vs C pa
I sc
5.30
Substituting ta(max) in Equation 5.7 for (t4-t3)

The value of V2 is,
V2 (max) = 2.01
Vs C pa
I L = 2.01V2
5.32
C Bus I sc
It is important to note that when array capacitance is measured by charge
accumulation technique, what is measured is the charge Q delivered to the switch. The
charge equivalent capacitance calculated from this Q automatically takes into account
the discharge of cell capacitance through the internal cell shunt resistance and need not be
additionally considered. This is the reason why the calculated and experimental values of
ripple (refer Figures 5.19 and 5.20) are in close agreement.
5.3.1 Importance and need of cell parallel resistance (Rp)
The solar cell array parallel resistance (Rpa) measured is parallel combination of shunt
resistance Rt and cell dynamic resistance Rd. Beyond Vmp, Rp is equal to Rd and
below Vmp; Rp is equal to Rt. The cell parallel resistance (Rp) measured using
impedance spectroscopy technique has following applications.
The Rp close to open circuit voltage is used for calculating carrier mean life time
(), diode factor ().
For calculating voltage injected due to external conducted EMI, the local value of
resistance (Rp) at the operating point is used.
For stability analysis of the shunt or series switching voltage regulator the solar
cell / array is modeled by its small signal (AC) characteristics where dynamic or
local value of cell resistance (Rp) and cell capacitance (Cp) is of importance.
Brief overview of the effect of RP on stability of shunt regulator is presented below,
The small signal equivalent circuit of array and switching regulator is shown in
Figure 5.38 [Cho .B. H, et al. (1988)]. Rp, Cp, and r represents small signal (AC)
equivalent of solar array whereas Rs and CBus is the equivalent circuit of the bus
capacitance. YB is the admittance function of shunt regulator and RL is the load
resistance. Cho .B. H, et al. (1988) showed that there are two poles and one zero. The
two poles are; i) high frequency pole given by RpaCpa, and ii) low frequency pole given by
RpaCBus. The zero is given by RsCBus. The corresponding frequencies are,
FHP = 1/2 RpaCpa,
FLP = 1/2 RpaCBus,
and
FZ = 1/2 RsCBus
Here RpaCpa is fairly low compared to RpaCBus; hence FHP is sufficiently larger than FLP
and is be beyond the frequency of interest. Also (RpaCpa /2) is and hence, FHP is fairly
constant irrespective of and operating point between Vmp and Voc. It is noted that Rpa
is a function of temperature and operating point, which must be considered for designing
admittance function (YB) of shunt regulator to make the system stable. The point here is
just to show the importance of Rpa measurement only.
Figure 5.38: Small signal equivalent circuit of solar photovoltaic shunt regulator
5.4
Summary
The output voltage ripple in a switching regulator increases with solar cell array
capacitance and it dominates above certain frequency fo > (Cqa RL)-1. For design
applications, it is necessary to consider the solar array charge equivalent capacitance at
the maximum power point and at the maximum operating temperature. The capacitance to
be considered for design of switching shunt voltage regulator is the charge equivalent
capacitor (Cqa) and not the cell capacitance (Cpa).
At higher switching frequencies the power loss due to charge stored in the array
capacitance is high and the efficiency of the switching regulator is low. Hence, the
switching frequency is limited by the value of array capacitance. The power loss in shunt
switch also depends on TON time, which determines the peak current in the shunt switch.
Chapter 6
CONCLUDING REMARKS
The conclusions drawn from the present investigations are presented under three
topics namely instrumentation, measurements and applications.
6.1
Instrumentation
Impedance Spectroscopy technique is suitable for measuring the AC parameters of
nonlinear devices such as solar cells.
A new instrument called Solar Cell Impedance Analyzer is developed to measure

solar cell AC parameters, which overcomes all the limitations of the earlier
measurement setups.
The concept of software range extender introduced, has virtually extended the
frequency range of the analog power amplifier in digital domain and improved the
measurement accuracy.
With the software range extender, the solar cell impedance analyzer measured the
solar cell AC parameters in the frequency range of 10Hz to 1MHz with a deviation
less than + 4%.
With the solar cell impedance analyzer parameters like cell capacitance (transition or
diffusion), cell dynamic resistance, cell series resistance and cell inductance are
measured. The extended range could show the frequency dependence of cell
capacitance and resistance.
From the measured parameters the charge equivalent and energy equivalent
capacitances are derived.
With time domain technique the charge accumulated in the solar cell is measured at
different bias voltages. From this the charge equivalent capacitances are calculated.
These values are used for designing a switching shunt voltage regulator.
6.2
Measurements
The measurements made on GaAs/Ge solar cell in dark and illumination show that the
cell capacitance and resistance do not depend on the condition of measurement.
Cell parameters measured in dark are more accurate than that measured under
illumination.
From application point of view, the cell parameters under illumination at different cell
terminal voltages are important, which can easily be computed from the dark data
with good accuracy.
The p-n junction of GaAs/Ge and BSFR silicon solar cells is an abrupt junction.
In both types of solar cells the cell capacitance increases with cell voltage, whereas
the cell resistance decreases with increase in cell voltage in forward bias.
The cell capacitance and cell resistance of both GaAs/Ge and silicon BSFR solar cell
are nonlinear and vary with bias voltage and temperature.
In reverse bias GaAs/Ge cell resistance increases as cell voltage reaches zero, whereas
in BSFR silicon solar cell the variation is very small.
In both solar cells the cell capacitance in forward bias increases with temperature at
all bias voltages, whereas cell resistance decreases with increase in temperature.
At 298K, the variation of cell capacitance in GaAs/Ge solar cell over the operating
voltage range is from 1.254F to 1.975F, while in silicon BSFR solar cell the
capacitance varies over a large range from 0.1362F to 304.43F.
In both these solar cells the cell capacitance is insensitive to variation in temperature
in the reverse bias condition.
In GaAs/Ge the cell capacitance is mainly due to transition capacitance at all cell bias
voltages, whereas in BSFR silicon solar cell the transition capacitance and diffusion
capacitance dominate in different ranges of voltages.
In GaAs/Ge solar cell the cell capacitance at Vmp is constant at all temperatures,
whereas in BSFR silicon solar cell the cell capacitance at Vmp increases with
temperature.
GaAs/Ge solar cell resistance at Vmp decreases with increase in temperature,

whereas BSFR silicon solar cell resistance peaks at 245K.
The GaAs/Ge solar cell (size 40mm*20mm) series resistance is 0.15 and its series
inductance is 0.051H for all temperatures.
The silicon BSFR solar cell (size 40mm*20mm) series resistance is 0.06 and its
series inductance is 0.28H for all temperatures.
In silicon BSFR solar cells at frequencies where >>1, the impedance spectrum
deviates from semicircle and tends to a straight line with a slope of 45o. This indicates
that the cell capacitance and cell resistance are function of frequency.
6.3
Applications
The actual value of array capacitance will be higher than the array capacitance derived
from the value of a single cell capacitance by more than 10%, depending on the
mismatch in short circuit currents and the I-V characteristics of the cells in series.
The output voltage ripple in a shunt switching regulator increases with solar cell array
capacitance and it dominates above a certain frequency.
For design application it is necessary to consider the solar array charge equivalent
capacitance at the maximum power point and at the maximum operating temperature.
For calculating power loss due to array capacitance the energy equivalent capacitance
of the solar array need to be considered.
At higher switching frequencies the power loss due to charge stored in the array
capacitance is high and consequently efficiency of the switching regulator is low.
Hence, the switching frequency is limited by the solar array capacitance.
The peak current in shunt switch though can be reduced with a large turn ON time,
power loss in the shunt switch increases.
Appendix 1(a)
Specifications of Electrochemical Interface (1286)
Measurement Configuration
Cell connections
2-, 3- or 4-terminal, all floating
Working Electrode
Current measurement resistor
Full-scale current ranges
Limit of error
0.1 to 1M
2A to 200nA
0.1% 0.05% of range
Counter Electrode
Output Voltage
>30V
Current, subject to thermal protection limits 2A
Slew rate, Potentiostatic control
>10V/s
Reference Electrodes
Input impedance
Capacitance
Current
Limit of error
Rejection
DC Polarization
Voltage range
Limits of error
>10G
50pF
<1nA
0.1%100V
f<10kHz: 75dB, f<1MHz: 40dB
Max. Resolution
Current Range
Limit of error
Max. Resolution
14.5V
V<3.2V: 0.2% 200V
V>3.2V: 0.2% 2mV
100V
2A
0.2% 0.1% of range
100pA
DC Sweep: Analog Ramp

Ramp rate (voltage)
Segment Duration
6mV/min to 6000V/min
10ms to 105s
DC Sweep: Stepped Ramp

Step height
Step Duration
5V/5pA to 29V/4A
10ms to 105s
AC Input
Voltage Range
Gain
Impedance
10V
x1. X0.01
10K
Digital Meters
Resolution
3 1/2, 4 1/2, 5 1/2 Digits
Maximum Resolution
Bias Rejection
Voltage Range
Limit of Error
Resolution
Current ranges (full scale)
Limit of error
Resolution
Power Supply
Power Consumption
Dimensions (w x h x d)
Weight
Operating Temp. Range
1V/1pA
14.5V
0.2%10mV
5mV
200nA to 2A
0.2%1% of range
1% of range
90 to 110V, 108 to 132V,
198 to 242V, 216 to 264V,
48Hz to 65Hz
150VA
432mm x 108mm x 472mm
11kg (24lb)
0 to 50C (32 to 122F)
Appendix 1(b)
Specifications of Frequency Response Analyzer (1250)
Waveform
Frequency Range
Maximum Resolution
Stability
Amplitude
Resolution
Error
Distortion
Sine, Square, Triangle

10Hz to 65kHz
10Hz: 100ppm
(24hrs, 1C): 10ppm
10mV to 10V
1 in 1023
<1% 1 digit
<2%
DC Bias
Range
Resolution
Error
Maximum Voltage
Impedance
Connection
Output
-10.23V to +10.23V
1 in 1023
<1% 1 digit
150V
100 k/ 100 pF
front, floating, 4mm: rear floating, BNC
short circuit proof
Analyzers
Two independent analyzers operating in parallel
Range Sensitivity
Sensitivity
(Dynamic range)
Full scale
Peak input
Common mode
rejected
30mV
1V (90dB)
45mV
30V
300mV
10V (90dB)
500mV
30V
3V
100V (90dB)
5V
30V
30V
1mV (90dB)
50V
500V
300V
10mV
500V
500V
Maximum Input
Coupling
Input Impedance
Common Mode Rejection
Cross Channel Isolation
Measurement Delay
Power Supply
Consumption
Dimensions (w x h x d)
Weight
Operating Temp. Range
500V peak, 300V rms

DC or AC (<1dB at 2.5Hz)
1M
>65dB up to 50V peak (dc coupling up to 100Hz)
>100dB up to 10kHz (1kacross inputs)
0 to 105s
90 to 127V, 188 to 265V AC, 45 to 440Hz
130VA to 210VA
432mm x 176mm x 573mm
18kg (40lbs)
0 to 50 C (32 to 122 F).
Appendix 2
The transformation from series to parallel equivalent and vice versa is given below,
The network shown in Figure A2.1, consist of resistor (Rs) and capacitor (Cs) in series,
whose parallel equivalent network is with resistor (Rp) and capacitor (Cp).
Figure A2.1: Parallel and series equivalent circuits
a) Conversion of series equivalent circuit (Rs, Xs) to parallel equivalent circuit

(Rp, Xp) (Xs and Xp are capacitive reactance)
Z = R s jX s
1
1
1
=
+
Z R p - jX p
For series equivalent

For parallel equivalent
(A2.1)
(A2.2)
Equating Equations A2.2 and A2.1

1
1
1
+
=
R s - jX s
R p - jX p
Taking complex conjugate and solving for
imaginary terms,
(A2.3)
1
R s - jX s
and separating real and
R + jX s
1
=
= s2
R s -jX s R s + X s2
Rs
R s2 + X s2
jX s
R s2 + X s2
(A2.4)
Equating real and imaginary terms in Equations A2.4 with A2.2,

Rs
jX s
1
1
;
=
=
Rp
R s2 + X s2 jX p R s2 + X s2
(A2.5)
R s2 + X s2
R s2 + X s2
Rp =
; Xp =
Rs
Xs
(A2.6)
b) Conversion of parallel equivalent circuit (Rp, Xp) to series equivalent circuit

(Rs, Xs)
Similarly,
Z = R s -jX s =
1
1
1
+
R p jX p
(A2.7)
Simplifying by taking complex conjugate and solving,
Z=
jX p R p
R p jX p
X p2 R p
R p2 + X p2
jX p R p ( R p + jX p )
R p2 + X p2
jR p2 X p
(A2.8)
R p2 + X p2
Comparing Equation A2.8 with Equation A2.7 and equating real and imaginary terms
Rs =
X p2 R p
R p2 + X p2
; Xs =
R p2 X p
R p2 + X p2
A2.9
Appendix 3 (a)
Specifications of National Instruments Scope Card
(NI-5112)
100 MHz, 100 MS/s 8-bit Digitizer
Acquisition System
Resolution
Bandwidth (3 dB)
Number of channels
Max real-time sample rate
Max random interleaved sampling
(RIS) sample rate
Onboard sample memory
Calibrated vertical ranges
AC/DC accuracy
Input coupling
Low Frequency (3 dB)
Input impedance
Input protection
Time base System
Reference clock
Clock accuracy (as master)
Clock input tolerance (as slave)
Clock input levels
Sampling clock frequency
8 Bits
100MHz max
2 simultaneously sampled
100MS/s
2.5GS/s
16MB per channel,
25mV to 25V in 10% steps
2.5% of range set.
DC or AC, software-selectable
1.1Hz /11Hz
1M || 30 pF or 50, Softwareselectable.
42V (DC + peak AC) for 1M,
5Vrms for 50 .
10 MHz square wave
50 ppm
1% minimum
TTL
100MHz fixed, data can be
Decimated by n where 1<n<100e6
Triggering System
Modes
Source
Slope
Coupling
Hold-off time
Trigger resolution
TRIG input impedance
TRIG input protection
Acquisition methods
Random interleaved sampling (RIS)
Edge, hysteresis, window, digital

CH 0, CH 1, TRIG
Rising/falling
DC or AC on CH 0, CH 1, TRIG
100s to 171.79s
>1,000 steps in full-scale
1M || 30pF or 50,
Software-selectable
42V (DC + peak AC) for 1M,
5Vrms for 50.
200 MS/s to 2.5 GS/s effective
sample rate for repetitive signals
only.
Calibration
Self-calibration
Self-calibration is done by software

command. The Calibration involves
gain, offset, frequency response,
Interval
External calibration
triggering, and timing adjustment for

all input ranges.
24 hours, or any time temperature
changes beyond 2 C from
temperature at which last internal
calibration was performed
Internal reference requires External
recalibration
1 year
15 minutes
Interval
Warm-up time
Power Requirements
+3.3 VDC
0.5A
+5 VDC
1.5A
+12 VDC
80mA
12 VDC
120mA
I/O Connectors
Analog inputs CH 0, CH 1
BNC female
Analog trigger TRIG
BNC female
Digital trigger PFI 1
SMB female
Digital trigger PFI 2
9-pin DIN
Maximum working voltage (signal voltage plus common-mode voltage)
Channel to earth
42V, Installation Category I
Channel to channel
42V, Installation Category I
Environmental Requirements
Operating temperature
0C to 40C
Storage temperature
20C to 70C
Humidity
10% to 90%, non-condensing
Maximum altitude
2000m
Appendix 3 (b)
Specifications of National Instruments
Arbitrary Function Generator (NI 5401)
Analog Output
Number of channels
Resolution
Maximum update rate
Frequency range
Sine
SYNC (TTL)
Square
Ramp
Triangle
Voltage Output
Ranges
Accuracy
Output attenuation
Resolution
Pre-attenuation offset
Range
Accuracy
Output coupling
Output impedance
Load impedance
Output enable
Protection
Typical rise/fall time
Sine Spectral Purity
Harmonic products and spurs
Up to 1 MHz
Up to 16 MHz
Phase noise
1
12bits
40MHz
16MHz, max
16MHz, max
1MHz, max
1MHz, max
1MHz, max
5V into a 50 load;
0.1dB
073dB
0.001dB steps
2.5V into 50
5mV
DC
50 or 75, software
selectable
50 or greater
Software switchable
Short-circuit protected
8 ns (1090% 05 V square
wave into 50 load, filters
off)
60 dBc
35 dBc
105 dBc/Hz at 10 kHz from
carrier
Filter Characteristics
Digital
Type
Selection
Taps
Filter coefficients
Data interpolating frequency
Pipeline signal delay
Half-band interpolating
Software switchable
67
Fixed 20-bit
80 MS/s
26 sampling periods
Analog
Type
Waveform Specifications
Memory
Segment length
Segment linking (instruction FIFO)
Timing I/O
Update clock
External reference sources

Reference clock frequencies
Frequency locking range
7th-order L-C low pass filter

Pass band ripple2 dB
16,384 16-bit samples
16,384 samples, exact
512 links
Internal, 40MHz only
Frequency locking
Input connector, RTSI clock
line, or internal
1MHz, 520MHz in 1MHz
steps
100ppm
Triggers
Digital Trigger
Compatibility
Response
Pulse width (Td1)
Trigger to waveform
Output delay (Td2)
TTL
Rising edge
20ns, minimum
28 sample clocks plus150 ns,
max
Operational Modes
Type
Single, continuous, stepped
Internal Clock
Frequency
Initial accuracy
Temperature stability (0 to 50 C)
Aging (1 year)
40MHz
5ppm
25ppm
5ppm
Appendix 4
Ripple due to Bus capacitance
Figure 5.8 (refer in chapter 5), Ripple due to bus capacitance V1 is the ripple voltage,
For charge balance
( I sc I L )TOFF = I L TON
Duty cycle D =
TON
TON + TOFF
(A4.1)
(A4.2)
From Equations A4.1 and 4.2, we can write,

ISC I L TON
D
=
=
IL
TOFF 1 D
I L = ISC (1 D) =
V1 =
V1CB
TON
IL
I D
TON = L
CB
CBfs
(A4.3)
(A4.4)
(A4.5)
or
V1 =
ISC D(1 D)
CBfs
(A4.6)
Considering the effect of series equivalent resistance (Rc) of bus capacitor (CB) the ripple
V1 increases and is given by,
V1 =
ISC D(1 D)
+ ISC R C
CBfs
(A4.7)
Appendix 5
Extra /Additional ripple due to solar array capacitance
(Neglecting array resistance)
From Figure 5.9 (refer Chapter 5) V2 is the additional ripple due to solar array
capacitance at the output. It is assumed that the,
a. Solar array current and load current are constant
b. Solar array parallel resistance and series resistance are neglected
c. Switch ON resistance of the shunt switch is zero
When shunt switch opens at time t1, the voltage across solar array increases from
zero to Vs (=Vo +V). Where V is forward voltage drop across blocking diode. The Vs
is given by,
Vs =
ISC TOFF
Ca
TOFF =
Ca VS
ISC
(A5.1)
(A5.2)
where,
Ca
Isc
solar array charge equivalent capacitance

short circuit current of solar array
From Figure 5.9 (c)(refer Chapter 5) at time t2

TOFF =
CB V2
IL
(A5.3)
where,
IL
V2
load current
additional / extra ripple due to solar array capacitance
Equating Equations A5.2 and A5.3,

Ca Vs CB V2
=
ISC
IL
(A5.4)
Rearranging Equation (A5.4), the additional / extra ripple voltage at the output is,
V2 =
Ca I L Vs
CB ISC
(A5.5)
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Studies on Solar Cell AC Parameters

(Instrumentation, Measurements and Applications)

Indian Institute of Science

I owe my respected thanks to my parents Shri. K. Ramaseshasastry and Smt. R. Shashi,

Chapter 2: LITERATURE OVERVIEW

Comparison of AC Parameters between GaAs/Ge and Silicon

Area of cross-section in m2 of solar cell

Solar array / panel capacitance (Cp)

Bulk capacitance between front and back contacts

Diode diffusion capacitance of solar cell

Energy equivalent capacitance of solar cell

Solar array / panel Energy equivalent capacitance

Metal-semiconductor junction capacitance

Solar cell parallel capacitance

Charge equivalent capacitance

Solar array / Panel Charge equivalent capacitance

Diode transition capacitance

Rate of change of voltage

Energy stored in solar cell capacitance

Conduction Energy level

Band gap energy

Energy dissipated in the shunt switch during Turn ON

Energy dissipated in the shunt switch during Turn OFF

Valance energy level

Switching frequency of voltage regulator

Solar cell dynamic conductance

Imaginary (Z) Imaginary part of impedance

Current at maximum power point

Diode reverse saturation current

Minimum Peak current

Maximum Peak current

Photon generated current

Peak-to peak current

Root mean square current

Short circuit current

Complex quantity (SQRT (-1))

Boltzmans constant = 8.617 x 10-5 eV/K.

Doping concentration in p region

Doping concentration in n region

Intrinsic concentration of electrons & holes for the base semiconductor

Average power loss in shunt switch due to array capacitance

Maximum power point

Incident solar radiation power

Total average power loss in the shunt switch

Average power loss due to turn ON time in shunt switch

Average power loss due to turn OFF time in shunt switch

Average power loss due to ON resistance of shunt switch

Total charge stored in solar cell

Bulk / Series resistance

Bulk resistance of the n type region

Bulk resistance of the p type region

Equivalent series resistance of capacitor

Contact resistance between metal and n type semiconductor

Contact resistance between metal and p type semiconductor

Diode dynamic resistance of solar cell

Real part of impedance

Series equivalent resistance of RP||XP

Shunt resistance of solar cell

Surface recombination velocity

Forward voltage drop across diode

Solar cell diode voltage under dark

Solar cell diode voltage under illumination

Junction voltage / Built-in voltage

Maximum power point voltage