Digtal

Combinatorial Devices
A digital circuit can be in one of two states 0 or 1.

0-1 volts -> logic 0
2-5 volts -> logic 1
A gate is a simple electronic device that can be used to compute various
combinations of logic states.
A transistor can be thought of as a simple switch either closed or open.
Gates are made from transistors:
Invertor or NOT gate
Vcc
Vout
Collector
Vin
Base
Emitter
NAND gate
Vcc
Vout
V2
V1
NOR gate
Vcc
Vout
V1
V2
159.233 Lecture 1 - 1
Logic symbols used for these combinations are:

A
NOT
A
0
1
X
1
0
B
NAND
A
0
0
1
1
B
0
1
0
1
X
1
1
1
0
B
NOR
A
0
0
1
1
B
0
1
0
1
X
1
0
0
0
159.233 Lecture 1 - 2
B
AND
A
0
0
1
1
B
0
1
0
1
X
0
0
0
1
B
OR
A
0
0
1
1
B
0
1
0
1
X
0
1
1
1
A NAND or a NOR gate can be built from just two transistors

AND or OR require three, so most logic is built from NANDs and NORs
All logic circuits can be built just from NAND gates (or NOR)
eg an invertor:
A
1
NAND
159.233 Lecture 1 - 3
Boolean Algebra
Another way to describe circuits is by using Boolean Algebra.
Variables (normally capital letters) can be either 0 or 1 and can be
combined by :
AB
>AandB (sometimes written AB)
A+B
>AorB
>notA
From an arbitrary truth table, we can generate a Boolean expression:

A
0
0
1
1
B
0
1
0
1
C
1
0
1
1
Look at each row that produces a 1 in the C column. Form the expression
using AND and NOT that generates a 1. OR all the rows that produce a 1
together:
C
A B +A B +AB
To implement the function as a circuit:

A A
159.233 Lecture 1 - 4
Use standard ANDs and ORs to start with. Use more than two inputs if
necessary.
Convert to NANDs and NORs when finished.
Inverting circles can be added to/removed from either end of a line.
3 input devices can be formed from 2 input devices with the output
combined with the third input
is the same as:
The following equivalences also allow us to simplify our circuits:
which are a result of De Morgans Law AB = A + B
Cache memories
Large memories DRAM (dynamic ram) are slow
~100ns
compared to our pipeline time of ~10ns

Small memories SRAM (static ram) are fast
~10ns
159.233 Lecture 1 - 5
but are ~10 times as expensive.

Memory is built using a hierarchy,
disk being the slowest and cheapest
then DRAM
then SRAM the fastest and most expensive.
A library is a good example of a memory hierarchy.
It is very important to have access to all books in a library, but at any one
time you will only need a few books on one particular subject, and of
those books maybe a few pages in each.
If you leave the books open, on your desk, at these particular pages, you
have very fast access to the information.
If you are prepared to turn the pages you get slower access to other
information in the book.
If you are prepared to go to the library you get even slower access to lots
more information.
159.233 Lecture 1 - 6
The same principle applies to memory.

The Principle of Locality states that programs access a relatively small
portion of their address space at any instant of time.
Temporal locality - if an item is referenced, it will tend to be referenced
again soon
Spatial locality - if an item is referenced, items whose addresses are
close by will tend to be referenced soon.
A Hit is when the processor requests data that is in the faster memory
(cache).
Hit Rate is the percentage of accesses that are found in the cache.
Hit Time is the time taken to access the cache.
A Miss is when the processor requests data that is not in the cache.
Miss Rate is (1 - Hit Rate).
Miss Penalty is the time taken to move data from memory to cache.
The Block Size is the amount of data that is transferred from memory to
cache when a miss occurs.
Typical values are:
Block size 4 to 128 bytes
Hit time 1 cycle
Miss Penalty 8 cycles
Miss Rate 10%
Cache Size 256KB
159.233 Lecture 1 - 7
When the processor wants to access data x5:

It first decides whether it is already in the cache.
If it isnt it retrieves x5 from memory and inserts it in the cache.
X4
X1
X4
X1
X3
X3
X2
X5
X2
cache
before
cache
after
How does the processor know if the data is in the cache?

How does the processor know its position in the cache?
The cache is ordered so that there is a relation between memory
addresses and cache structure.
159.233 Lecture 1 - 8
Direct mapping
The position or index of a data item in the cache is determined directly
from its memory address.
Consider a cache of 8 entries each entry 32 bits wide.
Direct mapping will place data from memory into locations in the cache at
positions corresponding to the low-order 3 bits of their memory address:
location
000000
000001
000010
000011
000100
000101
000110
000111
001000
..
010101
..
111111
data
23
44
13
48
17
56
44
22
39
cache index
000
001
010
011
100
101
110
111
000
29
101
33
111
the 3 low order bits give the position in the cache.

When the processor is first switched on, the cache will not contain valid
data. So a valid bit is associated with each cache location, and is set
when data is written.
159.233 Lecture 1 - 9
Lots of memory locations are mapped to the same cache location.

We also need to know which location is currently in the cache.
We do this with a cache tags.
The cache tag is the remaining bits of the address:
cache
tag
000
100
011
000
000
010
100
111
cache
index
000
001
010
011
100
101
110
111
cache
data
23
28
34
48
17
29
92
33
corresponding
memory
000000
100001
011010
000011
000100
010101
100110
111111
To discover whether a data reference hits or misses the cache:

1
find the cache index of the address
2.
match the cache tag with the cache tag part of the address
100110
cache index is 110 -> cache tag is 100
cache tag part of 100110 is 100
100 == 100
-> hit
010011
cache index is 011 -> cache tag is 000
cache tag part of 010011 is 010
000 != 010
-> miss
159.233 Lecture 1 - 10
To increase the size of the cache we can either increase the number of
positions, or increase the size of the data stored at those positions
Example of a cache with 32 entries each 32 bytes of data:
cache
index
2
cachetag
10237
9
31
==?
Valid
cachetag
byte
select
1
4
0
cachedata
1
31
0
0
1
10237
36
31
Increasing the number of bytes for each cache entry involves a penalty
when there is a miss. More bytes need to be copied from memory into
the cache. Spatial locality means that this is not necessarily a bad thing!
Using the cache index to find the correct data line before comparing the
cache tag involves two levels of computation.
159.233 Lecture 1 - 11
A fully associative cache combines the cache index with the cache tag.
byte
select
1
4
0
cachetag
482933
31
Valid
cachedata
1
31
cachetag
11335
==?
33561
==?
482933
==?
7562
==?
36
To find out whether the data is in the cache:

compare the cache tag part of the memory address with all the cache
tags in the cache.
This matching is done in parallel in a fully associative cache.
159.233 Lecture 1 - 12
Cache replacement:
In a directly mapped cache:
If there is a cache miss then the cache is updated and the new entry
replaces the old.
In a fully associative cache:
If there is a cache miss then the new entry can be placed anywhere.
Where do we put it?
Using the Least Recently Used algorithm - hardware keeps track of which
cache entry has not been accessed for the longest time.
This can be tricky to implement!
159.233 Lecture 1 - 13
A simple pseudo LRU algorithm is:

Keep an index.
If the cache at that value is accessed add one to the index.
If a replacement is needed choose the cache entry at the index.
Cache writes:
Reading cache is straight forward. Writing to cache is not.
How do we keep cache data and memory data the same?
Write Back policy:

Keep an extra bit in each cache entry to mark whether the entry has been
written to.
When the cache entry is replaced, write it back to memory if it has
changed.
Write Through policy:

Always write to memory as well as to cache.
Use a write buffer between memory to speed up memory access.
Full Adder
A full adder adds two binary numbers (A,B) together and includes
provision for a carry in bit (Cin) and a carry out bit (Cout).
The truth table for a full adder is:
A
B
0
0
0
Cin
0
0
1
0
1
0
Cout
0
0
0
Sum
0
1
1
159.233 Lecture 1 - 14
0
1
1
1
1
1
0
0
1
1
1
0
1
0
1
1
0
1
1
1
0
1
0
0
1
->
Sum
Cout
=
=
A
B Cin
A BCin
A A
B B
+
+
A B
Cin
A
B Cin
+
+
A
B
Cin
AB
Cin
+
+
ABCin
ABCin
Cin Cin
Sum
B
Cout
Cin
Cin
159.233 Lecture 1 - 15
Decoder
A decoder accepts a binary encoded number as input and puts a logic 1
on the corresponding output line.
For 2 inputs
3 inputs
->
->
4 output lines
8 output lines
eg for 3 inputs with the signal 101 on them:

the 5th output line will be 1, the rest 0
Outputs
Inputs
I1
0
0
1
1
I0
0
1
0
1
A
1
0
0
0
Decoder
B
0
1
0
0
C
0
0
1
0
I1 I1
D
0
0
0
1
A=
I1
I0
B=
I1 I0
C=I1
I0
D=I1I0
I0 I0
A
I1
I1
I0
C
I0
D
159.233 Lecture 1 - 16
Decoder with output enable

Inputs
Decoder
Outputs
OE
All outputs will be 0 unless

OE
0
0
0
0
1
1
1
1
I1
0
0
1
1
0
0
1
1
I0
0
1
0
1
0
1
0
1
I1 I1
A
1
0
0
0
0
0
0
0
I0 I0
OE
(Output Enable) is Low

B
0
1
0
0
0
0
0
0
C
0
0
1
0
0
0
0
0
D
0
0
0
1
0
0
0
0
A=
I1
I0 OE
B=
I1 I0OE
C=I1I0
OE
D=I1I0OE
OE
A
Design a simple decoder for 4 bit numbers....
Multiplexor
159.233 Lecture 1 - 17
Chooses one input from many and copies it to the output.

OE
Output
Inputs
Control inputs
address
Common configurations are:

4 inputs 8 inputs -
2 address lines
3 address lines
The Output Enable line is the same as before

The truth table becomes unwieldy with so many variables, and is mostly
empty, so we cut out all the uninteresting cases:
OE
0
0
0
0
C1
0
0
1
1
C0
0
1
0
1
Q
I0
I1
I2
I3
OE(
C1
C0I0+
C1C0I1+C1
C0I2+C1C0I3)
159.233 Lecture 1 - 18
C1 C1
C0 C0
OE
I0
I1
I2
I3
159.233 Lecture 1 - 19
Demultiplexor
1 input is copied to one of several outputs
Common configurations are:
1 input
1 input
2 address lines
3 address lines
Input
4 outputs
8 outputs
Outputs
Control inputs
address
Consider the decoder. It is equivalent, if we replace the input with OE
Glitches
So far we have assumed that all logic devices are infinitely fast.
Outputs immediately reflect inputs.
In practice this is not the case. There is a short delay between an input
logic level changing and the corresponding output change.
Gate delays for TTL are typically 5 nanoseconds.
20 cm of wire will also delay a signal by 1 nanosecond.
159.233 Lecture 1 - 20
A
1
A
A+
=
A
TRUE
However consider what happens when the signal A goes from 1 to 0
A
A
A+A
This spurious 0 is called a glitch.
These glitches may or may not have disastrous effects.
It is possible to design circuits that have no glitches. This requires extra
hardware and considerable effort.
Another approach is to design circuits that are insensitive to glitches.
Wait a fixed time after a change - during which the glitches will go away.
This idea is the basis for clocked circuits that we will come to later.
159.233 Lecture 1 - 21
Memory
Feedback
If we loop the output of a circuit back into its input, we have a condition
called feedback, and some interesting results are obtained.
This circuit will oscillate rapidly
Will eventually settle on one input 0 and the other 1 (either way)
159.233 Lecture 1 - 22
RS Flip-flop
S
Consider what happens when S and R are both 0

If Q is 0:
the top NOR will have 0 0 as inputs and will output 1
the bottom NOR will have 1 0 as inputs and will output 0
=> the state is stable
if Q is 1:
the top NOR will have 0 1 as inputs and will output 0
=> the state is stable
If S is switched to a 1
the top NOR will have 1 X as inputs and will output 0
=> Q is forced to be a 1 (S stands for Set)
If R is switched to a 1
the bottom NOR will have 1 X as inputs and will output 0
=> Q is forced to be a 0 (R stands for Reset)
159.233 Lecture 1 - 23
RS Flip-flops are useful for switch debouncing.
Vcc
Switches make and break several times while in close contact.
Vcc
Q will be Set to 1 if switch makes contact with S

Q will stay at 1 despite make/breaks on S until switch touches R
159.233 Lecture 1 - 24
Circuits can use a clock to provide timing pulses. Logic levels can be
read on the clock pulse, which is allowed to go high only when glitches
are unlikely.
The RS Flip-flop can be clocked.
Clock
Q
The output of the AND gates will only reflect S and R when the Clock is 1
When the Clock is 0 the outputs of the AND gates are always 0
The X output of a RS Flip-flop is normally
One problem with the RS Flip-flop is what happens when R and S are 1.
Q 0 !
In this state the only stable state is both Qand
If both R and S return to 0 simultaneously Qjumps to 1 or 0 at random

otherwise Qwill reflect which one returned to 0 last.
159.233 Lecture 1 - 25
Clocked D Flip-flop
The D flip-flop removes this ambiguity
D
Q
Clock
Q
The Clock can now be considered a Strobe. A single clock pulse.
When the strobe is high, the value of D will be transferred to Q
Q will remain at that value until the strobe returns to a high state.
The D Flip-flop acts as a simple 1 bit memory.
As described, this type of flip-flop is level triggered. It depends on the
strobe or clock being in a high state.
In practice this is not so desirable. It is better to transfer the value of D to
the flip-flop when the strobe changes from a 0 to a 1
This is called edge triggered.
Edge triggered flip-flops are far more common.
They can be either 0>1 rising edge, or 1>0 falling edge
Clock
159.233 Lecture 1 - 26
Clocked J-K Flip-flop

Rather than removing the ambiguity of the RS flip-flop as in the D flipflop, the J-K flip-flop makes use of it.
J is equivalent to s.
K is equivalnet to R.
When J=1 =>Q becomes 1

When K=1 =>Q becomes 0
When J=K=1=>Q becomes
The J-K flip-flop toggles the output when J=K=1.

Given a regular clock and J=K=1 the Q output will be a clock with half the
frequency.
159.233 Lecture 1 - 27
Register
We construct a register by connecting together a group of D flip-flops
Data
in
D Q
D Q
Q3
D Q
Q2
D Q
Q1
Q0
All the flip-flops load simultaneously from the data in lines
159.233 Lecture 1 - 28
Bus
A bus is a common set of wires connecting multiple devices together.
Buses are used to connect the data and address lines between computers, memory
and i/o devices.
One problem with normal logic components is that their outputs are always active either a 1 or a 0 (5V or Gnd).
If we connect the output of two gates together, where one output is a 0 and the other
is a 1, then the result will be somewhere in between
If we want to use a bus architecture we must make sure that only one device at a
time outputs a logic signal of 0 or 1
All other devices must go into a high impedance state
ie they look like they are not connected at all.
Tri-state devices have this capability.
A tri-state device is like a normal gate but with the added capability of going into this
off-line mode.
In tri-state devices the OE output-enable line drives the outputs into this third state
rather than into the 0 logic state as previously.
Not all devices are tri-state. To connect these devices to a bus we need to put a tristate driver chip in between the device and the bus.
A tri-state driver just sends its input to its output, but also has an OE input to allow the
output to go not connected.
OE
RAM - Random Access Memory

Static memory is an array of D flip-flops.
The access time is the same for all bits in the array.
159.233 Lecture 1 - 29
Most memory chips are 1 bit wide, a byte is 8 chips side-by-side.
1stchip
3rdchip
etc..
2ndchip
(Some memory chips are several bits wide - normally a power of 2)
The desired bit is selected by the use of address lines.
159.233 Lecture 1 - 30
A typical memory device - 1 bit wide

CS
R/W
Data
Address
CS Chip Select line acts as an Enable line to the chip

The
(when several banks of chips are being used)
and also to tri-state the Data line depending on how it is being accessed
W determines whether the memory is written to or read from.
The R/
When memory is being read the Data line acts as an output
159.233 Lecture 1 - 31
Write access to memory

We need to:
select 1 flip-flop
perform the write on a clock pulse
the pulse must arrive after the chip is selected and a write operation
specified.
Use a decoder and the address lines to select a particular flip-flop
AND this signal with the
in.
CS ,
W to act as a clock to strobe the data

R/
Datain
D
Decoder
A0 A1
R/W
CS
159.233 Lecture 1 - 32
Read access from memory

Datain
D Q
D Q
D Q
mux
Data
out
D Q
Decoder
A0A1
A0 A1
R/W CS
Place the correct bit on the output line by using a multiplexor
CS , R/
W to enable a tri-state buffer.
Use the
159.233 Lecture 1 - 33
1Mb Memories
We can make the above memory larger by making it Byte wide rather
than bit wide.
This just means we have to copy 8 times the flip-flop column and its
associated data in and data out lines.
The lines from the decoder and CS/RW logic go to each of the flip-flop
columns.
For large Bit wide memories, we soon run into large numbers of pins to
connect to the chip.
1Mbit needs:
20 address lines
1
data line
1
CS line
1
R/W line
2
power/ground
The decoder within the chip will need 1 million output lines!
To get round these problems, we arrange the memory as a 2 dimensional
grid, 1024 x 1024 elements.
We use 2 decoders and send the address in 2 chunks - the row and
column addresses.
1Mbit now needs:
10 address lines
1
data line
1
CAS/RAS strobe (column/row strobe)
1
CS line
1
R/W line
2
power/ground
The 2 decoders now have only 1024 lines each as outputs.
Shift Registers
159.233 Lecture 1 - 34
Contain several flip-flops in a row. One bit is input at one end on each
clock pulse. Each other bit moves one place to the right (or left). The
outputs of each flip-flop are available simultaneously.
Q3
Data
Q2
D
Q1
D
Q0
D
Clock
We can use shift registers for serial to parallel conversion. Input 8 bits on
8 pulses, then read data simultaneously.
Division by 2
We can use the above principle to implement a divide by 2 circuit.
In the parallel load register (lecture 4) we can use an extra control line
load
shift/
to determine whether the input to a flip-flop comes from the data lines or
from the previous flip-flop (the left-most flip-flop gets a 0 in shift mode)
(use the control line as the address of a 2 input multiplexor, the output is
connected to the input of the flip-flop)
Try this as an exercise.
(design your own 2 input mux using AND/OR gates)
159.233 Lecture 1 - 35
Multiplication by 2
Multiplication can be done by shifting to the left.
Higher powers of two can be done by shifting several times.
An extra flip-flop can be added to the ends of the chain.
In the case of division by 2, this flip-flop will contain the remainder.
In the case of multiplication the flip-flop will flag whether an overflow has
occurred.
The 74LS75B is a parallel load/shift right register 4 bits wide, which (with
external assistance) can do shift left as well.
159.233 Lecture 1 - 36
Counters
Add one to the current number.
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
For the low order bit:

just swap between 0 and 1 - ie it toggles
For higher order bits:
the nth bit toggles when the n-1th bit changes from 1 to 0
Use a J-K flip-flop (falling edge triggered) as a toggle.
CLK
Q
Use the Qn-1 output as a clock to the Qn flip-flop
5v
CLK
K
Q0
K
Q1
K
Q2
Q3
159.233 Lecture 1 - 37
CLK
Q0
Q1
Q2
This is an ideal case - unfortunately the output of a flip-flop, like any gate, is slightly
delayed with respect to a changing input.
So the toggling of Q1 will be delayed by a few nanoseconds.
Q2 will only toggle on a change in Q1 so it will be delayed by twice the amount.
This effect will keep on compounding.
These glitches can have quite a disturbing effect.
Consider the case when the counter is at 0111
At the next pulse we would expect the counter to show 1000
However because of the delays the following patterns will all occur
0110
Q0 changes but Q1 hasnt caught up yet
0100
Q1 has now changed but Q2 is still to flip over
0000
Q2 now has reacted but Q3 is still to change
1000
eventually we get the right answer.
Circuits can be designed so that this ripple effect can be safely ignored,
However it is possible to design a counter that changes all the gates
simultaneously.
159.233 Lecture 1 - 38
Synchronous Counters
We cannot use the preceding bit as a pulse.
The same pulse must be used for each flip-flop.
How do we know when to toggle a flip-flop?
The synchronous counter uses the following fact:
a bit will toggle if all the low-order bits in the previous state are 1
5v
J
K
J
K
Clock
Flip-flops toggle at the same time - but only if J-Ks are high.
J-Ks are formed by ANDing the output of the previous bits.
Because the new output comes after the toggle by a few nanoseconds
The new state is not involved in any of the inputs
The AND gates are sampling the previous state.
We are deliberately using to our advantage the gate delay time.
159.233 Lecture 1 - 39
Synchronous up-down counter

As an exercise create a synchronous down counter.
Q output)
(remember that the J-K flip-flop also has a
Using a control line

down
up/
we can also create a synchronous up-down counter try it!
Algorithmic State Machines (ASMs)

The functionality of complex machines is divided into two parts:
An architecture -
details of the components that perform

actions, and their interconnections
A controller -
instructs the architecture to perform particular

actions, and when to do them.
Architectures can be of many different types:

Digital
eg a CPU
Mechanical
eg a lift
Electrical
eg a set of traffic lights
Hydraulic etc
For a computer processor:
159.233 Lecture 1 - 40
commands
Controller
processor
status
memory
Machine instructions are stored in the memory

The controller executes a loop performing these actions:
tell the processor to fetch an instruction from memory
tell the processor to perform the actions requested by the instruction
159.233 Lecture 1 - 41
status lines contain:

The instruction
Other status information eg
Z flag
NEG flag
OVFL flag
which will give the state of the accumulator after the instruction
Using these status flags the controller can follow different paths through
the program
command lines allow the controller to perform specific actions

The processor architecture will contain specific logic elements eg
registers
multiplexors
adders
Command lines will control these devices:
Load a register
Output enable a register
Select a multiplexors input
Read/write enable memory
159.233 Lecture 1 - 42
The controller is implemented as a state machine
Z
F
Q
Each state starts in a square box and lasts until you reach the next
square box.
159.233 Lecture 1 - 43
State0
State1
T
Z
F
Q
State2
Everything within a state happens simultaneously

States can be numbered arbitrarily but it makes sense to try and keep to
some pattern and to label the most common state 0
Command lines (outputs), listed in the square boxes, are true (1) when
the controller is in that state false (0) otherwise.
Status lines (inputs) are tested in diagonal boxes. The two paths leading
away from the test will be labelled with either T or F.
Outputs listed in rounded boxes are only asserted if that path is taken.
The state machine goes from one state to another on the tick of a clock.
159.233 Lecture 1 - 44
How to implement an ASM:

1.
Use a register to store the present state number
2.
Use some combinatorial logic to calculate what the next state

should be.
3.
On the tick of the clock transfer that new state into the register
4.
repeat indefinitely
The register stores the number of the current state.

How many bits does it take to store a state?
If there are 2 states we only need 1 bit wide register
0
1
>
>
0
1
if there are 4 states we will need a 2 bit wide register

0
1
2
3
>
>
>
>
00
01
10
11
if there are 8 states we will need a 3 bit wide register

0
1
>
>
000
001
etc
If we have seven states we will have to use 3 bits - one of the states will
never occur.
159.233 Lecture 1 - 45
status
inputs
combinatorial
logicfornext
state
current
state
Register
outputs
next
state
clock
We have a practical problem when we first start the machine:

Which state will it start in?
To make sure we dont start in a state that could lead to self-destruction,

we make sure we always start in state 0
This is achieved by holding a Reset line high when power is first applied,
removing the Reset only after a little time has elapsed
Controlling the states in an ASM

The current state is stored in a register (a set of D flip-flops)
The next state is the result of combining the previous state with the
inputs lines and status lines of the ASM.
We can draw up a table of current state / inputs / status / next state
159.233 Lecture 1 - 46
State0
State1
T
Z
F
Q
State2
159.233 Lecture 1 - 47
Current state
AB
0
00
1
2
In state 0
Next state
AB
1
01
2
10
0
00
0
00
01
10
Condition
Z
Z
the B flip-flop
the A flip-flop
->
->
In state 1
the B flip-flop
the A flip-flop
->
->
0
0
In state 2
the B flip-flop
the A flip-flop
->
->
0
0
We could use a combination of logic gates to generate our new state but this gets very messy for large numbers of states / inputs.
A very neat way of solving the problem is to use table look-up
Given our present state look it up in a table and read off the new state.
A multiplexor acts as a table look up.
T F
T F
1
2
1
2
1 0
1 0
Current state
159.233 Lecture 1 - 48
We will need to include the Z input for the 0 state:
ZZT F
ZZT F
0 or 1
1
2
1 or 0
1
2
0 0
0 0
Current state
Our complete look up table looks like this:
ZZT F
ZZT F
New A
1
2
New B
1
2
AB
AB
Current state
Notice that although state 3 doesnt exist we make it go to state 0.

Inputs will in general be some combination of logic symbols.
159.233 Lecture 1 - 49
Output signals
There are two standard ways of generating output signals from an ASM.
One way or the other will normally involve less chips.
Use one mux chip for each output.
Feed the current state into the mux. For each of the possible states use
the correct inputs to give the desired output signal.
ZZT F
1
2
3
AB
Use a decoder chip on the current state.
Z
0
Decoder
B
2
3
A more complicated ASM

159.233 Lecture 1 - 50
00
01
F
X
T
Y
F
11
10
T
W
F
Z
T
Current state
AB
0
00
1
2
3
01
10
11
Next state
AB
1
01
2
10
3
11
0
00
2
10
0
00
0
00
2
10
3
11
Condition
XY
XY
W
T
ZX
ZX
Z
159.233 Lecture 1 - 51
In state 0
the B flip-flop
the A flip-flop
->
->
X Y+X
In state 1
the B flip-flop
the A flip-flop
->
->
F
W
In state 2
the B flip-flop
the A flip-flop
->
->
F
F
In state 3
the B flip-flop
the A flip-flop
->
->
X Y +X
ZX+Z
>
>
X+Y
X+ Y
>
X+ Z
XYZT F
0
1
New B
2
3
WXY ZT F
AB
Current state
0
1
New A
2
3
AB
Current state
159.233 Lecture 1 - 52
A Multiplication Circuit
Phase 1:
Analyse the problem in terms of its inputs
Generate an architecture
Phase 2:
Design a controller (ASM)
Think in terms of normal long multiplication - but in binary not decimal

0111
multiplicand
x1010
multiplier
0000
0111 partialproducts
0000
0111
01000110
product
This way is not satisfactory:
We have to remember all the partial products before we can sum them to
get the final product -> we would need lots of registers
Instead we can keep a running total in a single register.
If the multiplicand and multiplier are each n bits wide, the running total
needs to be 2n bits wide.
159.233 Lecture 1 - 53
Multiplier
1. Start the running total with the multiplier in the low order bits.
2. Increment a loop counter.
3. Check the state of the lowest bit.
4. If it is a 1 add the multiplicand to the high order bits of the total.
5. Shift the running total 1 bit to the right.
6. Repeat from 2 until the loop counter gets to n.
The multiplier has now disappeared from the total.
The total itself has the first terms in the addition shifted down to the low
order end
ie
Counter
1
00001010
>
Low
Bit
0
>
00000101
>
>
00111010
>
>
00011101
>
>
01000110
>
Add
00000101
01110000
01110101
00011101
01110000
10001101
Shift
>
00000101
>
00111010
>
00011101
>
01000110
answer
159.233 Lecture 1 - 54
Loworder
result
Highorder
result
LOBIT
carry
LDPROD
SHIFT
SRA
LDMPL
R
RSTA
SRB
carry
Multiplier
Adder
INCR
CLRCNT
2bit
Counter
EQZ
Multiplicand
159.233 Lecture 1 - 55
00
CLRCNT
F
START
T
LDMPLR
RSTA
01
INCR
LOBIT
10
LDPROD
F 11
SHIFT
EQZ
T
DONE
Current state
AB
0
00
1
2
3
01
10
11
Next state
AB
0
00
1
01
2
10
3
11
3
11
0
00
1
01
Condition
START
START
LOBIT
LOBIT
EQZ
EQZ
159.233 Lecture 1 - 56
LDMPLR
RSTA
START
0
Decoder
B
2
3
EQZ
CLRCNT
INCR
LDPROD
SHIFT
DONE
START LOBIT EQZ EQZ T F
NewA
1
2
3
A B
0
NewB
1
2
3
B
A B
2bit
register
Designing a Computer
von Neumann model
general purpose architecture
programmed by stored instructions
159.233 Lecture 1 - 57
linearly addressed memory

program and data stored in memory
results generated into an accumulator by an ALU
The Pico-computer architecture

WEMEM
OEMEM
Bus
OEPC
Tristate
buffer
ProgramINCPC
counter LDPC
OECONST
Tristate
buffer
OEACC
Tristate
buffer
LDACC Accumulator
CO/C1
const
mux
OEPORT
Tristate
buffer
Memory
InputPort
zero EQZ
detect
Arithmetic
LogicUnit
LDABR ABuffer
Register
xor
invertor
sub
LDMAR Memory
Address
Register
Program Counter
PC
keeps track of current instruction
Arithmetic/logic
ALU
performs data manipulations - add/sub
Accumulator
Acc
temporary store for results of ALU
Input port
IO
interfaces to outside world
Const mux
easy access to the constants 0 and 1

159.233 Lecture 1 - 58
Buffer register
Memory address
register
ABR
buffer for the ALU
EQZ
TRUE if accumulator is zero
MAR
select a particular address in memory
Memory
256 8 bit bytes
Bus
8 bits wide
159.233 Lecture 1 - 59
Design of the ALU

Accepts two numbers from the Bus
Calculates sum or difference - specified by the controller
Stores result in accumulator
Addition:
Acc
LDACC
Adder
LDABR
ABR
Use an 8 bit adder

Put one operand on the Bus, assert LDABR to store it in ABR
Put other operand on the Bus
Load result of adder in accumulator by asserting LDACC
159.233 Lecture 1 - 60
Subtraction:
a
using 2s complement notation =>

a
(2scomplement)b
2scomplementb
complementb
Use an Exclusive OR gate as a programmable complementor:

s
0
0
1
1
b
0
1
0
1
EOR
0
1
1
0
When s=0 the output is b

b
When s=1 the output is
so for a b that is 4 bits wide:

complement
enable
borb
159.233 Lecture 1 - 61
To subtract use the subtract control line as a complement enable

and also as a Carry in to the adder => complement + 1
LDACC
Acc
Adder
LDABR
ABR
EOR
array
sub
We now need to add a zero detect circuit to the Accumulator, and a tristate gate to attach the accumulator to the Bus.
zero detect:
EQZ
Accumulator
159.233 Lecture 1 - 62
The complete ALU with signals that the controller needs
OEACC
Tristate
buffer
zerodetect
LDACC
Acc
Adder
LDABR
ABR
EQZ
EOR
array
sub
The Controller
The controller is an ASM that implements the instruction set of the
computer
When the power is first turned on, and after each instruction has
completed the controller:
uses the value in the PC to address memory
the value at that memory location is the next instruction
issues a sequence of signals to the architecture corresponding
to the instruction
The input signals to the controller are:
159.233 Lecture 1 - 63
The current instruction

EQZ
The output signals generated by the controller are:
LDABR
sub
LDACC
OEACC
OECONST
C0/C1
OEPC
RESET
LDPC
INCPC
WEMEM
OEPORT
OEMEM
LDMAR
DISABLE
load a buffer register

subtract instead of add
load the accumulator
output enable the accumulator
output enable the constant
select between constant 0 or 1
output enable the Program Counter
reset line to gates
load the PC
increment the PC
write enable memory
output enable the I/O port
output enable memory
load memory address register
disables the clock (user re-enables it)
159.233 Lecture 1 - 64
Instruction set
The pico-computer only has 8 instructions:
0
LDA operand
Load value at location operand into Acc
ADD operand
Add value at location operand to Acc
SUB operand
Subtract value at location operand from Acc
STA operand
Store value in Acc at location operand
JPZ operand
If value in Acc is 0 jump to operand

otherwise proceed to next instruction
IN
Input a number from I/O port
CLR
Load accumulator with 0
HLT
Halt the clock
So a set of instructions to input three numbers and add them together is:
5
input number to acc
3 100
store acc to location 100
input number to acc
3 101
store acc to location 101
input number to acc
1 101
add value from location 101
1 100
add value from location 100
Halt
159.233 Lecture 1 - 65
Instructions in detail
For all these instructions we may assume that the PC has already been
incremented
LDA operand
Algorithm:
LDA
Output enable const mux (0) onto bus
OECONST
LDABR
Load bus (0) into ABR

2
3
4
Load MAR with location of address of operand
OEPC
LDMAR
INCPC
Load MAR with address of operand
OEMEM
LDMAR
Output enable memory
OEMEM
LDACC
Load Acc with sum of ABR (0) and bus
159.233 Lecture 1 - 66
1
ADD operand
Algorithm:
ADD
Output enable accumulator onto bus
OEACC
LDABR
Load bus (accumulator) into ABR

2
Output enable memory

Load Acc with sum of ABR (accumulator) and
bus
OEPC
LDMAR
INCPC
OEMEM
LDMAR
OEMEM
LDACC
2
SUB operand
Algorithm:
SUB
OEACC
LDABR
Load bus (accumulator) into ABR

2
Output enable memory onto bus

Load Acc with sum of ABR (accumulator) and
bus
OEPC
LDMAR
INCPC
OEMEM
LDMAR
OEMEM
LDACC
SUB
Subtract line enable
159.233 Lecture 1 - 67
3
STA operand
Algorithm:
STA

Write-enable memory
OEPC
LDMAR
INCPC
OEMEM
LDMAR
OEACC
WEMEM
4
JPZ operand
Algorithm:
JPZ
Load PC into MAR

increment PC in case jump doesnt occur
Output enable memory (operand) onto bus
OEPC
LDMAR
INCPC
OEMEM
EQZ
If EQZ (accumulator contents) enable LDPC

to load operand into PC
T
LDPC
159.233 Lecture 1 - 68
5
IN
Algorithm:
1

Halt the clock

Output enable the I/O port onto the bus
IN
OECONST
LDABR
OEPORT
LDACC
DISABLE
Load the accumulator with the sum of ABR (0)

and the value from the I/O port
wont take effect until user starts clock
6
CLR
Algorithm:
1

CLR
OECONST
LDABR
OECONST
LDACC
Load the accumulator with the sum of ABR (0)

and the value on the bus (0)
7
HALT
Algorithm:
1
Disable the clock
HALT
DISABLE
Simple ASM for the Pico-computer

159.233 Lecture 1 - 69
0
OEPC
LDMAR
INCPC
1
OEMEM
LDIR
INSTR
LDA
2 ADD
6 SUB 10
OECONST OEACC
OEACC
LDABR
LDABR
LDABR
3
OEPC
LDMAR
INCPC
OEPC
LDMAR
INCPC
8
4
OEMEM
LDMAR
11
OEPC
LDMAR
INCPC
STA
14
OEPC
LDMAR
INCPC
JPZ
19
IN 21
CLR
OECONST OECONST
LDABR
LDABR
HALT
17
OEPC
LDMAR
INCPC
12
15
18
OEMEM
OEMEM
OEMEM
OEMEM
LDMAR
LDMAR
LDMAR
13
16
5
9
OEMEM
OEMEM
OEACC
OEMEM
LDACC
LDACC
WEMEM
LDACC
SUB
EQZ
T
LDPC
20
OEPORT
LDACC
DISABLE
23
OECONST DISABLE
LDACC
22
159.233 Lecture 1 - 70
This ASM is straight forward, but it contains 24 states!

There are a lot of duplicates!
We can simplify the number of states
We also have a problem...
How do we get our program into the memory in the first place?
We need some extra hardware.
A toggle switch connected to the control line PLOAD (program load)
3 further switches:
Load address
Increment addr
Load memory
(together with our I/O port to enter the actual codes)
8 state ASM incorporating program load commands:
159.233 Lecture 1 - 71
0
RESET
1
OEPC
LDMAR
INCPC
7
DISABLE
PLOAD
ACTION
PLOAD
n
2
none
load
addr
OEMEM
LDIR
OEPORT
LDMAR
INSTR
hlt
inc
addr
INCMAR
load
memory
OEPORT
WEMEM
sta+jpz
lda+add+
3
sub+in+clr
LDABR
INSTR
lda
OECONST
in+clr
OECONST
add+sub
OEACC
4
OEPC
LDMAR
INCPC
5
OEMEM
JPZ
LDMAR
6
EQZ
y
?
pload.hlt
clr
sub
sta
pload.in
lda+add
SUB
DISABLE
OECONST
LDACC
OEMEM
LDACC
OEPORT
LDACC
DISABLE
OEACC
WEMEM
LDPC
159.233 Lecture 1 - 72
ASM transition table

Currentstate
ABC
Nextstate
ABC
Condition
000
001
001
2
7
010
111
pload
pload
010
3
6
4
011
110
100
lda+add+sub+in+clr
hlt
sta+jpz
011
4
6
100
110
lda+add+sub
in+clr
100
101
101
6
1
110
001
jpz
jpz
110
001
111
0
7
000
111
pload
pload
159.233 Lecture 1 - 73
State0
A
B
C
=
=
=
false
false
true
A
B
C
=
=
=
pload
true
pload
A
B
C
=
=
=
hlt+sta+jpz
hlt+lda+add+sub+in+clr
lda+add+sub+in+clr
A
B
C
=
=
=
true
in+clr
false
A
B
C
=
=
=
true
false
true
A
B
C
=
=
=
jpz
jpz
A
B
C
=
=
=
false
false
true
A
B
C
=
=
=
pload
pload
pload
State1
State2
State3
State4
State5
jpz
State6
State7
159.233 Lecture 1 - 74
databus
instregister
decoder
T F
0
1
2
NewA
3
4
5
6
7
A BC
0
1
2
NewB
3
4
5
6
7
A BC
0
1
2
NewC
3
4
5
6
7
A BC
la ss j
dd ut p
ad ba z
ich
nll
rt
p
l
o
a
d
A
B
C
3bit
register
159.233 Lecture 1 - 75
Microprogramming
The Pico-computer uses hardware to implement its controller.
Combinations of status lines are used to create the next state of the
ASM, and multiplexors choose between them given the current state.
The muxs are performing a table-lookup
- a job that could just as easily be performed by a ROM.
- The Microprogrammed approach.
Benefits:
If the instruction set needs to be altered, or corrections made, it is a lot
easier to change a ROM, than to change or add to the combinatorial logic
of the hardwired approach.
A processor can be made to look like, emulate, another processor, by
changing the micro-code, an instruction set of another processor can be
implemented (as long as the architecture is compatible).
Extra instructions can be implemented depending on the type of program
the processor is executing.
If the program is heavily maths based, we could implement one
instruction that performs a Fast Fourier Transform on a set of numbers.
If its text based, we could implement a strcpy instruction that performs a
block move of data.
In both these instances we are only invoking 1 instruction instead of
many. So the total cycle time will be reduced because of the smaller
number of instruction fetches. (Data fetches and ALU operations will be
the same)
159.233 Lecture 1 - 76
Micro-program controller
processor
control
line
s
Bus
opcode
ROM
nextaddr
condition
select
addr
out
opcode/
nextaddr
in
program ld/
inc
counter
F
T
EQZ
Clock
There is no longer an instr register. The -controller loads the opcode
from the Bus when necessary into its own program counter.
The -program counter is reset to zero on power up.
-addr - initially points to address 0 of -ROM.
-ROM contains a sequence of data bytes.
These data bytes appear as output and control lines:
processor control lines
condition select
next -addr
opcode/(next -addr)
159.233 Lecture 1 - 77
The -PC is fairly complex:

The data stored in the counter can be either:
incremented if LD/(INC) is False
or:
loaded from in if LD/(INC) is True
If LD is True, then the PC is either:
next -addr coming from ROM
or:
the next opcode coming from the Bus
Depending on whether opcode/(next addr) is 1 or 0
The data stored in the counter changes on a clock tick.
out addresses ROM.
159.233 Lecture 1 - 78
Inside the ROM:
O
E
P
-addr cond opcode next C
sel /addr addr
0
1
.
8 .
goto fetch
1
1
.
10 .
goto LDA
2
1
.
14 .
goto ADD
3
1
.
18 .
goto SUB
4
1
.
22 .
goto STA
5
1
.
25 .
goto JPZ
6
1
.
29 .
goto CLR
7
1
.
31 .
goto HLT
fetch 8
0
.
1
mar=pc
9
1
1
.
+; goto Bus
lda 10
0
.
.
abr=0
11
0
.
1
mar=pc; pc++
12
0
.
.
mar=m[mar]
13
1
.
8 .
a=abr+m[mar]; goto fetch
L
D
P
C
I
N
C
P
C
O
E
C
O
N
S
T
O
E
A
C
C
L
D
A
C
C
L
L O
D
D E
A S M M
B U A E
R B R M
W
E
M
E
M
D
I
S
A
B
L
E
. . . . . . . . . . .
. . . . . . . . . . .
. . . . . . . . . . .
. . . . . . . . . . .
. . . . . . . . . . .
. . . . . . . . . . .
. . . . . . . . . . .
. . . . . . . . . . .
. . . . . . . 1 . . .
. 1 . . . . . . 1 . . pc+
. . 1 . . 1 . . . . .
. 1 . . . . . 1 . . .
. . . . . . . 1 1 . .
. . . . 1 . . . 1 . .
159.233 Lecture 1 - 79
O
E
P
-addr cond opcode next C
sel /addr addr
add 14
0
.
.
abr=a
15
0
.
1
mar=pc; pc++
16
0
.
.
mar=m[mar]
17
1
.
8 .
a=abr+m[mar]; goto fetch
sub 18
0
.
.
abr=a
19
0
.
1
mar=pc; pc++
20
0
.
.
mar=m[mar]
21
1
.
8 .
a=abr-m[mar]; goto fetch
sta 22
0
.
1
mar=pc; pc++
23
0
.
.
mar=m[mar]
24
1
.
8 .
m[mar]=a;goto fetch
jpz 25
0
.
1
mar=pc; pc++
26
2
.
28 .
if EQZ goto 28
27
1
.
8 .
goto fetch
28
1
.
8 .
pc=m[mar];goto fetch
clr 29
0
.
.
abr=0
30
1
.
8 .
a=abr+0;goto fetch
hlt 31
1
.
8 .
disable;goto fetch
L
D
P
C
I
N
C
P
C
O
E
C
O
N
S
T
O
E
A
C
C
L
D
A
C
C
L
L O
D
D E
A S M M
B U A E
R B R M
W
E
M
E
M
D
I
S
A
B
L
E
. . . 1 . 1 . . . . .
. 1 . . . . . 1 . . .
. . . . . . . 1 1 . .
. . . . 1 . . . 1 . .
. . . 1 . 1 . . . . .
. 1 . . . . . 1 . . .
. . . . . . . 1 1 . .
. . . . 1 . 1 . 1 . .
. 1 . . . . . 1 . . .
. . . . . . . 1 1 . .
. . . 1 . . . . . 1 .
. 1 . . . . . 1 . . .
. . . . . . . . . . .
. . . . . . . . . . .
1 . . . . . . . 1 . .
. . 1 . . 1 . . . . .
. . 1 . 1 . . . . . .
. . . . . . . . . . 1
159.233 Lecture 1 - 80
Example - Instruction: LDA 100 at location 0.

-addr
0
CS = 1
op/n = 0
Next addr = 8
Condition
opcode/
Next
Select
(next addr)
address
1
0
8
=>
LD is True; -PC will load data
=>
Data will come from Next addr
=>
The -PC will be 8 next clock tick
8
LDMAR;OEPC
CS = 0
0
=>
=>
0
0
mar = pc (=0)
-PC will inc to 9 on next clock tick
9
INCPC;OEMEM
CS = 1
op/n = 1
Bus = 1
1
=>
=>
=>
=>
1
0
pc =1; Bus = mem[0]; (Bus=LDA = 1)
Data will come from Bus/opcode
-PC will be 1 on next clock tick
1
CS = 1
op/n = 0
Next addr = 10
1
=>
=>
=>
0
10
10
0
LDABR;OECONST =>
CS = 0
=>
0
0
Bus = 0; abr = Bus; (abr=0)
11
0
OEPC;INCPC;LDMAR
CS = 0
=>
0
0
mar = pc (mar = 1); pc++; (pc = 2)
=>
12
OEMEM;LDMAR
CS = 0
0
=>
=>
0
0
mar = m[mar] (mar = m[1] = 100)
13
OEMEM;LDACC
CS = 1
op/n = 0
Next addr = 8
1
=>
=>
=>
=>
0
8
acc = abr + m[mar] (acc = 0 + m[100])
159.233 Lecture 1 - 81
This type of ROM organisation is called Horizontal Microprogramming.

In the pico-computer there are 32 -instructions and each instruction
contains 12 control lines.
These numbers are manageable. But a processor with 200 control lines
and 4096 -instructions would require ~1Mbit of ROM.
This ROM has to be very fast and so is expensive.
One way of reducing the size of ROM is to consider how many output bits
are active at any one time.
In the pico-computer there are 12bits of output so in theory there could
be 212 different combinations.
In practice the ROM consists of common combinations of outputs, indeed
there are only ~13 different outputs.
We can reduce the size of the ROM by encoding these 13 different
outputs as a 4bit number, and decoding this number to generate the
correct outputs
This is called Vertical Microprogramming - 200 control lines may be
encoded using only 6 bits:
12
6
4096
decoding
circuit
200
ROM
control
lines
159.233 Lecture 1 - 82
Vertical Microprogramming
This considerably reduces the amount of ROM needed, but at a cost the hardware for the decoding circuit is fixed and so we lose some of the
benefits of being able to program at this level.
One solution to this is to replace the decoding circuit by yet another ROM
- nano-ROM.
Use table lookup to generate the control lines
6
nanoROM
200bitx64
12
6
4096
200
ROM
control
lines
We again have complete control over this programming level.

We have saved on ROM together both ROMS need only ~35Kbits.
-ROM and nano-ROM can be replaced without having to do any
hardware alterations.
One drawback is that ROM now needs to be twice as fast - as we are
now doing two table lookups instead of one.
Construction of an ALU.
The picocomputer has a very primitive ALU. It consisted of just an Adder
with the ability to subtract using 2s compliment arithmetic. There was no
Logic in it at all!
159.233 Lecture 1 - 83
The symbol for an ALU is normally written:

A
4bitALU
Carryout
Function
Where the Function input selects the desired combination of the two
inputs.
If the Function input consists of 2 control lines, 4 functions are
possible:
eg:
00 Add
C = A + B
01 Subtract
C = A - B
10 And
C = A and B
11 Or
C = A or B
If we increase the number to 3 control lines then further functions (8 in
total) are possible - eg Xor
159.233 Lecture 1 - 84
ALUs are constructed by creating each of the functions separately, and

then using a multiplexor to select the desired output. The Function
input is used for the input address lines of the mux.
sub
A
add
sub
C
and
or
function
This ALU can be constructed using a 74153 4-input mux, a 7483 4-bit
adder, and and or gates. The subtract function needs a little work. It has
to generate the inverse of B, and the carry-in signal to the adder, as well
as being used by the address lines of the mux.
f0
carry in
sub
f1
B0
159.233 Lecture 1 - 85
Adders
There is one small problem with designing an n-bit adder. It is normal to
design a 1-bit adder and then use n of them to handle n-bits - a ripplecarry adder
carry in
sum
carry out
The problem is to do with the carry. Every time a signal has to go

through a gate, it incurs a small delay. This gate delay is ~5 ns. The
adder itself can be made from 2 levels of gates. The first level is an and
array, this is then fed into the second level which is an or array.
To add 2 bits together takes 2 gate delays.
If we chain several 1-bit adders together to make an n-bit adder, we have
to wait a considerable time for the carry out to propagate through. The
carry out takes 2-gate delays for each single adder, and so will take 2*n
gate delays to appear at the final bit.
For a 32-bit adder this will increase the time from 10ns to 320ns - 32
times slower!
159.233 Lecture 1 - 86
It is possible to speed up this process. Indeed, it is always possible to

design a circuit that has only two levels of logic. But for a 32-bit adder,
this is extremely hardware intensive.
Cin1 (the carry in of bit 1 ) =
Cout0 (the carry out of bit 0)
Cout0
= (B0.Cin0) + (A0.Cin0) + (A0.B0)
=>
Cin1
= (B0.Cin0) + (A0.Cin0) + (A0.B0)
Cin2 (the carry in of bit 2) =

Cout1 (the carry out of bit 1)
Cout1
= (B1.Cin1) + (A1.Cin1) + (A1.B1)
= (B1.B0.Cin0) + (B1.A0.Cin0) + (B1.A0.B0)

+ (A1.B0.Cin0) + (A1.A0.Cin0) + (A1.A0.B0)
+ (A1.B1)
This complexity can be simplified somewhat, by substituting
gi = ai.bi
which is true if bit i of the adder generates a carry out independent of
carry in.
and
pi = ai+bi
which is true if bit i of the adder propagates a carry in to carry out.
c1
c2
c3
c4
=
=
=
=
g0
g1
g2
g3
+
+
+
+
+
(p0.c0)
(p1.g0) + (p1.p0.c0)
(p2.g1) + (p2.p1.g0) + (p2.p1.p0.c0)
(p3.g2) + (p3.p2.g1) + (p3.p2.p1.g0)
(p3.p2.p1.p0.c0)
159.233 Lecture 1 - 87
A carry is generated if carry in for some earlier bit is a one, and all
intermediate bits propagate a carry. This is called a carry-lookahead
adder
Now we have groups of 4-bits with the carry being handled as quickly as
the addition.
To extend this scheme to more than 4-bits we can either:
block them together as before and let the carry ripple through
a partial carry-lookahead adder
or
use a higher level carry lookahead on each block of 4-bits
P0 = p3.p2.p1.p0
G0 = g3 + (p3.g2) + (p3.p2.g1) + (p3.p2.p1.g0)
C1 = G0 + (P0.c0)
and similarly for C2, C3 and C4
159.233 Lecture 1 - 88
Multipliers - Booths Algorithm

Booth observed that if we allow the adder to subtract as well as add, we
can multiply numbers differently. When he invented this approach,
shifting right was quicker than adding. If the multiplier contains
sequences of 1s or 0s then we can reduce the number of additions.
Instead of just looking at the LOBIT of the shift register, we look at the
LOBIT and the 'previous LOBIT'
The new algorithm is now:
Depending on the LOBIT and previous LOBIT do one of the following:
00: Middle of a string of 0s - do nothing
01: End of a string of 1s - add the multiplicand to the high order
result
10: Beginning of a string of 1s - sub multiplicand
11: Middle of a string of 1s - do nothing
After this perform a one bit arithmetic right shift, and repeat n times.
An ASR shifts 1 bit to the right, but the high order bit inserted is the same
as the previous high order bit
eg
0111
1100
=>
=>
0011
1110
The very first previous LOBIT is 0.
159.233 Lecture 1 - 89
Example of 2 * 6
Multiplicand
0010
1
0010
0010
2
0010
0010
3
0010
0010
4
0010
0010
Step
Initial values
00: do nothing
ASR
10: sub mcand
ASR
11: do nothing
ASR
01: add mcand
ASR
Shift Regs
0000 0110 0
0000 0110 0
0000 0011 0
1110 0011 0
1111 0001 1
1111 0001 1
1111 1000 1
0001 1000 1
0000 1100 0
One side-effect of Booths algorithm is that it handles negative as well as

positive numbers.
Using the previous algorithm, it is necessary to remember the initial
signs, convert both numbers to be positive, and negate the final result if
the two initial signs were different.
Instruction set design

The Pico-computer has 7 instructions, LDA IN ADD etc, they are of
variable size the IN instruction is just a single byte, but LDA takes 2
bytes. They also take a variable number of clock cycles IN takes 2 less
cycles than LDA. They are also the idea of one person others might
have different ideas of what constitutes a good instruction set.
The controller specifies how the instructions are implemented by the
hardware and in general they follow 5 basic steps:
Fetch:
an instruction is brought into the control unit from memory.
Decode: The control unit decodes the instruction to determine the

sequence of events necessary to execute it.
Memory: Any data necessary for the instruction are fetched from
memory
Execute: The operation is performed
159.233 Lecture 1 - 90
Write:
Results of the operation may be written to memory
Each machine code, expressed in Assembler language contains:

OpCode
Operands
Addresses
the operation to be performed and

the rest of the instruction
some of the operands may be addresses of data
Eg
ADD
AX,[102]
The OpCode is ADD, there are two operands AX and [102], and one
address [102]
Assembler language syntax is specific to the processor, and varies
widely.
Types of instructions
Five address machines
Machines with only one instruction type:
If we need to put all the information necessary into a single instruction,
then it must contain the following:
OpCode Dest Addr, Src1 Addr, Src2 Addr, Cond Code, True Addr,
False Addr
5 addresses
e.g.
SUB
->
5 address machine
[0],[1],[2],NZ,4,5
Which subtracts the value stored at location 2 from that at 1 and stores
the result in 0. If the result is not zero, then the next instruction is at
location 4 otherwise the next instruction is at 5.
Some very early computers used this format, but it is not used today. It
has the disadvantage that all instructions are very big. Addresses are
normally 32 bits long, so the instruction will be ~160 bits long.
159.233 Lecture 1 - 91
We can make the instructions shorter if we allow ourselves two types of

instructions and 2 further registers:
159.233 Lecture 1 - 92
Three address machines

Machines with two instruction types.
Implement a Program Counter. If we order our program sequentially, then
the False Addr can be set to default to the next instruction (PC + 1).
Implement a Flags Register. Condition Codes set by one instruction are
remembered and can be tested by another.
The two instruction types are:
OpCode Dest Addr, Src1 Addr, Src2 Addr
OpCode Cond Code, True Addr
:Arithmetic/Logic instrs
:Control instructions
The longest instruction now has 3 addresses

e.g.
SUB
JNZ
[0],[1],[2]
4
159.233 Lecture 1 - 93
Two address machines

Three address machines still have a long instruction length (3 * 32 = 96),
we can cut out the Dest Addr by assuming it is the same as one of the
Src Addr.
This is often the case, but if it isnt we need to invent an extra operation
MOV.
We still have two types of instructions:
OpCode Dest/Src1 Addr, Src2 Addr
The longest instruction now has 2 addresses
machine
e.g.
MOV
SUB
JNZ
:Arithmetic/Logic instrs
:Memory/Memory move
->
2 address
[0],[1]
[0],[2]
4
Although this particular program is still the same length as the other two,
in general programs will be shorter as several ALU instructions performed
in sequence will only be ~64 bits. Shorter programs tend to be slower, but
this is not always the case.
159.233 Lecture 1 - 94
One address machines

Two address machines can be made even shorter, by implementing
special temporary locations within the processor Registers.
If there is only one register, its called the Accumulator. Several registers
are called either by their special function or by a more general R1, R2
etc. There will only be a few registers ~32 so they can be encoded using
only a few bits, rather than the 32 needed for memory.
We now have four types of instructions:
OpCode Dest/Src1 Addr, Src2 Reg
:Memory/Register moves
OpCode Dest/Src1 Reg, Src2 Addr
:Register/Memory moves
:Register/Memory ALU
The longest instruction now has 1 address -> 1 address machine

e.g.
MOV
SUB
MOV
JNZ
A,[1]
A,[2]
[0],A
4
159.233 Lecture 1 - 95
Zero address machines

We cant have instructions that do not access memory but we can
restrict the ALU operations to be Register/Register.
We now have four types of instructions:
OpCode Dest/Src1 Addr, Src2 Reg
:Memory/Register moves
:Register/Memory moves
OpCode Dest/Src1 Reg, Src2 Reg
:Register/Register ALU
e.g.
MOV
MOV
SUB
MOV
JNZ
A,[1]
B,[2]
A,B
[0],A
4
Often these machines are referred to as Load/Store. Only Registers are

involved with the ALU. Some processors allow 3 registers to be specified
for ALU operations, the MIPs processor that we will be looking at is one
of them.
159.233 Lecture 1 - 96
Stack machine:
One, final, zero address instruction set is for a stack based machine
PUSH
:Stack operation
POP
Src Addr
Src Addr
:Stack operation
e.g.
PUSH
PUSH
SUB
POP
JNZ
[1]
[2]
[0]
4
There are a few stack machines around today e.g. the Inmos
Transputer.
Addressing modes
The Pico-computer has one addressing mode: Direct.
lda 100
jnz 4
Each instruction contains an address.
Either the address is used directly for the jnz instruction, or the contents
of the address are transferred between memory and the accumulator.
There are several different assembler syntaxes for addresses
The pico-computer uses the address (a number) on its own. Another way
is to enclose the number in square brackets.
159.233 Lecture 1 - 97
We need to consider what addressing modes we would like the computer

to implement.
Direct Addressing:
add
a,[100]
The contents of location 100 are added to the Accumulator

byte x; /*x happens to be at addr 100*/
a += x;
159.233 Lecture 1 - 98
Immediate Addressing:
add
a,100
The value 100 is part of the instruction.

100 is added to the accumulator.
a += 100;
Register Addressing:
add
a,b
The operands of the instruction refer to specific registers.

The contents of register B are added to the accumulator
a += b;
Register Indirect Addressing:

add
a,[b]
The operands of the instruction refer to specific registers

Register b contains an address.
The contents of this address are added to the accumulator.
int x = 2;
b = &x;
a += *b;
159.233 Lecture 1 - 99
Register Indirect with Displacement Addressing:

add
a,[b+10]
The operands of the instruction refer to specific registers

Register b contains a number.
The desired memory address is 10 plus the contents of b.
byte x[20]; /*x is at addr 10*/
b = 5;
a += x[b];
Indexed Addressing:
add
a,[b+c]
Add the contents of b and c, use the address so formed.

byte array[10];
b = array;
c = 5;
a += b[c];
159.233 Lecture 1 - 100
Indexed with Displacement Addressing:

add
a,[b+c+10]
Add the contents of b, c and 10, use the address so formed.

struct {
byte k;
byte j;
} s[5]; /*address of s is 10*/
/*b is set to i*sizeof(s)*/
/*c is set to offset of j within s*/
a += s[i].j;
Memory Indirect Addressing:
add
a,@[100]
The contents of address 100 is another address.

byte x,*p; /*address of p is 100*/
p = &x;
a += *p;
159.233 Lecture 1 - 101
Register Indirect Addressing with auto-incr/decrement:

add
add
a,[b]+
a,-[b]
The contents of b is an address.

Afterwards b is incremented.
This addressing mode can be used in the absence of any explicit stack
instructions.
byte p[10];
b = p;
a += *b++;
159.233 Lecture 1 - 102
Instruction Size.
Instructions can be
either
variable in size e.g. the Pico-computer or Pentium,
or
of fixed length e.g. the MIPS processor or PowerPC.
Variable size instructions -> a program will take up less space.

Fixed sized instructions -> the processor can be made simpler - freeing
up space for more registers.
All instructions on the MIPs processor are 32 bits.
159.233 Lecture 1 - 103
MIPS.
RISC machines trade simplicity of processor v Registers.
The MIPs processor has fixed size instructions - 32 bits.
There are 32 registers but register $0 is reserved for the value 0
register $31 is the PC.
The MIPS architecture supports 4 addressing modes:

Register Addressing:
Register Indirect with Displacement Addressing:
Immediate Addressing:
PC Relative
159.233 Lecture 1 - 104
R type instructions:
ALU operations have three operands all of them registers
Opcode
6
add
rs
5
rt
5
rd
5
shamt
5
$1,$2,$3
sub-fct
6
bits
;$1 = $2 + $3
shamt is the shift amount

I type instructions:
Load/Store (the only instructions to access memory) and some branches
Opcode
6bits
lw
rs
5
rt
5
displ
16
$1,100($2)
bits
;$1 = mem[$2+100]
J type instructions:
Jump and procedure call.
Opcode
6bits
j
displ
26
10000
bits
;goto 10000
159.233 Lecture 1 - 105
add
$1,$2,$3
;$1 = $2 + $3;
sub
$1,$2,$3
;$1 = $2 - $3;
and
$1,$2,$3
;$1 = $2 & $3;
or
$1,$2,$3
;$1 = $2 | $3;
slt
$1,$2,$3
;$1 = ($2 < $3);
jr
$31
;goto $31;(return;)
lw
$1,100($2)
;$1 = mem[$2 + 100];
sw
$1,100($2)
;mem[$2 + 100] = $1;
beq
$1,$2,100
;if($1==$2) goto PC+100
10000
;goto 10000
jal
10000
;$31=PC+4;goto 10000;
;(function call;)
The MIPs Datapath

Unlike the Pico-computer the MIPs computer has several Buses
connecting its components together.
Well see later that this enables us to Pipe-line instructions.
The processor is built from several sub-sections.
The first section is the Program counter and the Instruction memory.
In this version of the MIPs processor, we keep instruction memory and
data memory separate.
159.233 Lecture 1 - 106
ADD
P
C
addr
instr
Instrmem
The Program Counter is used as the address line to the instruction

memory.
As each instruction is 32bits wide, each time we retrieve an instruction
we have to add 4 to PC to point to the next instruction. This will be
modified later to cope with jumps.
159.233 Lecture 1 - 107
R-type instructions:
These instructions only involve Registers and the ALU - remember that
the MIPS chip has a load/store architecture. Data stored in memory must
first of all be transferred to a register before performing any operation on
it.
read
data1
read
reg1
read
reg2
write read
data2
reg
instr
32
ALU
32
write
data
Registers
32
The instruction produces the numbers of each of the three registers

involved:
add
$4,$10,$14
will add register 14 to register 10 and put the result into register 4
The 32 bits making up this instruction has the form
Opcode
Rs
Rt
Rd
Shamt
Subfct
each of the register fields are 5 bits.

The register file allows 3 registers to be selected.
The two read registers, Rs and Rt are selected by the instruction and the
data stored in them appears as read data1 and read data2
The write register Rd gets its data from the output of the ALU.
The ALU is controlled by a combination of Opcode/Shamt/Subfct
159.233 Lecture 1 - 108
I-type instructions
These instructions load/store data from memory to register
lw
$1,100($2)
loads into register 1, the data stored at 100 + contents of register 2

We need to be able to add the offset stored in the instruction to a
register.
The offset is only 16 bits, so has to be extended to 32 bits for the ALU.
If the offset is negative we need to preserve the sign bit (ASR).
instr
read read
data1
reg1
read
reg2 read
write data2
reg
ALU
addr read
data
write
data
write
data
Registers
Datamem
16
32
sign
extend
159.233 Lecture 1 - 109
Branch instructions
These also have a 16bit immediate data in the instruction, which needs
to be added to the program count if the branch is taken
As the PC is always a multiple of 4, the immediate value has also to be
shifted left by 4.
PC+4
branch
address
shift
left2
instr
read
reg1
read
reg2
ADD
read
data1
ALU
branch
control
logic
write read
reg
data2
write
data
Registers
16
32
sign
extend
The ALU produces an output that will control whether the conditional
branch is taken or not.
The branch address is formed from (PC + 4) + the displacement
These separate parts can now be combined into one complete picture for
the MIPs processor architecture.
159.233 Lecture 1 - 110
m
u
x
ADD
P
C
shift
left2
addr
instr
Instrmem
read read
data1
reg1
read
reg2 read
write data2
reg
ADD
addr read
data
m
u
x
ALU
write
data
write
data
Registers
Datamem
16
m
u
x
32
sign
extend
The multiplexors have been included so that we can control which data is
to be forwarded.
The MUX sending data to the PC will be controlled by the branch control
logic
The MUX before the adder will be controlled by whether the instruction is
a load/store or not.
The MUX after the Data mem will control whether either the output from
the ALU is written back to the register bank (an R-type instruction), or
whether data from memory is written to a register (a load instruction)
Pipelining
Pipelining is an implementation technique where multiple instructions
have overlapped execution.
159.233 Lecture 1 - 111
In a car assembly plant, the work done to produce a new car is broken
down into several small jobs. As a car progresses along the assembly
line each of these jobs is performed in sequence.
The total time taken to produce a car is still the same, but several cars
can be assembled simultaneously.
A new car appears at a rate determined by how long each of the small
jobs take.
The MIPs processor can be thought of as having several steps:
lw $1,100($0)
;load the word at 100 into Reg1
is made up of five separate steps
10ns
5ns
10ns
10ns
5ns
Instr
Reg
fetch
ALU
Data
fetch
Reg
EX
MEM
WB
ID
IF
1.
IF:
Instruction fetch from Instr Memory
2.
ID:
Instruction Decode and Register fetch (Reg 0 = 0)
3.
EX:
Execution add the value (100) to register output (0)
4.
MEM:
Memory access - read location 100
5.
WB:
Write Back - write data into register 1
Total time is 40ns
159.233 Lecture 1 - 112
If we perform several loads in succession:

lw $1, 100($0)
lw $2, 200($0)
lw $3, 300($0)
The total time is 120ns
40ns
40ns
10ns 5ns 10ns
IF ID
10ns
EX
MEM
40ns
5ns
WB
10ns 5ns 10ns
IF ID
10ns
EX
MEM
5ns
WB
10ns 5ns 10ns
IF ID
EX
10ns
MEM
5ns
WB
We can reduce the total time if we overlap these steps :

Each step is independent of the others, but because some are performed
faster than others we have to insert some delays.
10ns
IF
10ns
ID
IF
10ns
10ns
EX
MEM
ID
IF
EX
ID
10ns
10ns
10ns
WB
MEM
EX
WB
MEM
WB
After we perform the ID and WB steps we must wait 5ns each step now takes the same amount of time - 10ns.
159.233 Lecture 1 - 113
Each instruction now takes 50ns.
10ns longer than before
All three instructions take 70ns.
slightly better than 120ns
But it only takes 10ns between instructions.

We have effectively increased our throughput by a factor of 4
1000 instructions now take 10,040ns instead of 40,000ns
We must be careful!
10ns
IF
10ns
ID
IF
10ns
10ns
EX
MEM
ID
IF
EX
ID
10ns
10ns
10ns
WB
MEM
EX
WB
MEM
WB
In cycle 3, the ALU is adding reg 0 to 100 for the first instruction
At the same time the immediate value 100 is changing to 200 as the
second instruction is being decoded.
Each pipeline stage needs to know the data for the instruction that it is
currently working on.
Before each of the stages, we need to include a register to remember
details of the current instruction for that stage..
We pass the contents of this register to the next stage at beginning of the
next cycle.
159.233 Lecture 1 - 114
IF/ID
m
EX/MEM u
x
ID/EX
ADD
shift
left2
P
C
Inst
mem
Regs
file
m
u
x
MEM/WB
ADD
ALU
Data
mem
m
u
x
sign
ext
Hazards
Data hazards:
Consider the following sequence of instructions:
sub
and
$2,$1,$3
$12,$2,$5
159.233 Lecture 1 - 115
sub
read
$1,$3
IM
Reg
write
$2
DM
and
read
$2,$5
IM
Reg
Reg
write
$12
DM
Reg
sub reads regs1 and 3 in cycle 2 and passes them to the ALU.
It is not until the cycle 5 that it writes the answer to the Reg File
and reads regs 2 and 5 in cycle 3 and passes them to the ALU.
Reg 2 has not yet been updated!
When and reads the Reg File it gets the wrong value for Reg 2.
This is called a data hazard.
Data hazards occur if an instruction reads a Register that a previous
instruction overwrites in a future cycle.
We must eliminate data hazards or pipelining produces incorrect results.
There are three ways to remove data hazards:
159.233 Lecture 1 - 116
The first way is to give the responsibility to software.

We must delay the and until after reg2 has been written.
sub
read
$1,$3
IM
Reg
write
$2
DM
Reg
nop
IM
Reg
DM
Reg
nop
IM
Reg
DM
nop
IM
sub
nop
nop
nop
and
Reg
and
read
$2,$5
IM
Reg
$2,$1,$3
$12,$2,$5
This puts the responsibility of removing hazards onto the compiler writer,
and involves no extra hardware.
159.233 Lecture 1 - 117
The second way is to implement hardware to detect hazards, if they

exist, and to insert a delay in the circuit - a stall.
IF/ID
sub
read
$1,$3
IM
Reg
ID/EX
EX/MEM
MEM/WBwrite
$2
DM
Reg
IF/ID
IF/ID
and
IM
stall
stall
stall
read
$2,$5
Reg
After we detect a hazard we stall the instruction memory so that no new

instructions are read until after the stall is resolved. Detecting the hazard
condition involves checking the write register in each of the pipeline
registers:
ID/EX
EX/MEM
MEM/WB
If the write register is equal to either of the two read registers in the IF/ID
register, then a stall occurs.
159.233 Lecture 1 - 118
The third way is to notice that although reg 2 does not contain valid
information at the time that the next instruction wants to read it, the
correct information is available!
It just isnt in the right place.
The EX/MEM register contains the output from the ALU.
The result that is destined for reg 2 is part of the EX/MEM register.
IF/ID
sub
read
$1,$3
IM
Reg
ID/EX
DM
IF/IDreadID/EX
and
$2,$5
IM
MEM/WB
write
$2
EX/MEM
Reg
Reg
MEM/WBwrite
$12
EX/MEM
DM
Reg
We can insert the output of the EX/MEM register into the input of the ALU
- data forwarding.
This again involves extra hardware.
It removes all of the stalls and nops of the two previous solutions.
159.233 Lecture 1 - 119
Unfortunately it does not work in all cases:

lw
and
$2,100($1)
$12,$2,$5
In this case the load instruction doesnt get the data from memory until
the DM cycle finishes
IF/ID
lw
IM
ID/EX
read
$1
Reg
DM
IF/IDreadID/EX
and
$2,$5
IM
MEM/WB
write
$2
EX/MEM
Reg
MEM/WBwrite
$12
EX/MEM
Reg
DM
Reg
The data is not available until after it is required.

We have to insert a stall.
The original MIPs chip relied on the compiler writer to insert nops trading the hardware space needed to control stalls.
These days processors must run as fast as possible. The extra hardware
for forwarding/stalling is included on the chip.
159.233 Lecture 1 - 120
Clever Compilers!
If the compiler re-orders instructions, hardware stalls for load instructions
can be eliminated:
lw
lw
add
lw
$2,(100)$10
$3,(200)$11
$4,$2,$3
$5,(300)$12
;|
;|one stall added here
Two values are copied from memory to regs 2 and 3, and are then added
together.
A further value is then copied from memory to reg 5
The second lw into reg 3, involves a stall.
If the compiler reorders the instructions:
lw
lw
lw
add
$2,(100)$10
$3,(200)$11
$5,(300)$12
$4,$2,$3
;$3 is available!
The result is the same - but now the add instruction is able to get the
value of reg 3 from the forwarding unit The load of reg 5 has inserted on extra stage into the pipeline.
159.233 Lecture 1 - 121
write
$2
read
$10
lw
Reg
IM
DM
Reg
write
$3
lw
read
$11
IM
Reg
DM
add
read
$2,$3
stall
IM
Reg
Reg
DM
read
$12
lw
Reg
IM
lw
IM
write
$2
read
$10
Reg
DM
lw
read
$11
IM
Reg
Reg
write
$3
DM
lw
read
$12
IM
Reg
Reg
DM
add
read
$2,$3
IM
Reg
no stalls!
159.233 Lecture 1 - 122
Branch Hazards
As soon as we branch to a new instruction, all the instructions that are in
the pipeline behind the branch become invalid!
..
+100
lw
beq
add
$5,(400)$14
$3,$2,100
$7,$8,$9
sub
$7,$8,$9
Either the add or sub instruction after the beq will be executed
depending on the contents of regs 2 and 3.
We can include extra hardware to calculate the branch offset in the
decode cycle. Data forwarding then makes it possible to do the branch
just one cycle later - insert a nop.
lw
IM
write
$5
read
$5,$14
Reg
DM
beq
read
$3,$2
IM
Reg
Reg
DM
Reg
nop
IM
Reg
DM
add
read
$8,$9
IM
Reg
sub
read
$8,$9
IM
Reg
Reg
DM
DM
159.233 Lecture 1 - 123
A clever compiler can eliminate the effect of the delay by inserting an

instruction after the branch!
This can be the previous instruction!
(If it is not involved in the branch.)
lw
beq
$5,(400)$14
$3,$2,100
can be re-ordered:
beq
lw
$3,$2,100
$5,(400)$14
beq
read
$3,$2
IM
Reg
lw
IM
DM
Reg
write
$5
read
$14
Reg
DM
add
read
$8,$9
IM
Reg
sub
read
$8,$9
IM
Reg
Reg
DM
DM
Power Control
The PCON register determines the idle modes of the 2051.

putting a 1 in either of the 2 low order bits will cause the 2051 to go into
idle or power-down mode.
Idle mode (01h) will allow interrupts, keep the timers going and preserve
RAM.
159.233 Lecture 1 - 124
An interrupt or reset will revert to normal operation

Power-down mode will preserve RAM but needs a reset to resume.
(resets will alter the contents of SFR).
Power-down uses considerable less power than idle mode, which again
uses less power than normal operations.
159.233 Lecture 1 - 125
Interrupts
Interrupts can be generated by the timers, the serial port or by an

external event connected via a parallel input.
The action taken by the processor is:
finish the currently active instruction.
generate an LCALL to an interrupt service routine
the ISR will perform an RETI when it finishes. This informs the CPU
that the interrupt has been handled
The LCALL branches to specific locations in memory:
0003h
000bh
0013h
001bh
0023h
Ext Int 0
Timer 0 interrupt
Ext Int 1
Timer 1 interrupt
Serial Port
Either the service routine can fit in 8 bytes (possible) or it will JMP to a
longer routine.
Interrupts can be controlled by using the IE register
EA
ES
ET1 EX1 ET0 EX0
EA is a global interrupt enable bit. Interrupts will not happen unless this is
set.
ET1/0 are the timer interrupts
ES is the serial interrupt.
The serial interrupt can happen either on RI or TI being set. The ISR will
have to read these bits to decide which requires servicing. These bits
should be cleared by software.
159.233 Lecture 1 - 126
It is good programming practice to put an reti instruction at each of the

LCALL locations even if no interrupts are expected! If one does happen
the program will jump into 'no-where'.
Interrupts can be given a priority level.
Those of higher priority can interrupt a running lower priority ISR.
The 2051 has only a two level priority scheme. Each interrupt can be
assigned 0 (low priority) or 1 (high priority).
Interrupts at the same priority level cannot interrupt each other.
Levels are set in the IP register:
-
PS
PT1 PX1 PT0 PX0
Which interrupt happens is indicated by the location involved in the

LCALL
Assembler programming
8031/51 architecture (specifically the 89C2051)

Is ideal for assembler programming!
2KBytes of program memory (read only)
128 Bytes of data
Programs must be small and efficient.
Compilers do exist for - Pascal, C and Modula 2.
159.233 Lecture 1 - 127
and most development work will be done in a high-level language, if at all

possible.
Concentrate on assembler level programming.
An assembler programmer needs to know details of the underlying
hardware, as well as be familiar with the machine instruction set.
159.233 Lecture 1 - 128
Assembler statements are English versions of machine instructions.

Each assembler statement generates 1 machine code instruction.
Whereas a C statement may well generate several machine instructions.
An assembler programmer is in complete control of the hardware.
Details that are generated automatically by C have to be done explicitly in
assembler code.
(eg passing arguments to functions)
It is important to have a good knowledge of the hardware - the 2051
includes several peripheral devices (timers, output ports etc) as well as
the CPU organisation
159.233 Lecture 1 - 129
2051 assembler programming involves:

Write the program using an editor on the development (or host)
machine.
Assemble the program.
Simulate the programs execution on a simulator or hardware emulator
Remove any mistakes
Program the chip using a FLASH programmer
Test the chip in a working environment
we will develop programs using a PC as the host environment. The
following programs are available from the network:
JFE
the gcc editor (but any text editor will do)
ASM51
a cross-compiler for 8031/8051 code
SIM51
a simulator for the 2051 controller
159.233 Lecture 1 - 130
The 2051 architecture:

Programs are stored in a separate memory area to where data is stored.
(This is different to many processors, where code and data are freely
intermixed)
2051 code must reside in the PROM (Programmable Read Only
Memory).
Constant data is also stored in the PROM.
Variable data is stored in Internal RAM.
(The 8031/8051 architecture does have facilities to allow external

program and data storage to be added to the controller chip - but these
are not available in the 2051 variant)
159.233 Lecture 1 - 131
Program code space is 2KBytes

The Program Counter is a 16bit register
(only 11 bits are used!)
8-bits
07ffh
0002h
0001h
0000h
reset
for PC
Variable data is stored in Internal RAM

8-bits
7fh
02h
01h
00h
159.233 Lecture 1 - 132
General purpose data registers are part of RAM

Machine instructions that access registers are 1 byte shorter than an
equivalent instruction that accesses RAM directly.
There are 4 banks of 8 registers
R0 - R7.
Only one bank can be active at any time.

Bank 0 is located at
00h - 07h
Bank 1 is the next 8 bytes
08h - 0fh
Bank 2 is at
10h - 17h
Bank 3 is at
18h - 1fh
Register banks are used when we have more than one activity being
performed at a time.
It is a simple matter to switch to the relevant set of registers, when we
need to swap from one task to the other.
159.233 Lecture 1 - 133
Other registers, eg the accumulator and stack pointer, are stored in an

extension to RAM
Locations 080h - 0ffh are called SFR space.
Special Function Registers
Most of this RAM is not there! Only locations for specific registers are
implemented in hardware.
SFR space varies considerably for different versions of the 8031/8051
controllers but there is a set of registers common to them all.
The 2051 implements this base set plus one other.
SFR space can be addressed either by actual locations or by standard
names
The Program Status Word is either
PSW
or
0d0h
159.233 Lecture 1 - 134
Most SFRs are concerned with specific i/o functions, we will deal with
them later
For the time being we need to know about the following:

081h
0d0h
0e0h
0f0h
SP
PSW
ACC
B
the
the
the
the
stack pointer
program status word
accumulator
B register
SP is used for subroutine calls and storing items on a stack

PSW contains flags to reflect the outcome of the previous instruction:
Carry flag, Auxiliary Carry flag, OVerflow flag
and also the current Register Bank pointer
ACC is used in most arithmetic and logic instructions - but is not normally
accessed directly through SFR space
B is used in multiplication and division
Assembler code
test.asm
$MOD2051
cseg
org 00h
mov a,#34
clr a
end
;put 34 in acc
;clear the acc
asm51 test
Notes:
159.233 Lecture 1 - 135
1. There are three types of instructions:

assembler controls
$MOD2051
tells the assembler to read predefined
register names from the file mod2051
assembler directives or pseudo-operations
cseg,
org
these do not generate machine code
real instructions
mov,
clr
2.
these do generate machine code
The assembler produces test.lst:

0000
0002
7422
e4
mov a,#34
clr a
The numbers in the 1st column are the address where the machine
code (2nd column) is stored.
and test.hex, which contains machine code in hexadecimal format. It
is read by the simulator.
3.
The first instruction generates 2 bytes of code. The second only

one.
4.
We can include comments in our code by inserting a semicolon.

All text after a ; to the end of the line is ignored.
5.
We format assembler programs so that they line up on tab stops.
6.
We can use either upper or lower case
7.
The program does not stop cleanly. Location 3 can contain anything
and will be executed after the clr instruction
159.233 Lecture 1 - 136
8.
There are 256 instructions!

The first byte is different for different instructions
There may be 1 or 2 more bytes, depending on the instruction.
9.
The second instruction could have been

mov a,#00
This takes the same time as clr (1 cycle)
but is a 2 byte instruction!
10. Assembler programs should be as concise (small) and as fast as

possible.
Sometimes these requirements conflict. We may need to trade
space for speed or vice-versa.
Assembler
Use .asm as an extension for assembler source
In a command prompt
C:> cd \159233
C:159233> asm51 filename
Errors will be reported in the file filename.lst
Simulator
C:159233>
00:
08:
10:
18:
20:
28:
30:
38:
sim51 filename
Data
00 00 00 00 00 00 00 00 ........000:
00 00 00 00 00 00 00 00 ........002:
00 00 00 00 00 00 00 00 ........003:
00 00 00 00 00 00 00 00 ........004:
00 00 00 00 00 00 00 00 ........005:
00 00 00 00 00 00 00 00 ........006:
00 00 00 00 00 00 00 00 ........007:
00 00 00 00 00 00 00 00 ........008:
Code SFR
7422
MOV
A,#22
ACC 00
E4
CLR
A
B 00
FF
MOV
R7,A
SP 07
FF
MOV
R7,A
PSW 00
FF
MOV
R7,A
IP 00
FF
MOV
R7,A
IE 00
FF
MOV
R7,A
P1 FF in
FF
MOV
R7,A
FF out
159.233 Lecture 1 - 137
40: 00 00 00 00 00 00 00 00 ........009: FF
MOV
R7,A
P3 FF in
48: 00 00 00 00 00 00 00 00 ........00A: FF
MOV
R7,A
FF out
50: 00 00 00 00 00 00 00 00 ........00B: FF
MOV
R7,A
SCON 00
58: 00 00 00 00 00 00 00 00 ........00C: FF
MOV
R7,A
SBUF 00 in
60: 00 00 00 00 00 00 00 00 ........00D: FF
MOV
R7,A
00 out
68: 00 00 00 00 00 00 00 00 ........00E: FF
MOV
R7,A
TCON 00
70: 00 00 00 00 00 00 00 00 ........00F: FF
MOV
R7,A
TMOD 00
78: 00 00 00 00 00 00 00 00 ........010: FF
MOV
R7,A
PCON 00
Flags T0 0000
LCD
RegBank 0
C N AC N OV N T1 0000
Display
Cycles
0
PC 0000 DPTR 0000
F1-RUN F2-STEP F3-STEPOVER F4-BREAK F5-RESET
Tab->next window
F10-EXIT v 1.2
159.233 Lecture 1 - 138
Constants
Numbers:
Can be in
decimal
hexadecimal
binary
34
22h
00100010b
(use a leading zero for 0aah etc)

Characters:
Can be in quotes
numeric
mixture
A
ABCD
41h
Hello,0dh,0ah
Expressions:
constants can be formed using expressions:
2+2
1 SHR 8
operators are:
Assembler directives:
+ - * / mod
shr shl
not and or xor
Segment directives:
cseg
dseg
bseg
selects the current segment.
cseg for code and constants
dseg for data.
cseg is active by default
159.233 Lecture 1 - 139
Location counter:
org
number
sets the value of the current segments location. If cseg is active, then
code will be placed at address number after the org directive
Location counter for each segment defaults to 0
End directive
end
signals the end of the source file.
Equate directive
TEN equ 10
Whenever the symbol TEN occurs in the text it will be replaced by 10
159.233 Lecture 1 - 140
Data directive
X
data
PSW
data
34h
0d0h
single byte data held in RAM or SFR can be given a name

X is the byte at location 34h in RAM
PSW is the name of the SFR register at 0d0h
Bit directive
b
bit 7
CF
bit 0d7h
single bit data held in RAM or SFR can be given a name
b is the bit at location 7 in bit addressable RAM
CF is the name of the bit at 0d7h - the carry flag
Labels
l1:
mov a,#34
Symbols must
only contain letters, numbers _ and ?

start with a letter or _?
be unique within the first 32 characters
not be a reserved word
All symbols are translated to uppercase by the assembler.

Labels are symbols with a trailing colon. They represent the location of
the instruction or assembler directive.
159.233 Lecture 1 - 141
DB directive
copyright_msg:
db
(c) Copyright, 1996
allocates space for initialised data in the cseg a byte at a time. Can only
be used when cseg is active
DS directive
buffer:
ds
16
reserves so many bytes (16) of data in RAM for variable data. The dseg
must be active.
DBIT directive
io_map:
dbit
12
reserves so many bits (12) of data in bit addressable RAM for variable
data. The bseg must be active.
The file mod2051 contains many of these directives.
Addressing Modes
There are a variety of ways to address data.
Register Direct
mov a,R3
There are 8 registers R0 - R7. Register direct will access the contents
of the specified register. The contents of R3 are placed into the
accumulator
Register Indirect
mov a,@R0
Only R0 and R1 may be used.
The register now contains an address.
The contents of that address are placed in the accumulator.
159.233 Lecture 1 - 142
The address must point to RAM ie 0 - 7fh

Immediate constants
mov a,#34
The value of the constant can be found as part of the instruction.
Direct
mov a,34
The contents of address 34 are placed in the accumulator.
The address can be either RAM or SFR
159.233 Lecture 1 - 143
Relative addressing
sjmp
start
The instruction contains a signed 8 bit offset that is relative to the first
byte of the following instruction,
Absolute addressing
ajmp
start
The instruction contains an 11 bit destination address to anywhere in the
2KByte program space
Implied addressing
Certain instructions imply a particular address - such as the accumulator.
The Program Status Word PSW
The PSW contains status bits that reflect the current state of the CPU
7
CY
6
AC
5
F0
4
RS1
3
RS0
2
OV
1
F1
0
P
The CY or carry flag is set by certain operations to indicate a carry out of

bit 7.
The AC or auxiliary carry flag is set to indicate a carry out of bit 3.
F0 and F1 are general purpose user definable flags
RS1 and RS0 define the currently selected register bank
P or parity flag is the parity of the accumulator - even parity.
Instructions
Arithmetic instructions:
159.233 Lecture 1 - 144
add
addc
subb
inc
inc
dec
dec
mul
div
da
a,<byte>
a,<byte>
a,<byte>
a
<byte>
a
<byte>
ab
ab
a
Addressing
Dir
Ind
X
X
X
X
X
X
A only
X
X
A only
X
X
A and B only
A and B only
A only
modes
Reg
X
X
X
Imm
X
X
X
X
X
mul multiplies A and B

the high order byte of the 16 bit result is in B
the low order byte in A
div divides A by B
the answer is placed in A
the remainder is in B
da is decimal adjust accumulator, and follows any add or addc
instruction working with BCD arithmetic
159.233 Lecture 1 - 145
Logical instructions:
Addressing modes
Dir
Ind
Reg
anl
a,<byte>
X
X
X
anl
<byte>,a
X
anl
<byte>,#data
X
same for orl and xrl
clr
a
A only
cpl
a
A only
rl
a
A only
rlc
a
A only
same for rr
swap
a
A only
anl
orl
xrl
clr
cpl
AND
OR
XOR
clear
NOT
rl
rlc
rotate left 1 bit

rotate left through carry
rr
rotate right
swap
low nibble (4 bits) of A with high nibble
Imm
X
159.233 Lecture 1 - 146
Data transfer:
mov
mov
mov
push
pop
xch
xchd
a,<src>
<dst>,a
<dst>,<src>
<src>
<dst>
a,<byte>
a,@Ri
Addressing
Dir
Ind
X
X
X
X
X
X
X
X
X
X
X
modes
Reg
X
X
X
Imm
X
X
mov instructions are the same as high level language assignment

statements.
push has the same effect as:
inc
sp
mov
@sp,<src>
pop has the same effect as:
mov
<dst>,@sp
dec
sp
xch exchanges the contents of A with <byte>
xchd exchanges the low nibble of A with the low nibble of the address
pointed to by R0 or R1
159.233 Lecture 1 - 147
The 2051 is capable of addressing single bits.

In RAM these bits are equivalent to the byte addresses 20h to 2fh.
These bits are numbered 0 - 7fh
Some SFR registers can be bit addressed.
These bits have symbols associated with them and are normally
accessed via the symbol. Otherwise they are numbered 80 - 0ffh
Boolean Instructions:
anl
c,bit
anl
c,/bit
same for orl
mov
c,bit
mov
bit,c
clr
c
clr
bit
setb
c
setb
bit
cpl
c
cpl
bit
jc
rel
jnc
rel
jb
bit,rel
jnb
bit,rel
jbc
bit,rel
;c = c and bit
;c = c and not bit
;c = bit
;bit = c
;c = 0
;bit = 0
;c = 1
;bit = 1
;c = not c
;bit = not bit
;jump if c == 1
;jump if c != 1
;jump if bit == 1
;jump if bit != 1
;jump if bit == 1
;then clear bit
159.233 Lecture 1 - 148
Program Branching:
jmp
addr
call
addr
ret
nop
;or sjmp/ajmp/ljmp
;or acall/lcall
;return from subroutine
; no operation
jz
jnz
rel
rel
;jump if A == 0
;jump if A != 0
djnz
<byte>,rel
;decrement, jmp if !=0
cjne
cjne
a,<byte>,rel
<byte>,#data,rel
;jump if A != <byte>
;jump if <byte> != #data
jmp or call may be used as generic instructions.

The assembler will choose which specific instruction to use. Sometimes it
does not choose the best! Forward jmp's will be converted to ljmp's.
relative addresses are -128 to 127 bytes from the PC.
PC will already be pointing to the next instruction
The $
sign is interpreted by the assembler as current location counter
sjmp
is an infinite loop.
The relative offset is not 0 though!
It is 0feh
Assembler Programs
Write an assembler program to add the two numbers stored at locations

14h and 15h in RAM and place the answer at location 16h
n3 = n1 + n2;
159.233 Lecture 1 - 149
$mod2051
n1
n2
n3
data
data
data
14h
15h
16h
org 0
mov
add
mov
a,n1
a,n2
n3,a
end
Write an assembler program to subtract the two numbers stored at
locations 14h and 15h in RAM and place the answer at location 16h
n3 = n1 - n2;
$mod2051
n1
n2
n3
data
data
data
14h
15h
16h
org 0
mov
clr
subb
mov
a,n1
c
a,n2
n3,a
end
159.233 Lecture 1 - 150
Write an assembler program to convert the character stored at location

65h to lower case
c1 |= 0x20;
$mod2051
c1
data
65h
org 0
mov
orl
mov
a,c1
a,#20h
c1,a
end
Write an assembler program to convert a string at location 45h to lower
case.
i = 0;
while (s[i]) {
s[i] |= 0x20;
i++;
}
$mod2051
dseg
org 45h
s:
ds
32
l1:
cseg
org 0
mov
mov
jz
orl
mov
inc
mov
jmp
r0,#s
a,@r0
l2
a,#20h
@r0,a
r0
a,@r0
l1
159.233 Lecture 1 - 151
l2:
nop
end
159.233 Lecture 1 - 152
Write a 2051 assembler program.

When the program starts, R0 points to a string of characters terminated
with a 00h byte.
When the program ends, R2 contains the number of consecutive double
characters within the string.
Eg
chocolate has no double letters -> R2 = 0
sweet has one -> R2 = 1
address has two -> R2 = 2
i = 0;
doubles = 0;
while (buffer[i] != 0) {
if ((buffer[i]-buffer[i+1])==0) {
doubles++;
}
i++;
}
or (using pointers):
char *r0, *r1;
char a;
int r2;
r2 = 0;
r0 = buffer;
r1 = buffer;
r1++;
a = (*r0)
while ((*r0) != 0) {
a = a (*r1);
if (a == 0) {
r2++;
}
r0++;
r1++;
159.233 Lecture 1 - 153
a = (*r0);
}
159.233 Lecture 1 - 154
$mod2051
dseg
org 40h
buffer: ds 64
;
cseg
;use R0 to point to first character
;and R1 to point to next one along
;R2 is where we store the answer
;
org 0
;
mov
R0,#buffer ;init R0 and R1
mov
R1,#buffer
inc
R1
mov
R2,#00
;set counter to 0
mov
a,@R0
;look at a char
l0:
jz
stop
;stop when its NUL
clr
c
subb
a,@R1
;sub next char
jnz
l1
inc
R2
;add to counter if zero
l1:
inc
R0
;move to the next pair
inc
R1
mov
a,@R0
;look at next char
sjmp
l0
;loop around the string
stop:
sjmp
stop
end
Subroutine/Function calls
The 2051 supports function calls:

acall
fct
transfers control to the code labelled fct
fct:
mov
@r0,20h
inc
r0
dec
a
159.233 Lecture 1 - 155
jnz
ret
fct
acall pushes the current PC on to the stack.

The SP register points to the stack - defaults to 7
The push, increments SP before transferring PC
ret pops back the previous PC from the stack
The pop, decrements SP after transferring PC
The assembler programmer has to decide, when a subroutine is called, if
registers are to be saved or not.
A subroutine may, when it is invoked, always save the registers it uses
on the stack.
Programs that call these routines can be sure that there are no side
effects - no registers are altered.
This may be inefficient!
The subroutine may alter R5 and so push and pop it to preserve its
contents.
However the calling program may not use R5 at all - in which case the
subroutine has pushed and popped needlessly.
159.233 Lecture 1 - 156
Another scheme is to have the calling program save registers before the
acall
and recover them afterwards.
push
acall
pop
5
sub
5
This suffers from the drawback that the main routine may save registers
that the subroutine doesn't use.
A final scheme is for the subroutine to document which registers it uses
and for the calling program to save only the ones that it wants.
Status flags are typically always altered by the actions of the subroutine.
Parameter passing:
1.
In Registers.
Used by most assembly programs.

Has a problem with large numbers of parameters - may run out of
registers.
Complex types - eg strings have to have their address passed.
2.
In a parameter block.
Pass a pointer to a block of memory in a register. The subroutine reads

the parameters from the block of memory.
Each routine has to have its own block of memory.
159.233 Lecture 1 - 157
3.
Immediately after the acall.
Parameters can be retrieved by finding out the return address (on the
stack) and reading the parameters from that area of memory.
Can't do this if the program is in PROM!
The return address on the stack has to be fiddled before the ret will
work. Otherwise the program will return and try and execute the first
parameter.
4.
On the stack
Most High Level Languages use this method

The calling program pushes parameters onto the stack. The subroutine
accesses them via the stack pointer.
One problem is - who pops them at the end?
In Pascal it is the responsibility of the subroutine to tidy up the stack
before returning.
In C it is the responsibility of the calling routine.
Pascal and C also have different conventions about the order of the
parameters.
In Pascal arguments are pushed from left to right.
C pushes them in the reverse order
C is designed for a variable number of arguments.
159.233 Lecture 1 - 158
SP
4a
49
return
48
address
47
ARGUMENT 1
46
ARGUMENT 2
45
ARGUMENT 3
44
ARGUMENT 4
Input / Output
The 2051 has:
2 parallel ports - port 1 and port 3
2 timers - timer 0 and timer 1
1 serial port.
(Output pins are shared between uses,
not all of the I/O capability will be available).
Timers:
The timers can be used as timers or counters.
(use either the system clock, or an external pulse).
Timer 1 can be used as the bit rate clock for the serial port.
The timers have several modes we will look at
Mode 1:
16 bit up counter - each cycle will cause the 16 bit pair TH0/TL0 to
increment. When the count gets to 0ffffh it wraps to 0000h and sets
an overflow flag.
Mode 2:
8 bit up counter with automatic reload.
159.233 Lecture 1 - 159
TL0 counts up.

When the count gets to 0ffh it sets an overflow flag and reloads TL0
with the value in TH0.
This mode is used for the serial bit rate.
159.233 Lecture 1 - 160
The TMOD register controls the mode setting for the two timers:
0
M1
M0
timer 1
M1
M0
timer 0
The TCON register controls the running of the two timers:

TF1 TR1 TF0 TR0 X
TF1 indicates an overflow has occurred

TR1 starts the counter running
The system clock runs at typically 11.0592 Mhz

1 cycle is 1/12 of the clock.
The serial clock runs at 32 times the bit rate.
At 9600 bps we auto reload after each count of 3. -> TH1 has the value
0fdh
159.233 Lecture 1 - 161
Serial I/O
Has 4 modes - look only at mode 1 (8bit UART).
SBUF is really two registers. One for input and one for output. Serial I/O
works in full-duplex, so the two registers will have different values.
Serial I/O is controlled by the SCON register
SM0 SM1 0
SM0 SM1 should be 0
TI
RI
1 for 8 bit UART
The TI bit indicates that the previous output character has been
transmitted. It should be cleared by software.
The RI bit indicates that a character has been received. It should be
cleared by software.
In the simulator (if the timer and serial i/o systems have been configured)
- the serial output is displayed at the bottom of the screen. Keys typed on
the keyboard appear as received characters in SBUF
159.233 Lecture 1 - 162
Parallel I/O
Parallel ports are for general I/O. They are all bi-directional - but if we
want to input data we must ensure that we write 1s to the pins. (they are
not full-duplex!)
The simulator is configured so that the parallel ports drive an LCD
display.
P1 holds the character to be displayed.
P3.5 acts as a strobe signal. The LCD display will read the value from
P1 when P3.5 changes from a 1 to a 0.
The real LCD is a little more complicated.
It must first be intialised.
After sending a character, either the CPU must delay for a small time
before sending another, or must wait for a signal from the LCD.
The LCD display also has a command mode (clearing the screen,
moving the cursor etc) and a data mode (ASCII characters).
159.233 Lecture 1 - 163

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Combinatorial Devices

A digital circuit can be in one of two states 0 or 1.

Logic symbols used for these combinations are:

A NAND or a NOR gate can be built from just two transistors

>AandB (sometimes written AB)

From an arbitrary truth table, we can generate a Boolean expression:

To implement the function as a circuit:

is the same as:

The following equivalences also allow us to simplify our circuits:

which are a result of De Morgans Law AB = A + B

Large memories DRAM (dynamic ram) are slow

compared to our pipeline time of ~10ns

but are ~10 times as expensive.

The same principle applies to memory.

When the processor wants to access data x5:

How does the processor know if the data is in the cache?

the 3 low order bits give the position in the cache.

Lots of memory locations are mapped to the same cache location.

To discover whether a data reference hits or misses the cache:

find the cache index of the address

To find out whether the data is in the cache:

This matching is done in parallel in a fully associative cache.

A simple pseudo LRU algorithm is:

Write Back policy:

Write Through policy:

eg for 3 inputs with the signal 101 on them:

Decoder with output enable

All outputs will be 0 unless

(Output Enable) is Low

Design a simple decoder for 4 bit numbers....

Chooses one input from many and copies it to the output.

Common configurations are:

The Output Enable line is the same as before

Consider the decoder. It is equivalent, if we replace the input with OE

However consider what happens when the signal A goes from 1 to 0

This circuit will oscillate rapidly

Consider what happens when S and R are both 0

RS Flip-flops are useful for switch debouncing.

Switches make and break several times while in close contact.

Q will be Set to 1 if switch makes contact with S

The X output of a RS Flip-flop is normally

If both R and S return to 0 simultaneously Qjumps to 1 or 0 at random

Clocked J-K Flip-flop

When J=1 =>Q becomes 1

When J=K=1=>Q becomes

The J-K flip-flop toggles the output when J=K=1.

All the flip-flops load simultaneously from the data in lines

RAM - Random Access Memory

Most memory chips are 1 bit wide, a byte is 8 chips side-by-side.

A typical memory device - 1 bit wide

CS Chip Select line acts as an Enable line to the chip

When memory is being read the Data line acts as an output

Write access to memory

W to act as a clock to strobe the data

Read access from memory

For the low order bit:

Q0 changes but Q1 hasnt caught up yet

Q1 has now changed but Q2 is still to flip over

Q2 now has reacted but Q3 is still to change

eventually we get the right answer.

Synchronous up-down counter

Using a control line

we can also create a synchronous up-down counter try it!