1.

Explain cross talk in a chip giving details of its root cause, impact on the
performance and reliability and remedies?
Ans:An unwanted coupling from a neighbouring signal wire to a network node
introduces an interference that is generally called cross talk.This resulting
disturbance act as a noise source and can lead to hard to trace intermittent errors,
since the injected noise depends upon the transient value of other signals routed in
neighbourhood. In IC this intersignal coupling can be both capacitive and
inductive .capacitve cross talk is the dominant effect at current switching speeds.
The potential impact of capacitive cross talk is influenced by the impedance of
the line under examination.If the line is floating, the disturbance is caused by the
coupling persists and may be worsened by subsequent switching on adjacent
wires. If the wire is driven, on the other hand, the signal returns to its original
level. Let us consider the circuit configuration of Figure 9.1. Line X is coupled to
wire Y by a parasitic capacitance CXY. Line Y sees a total capacitance to ground
equal to CY. Assume that the voltage at node X experiences a step
change equal to VX. This step appears on node Y attenuated by the capacitive
voltage divider.
(9.1)

Circuits that are particularly susceptive to capacitive cross talk are networks with
low swing precharged nodes, located in adjacency to full-swing wires (with
VX = VDD).Examples are dynamic memories, low-swing on-chip busses, and some
dynamic logic families.
Interwire Capacitance and Cross Talk
Consider the dynamic logic circuit of Figure 9.2. The storage capacitance CY of
the dynamic node Y is composed of the diffusion capacitances of the pre- and
discharge transistors, the gate capacitance of the connecting inverter, and the wire
capacitance. A nonrelated signal Y is routed as a Metal1 wire over the polysilicon
gate of one of the transistors in the inverter. This creates a parasitic capacitance
CXY with respect to node Y. Suppose now that node Y is precharged to 2.5 V and
that signal X undergoes a transition from 2.5 V to 0 V. The charge redistribution
causes a voltage drop DVY on node Y, as given by Eq. (9.1).

Cross Talk and Performance

The previous section discussed the impact of capacitive crosstalk on the signal integrity.
Even when cross talk does not result in fatal breakdown of the circuit, it still should be
monitored carefully as it also impacts the performance of the gate. The circuit schematic
of Figure 9.5 is illustrative of how capacitive cross talk may result in a data-dependent
variation of the propagation delay. Assume that the inputs to the three parallel wires X, Y,

and Z experience simultaneous transitions. Wire Y (called the victim wire) switches in a
direction that is opposite to the transitions of its neighboring signals X and Z. The
coupling capacitances experience a voltage swing that is double the signal swing, and
hence represent an effective capacitive load that is twice as large as Ccthe by now
well-known Miller effect. Since the coupling capacitance represents a large fraction of the
overall capacitance in the deep-submicron dense wire structures, this increase in
capacitance is substantial, and has a major impact on the propagation delay of the circuit.

Observe that this is a worst-case scenario. If all inputs experience a simultaneous

transition in the same direction, the voltage over the coupling capacitances remains
constant, resulting in a zero contribution to the effective load capacitance. The total load
capacitance CL of gate Y hence depends upon the data activities on the neighboring
signal,s and varies between the following bounds:
CGND CLCGND + 4Cc

(9.2)

with CGND the capacitance of node Y to ground, including the diffusion and fanout
capacitances. In [Sylvester98], it was established that for a 0.25 mm technology the wire
delay with noise is potentially 80% larger than the wire delay without noise (scenario of
Figure 9.5; wire length = 100 mm, fanout = 2).Complicating the analysis of this problem
is the fact that the capacitance not only depends upon the values of the surrounding wires,
but also upon the exact timing of the transitions. The simultaneity of transitions can only
be detected from detailed timing simulations, making the timing verification process
substantially more complex. The ensuing explosion in verification cost caused by the
unpredictably of the actual delay is hence a source of major concern. Just assuming
worst-case conditions for the capacitancesthis is, always assuming the Miller effect
leads to an overly pessimistic estimation, and overkill in the circuit design.
Design TechniquesReducing Capacitive Cross Talk
Cross talk is a proportional noise source. This means that scaling the signal levels to
increase noise margins does not help since the noise sources scale in a similar way. The
only options in addressing the problem is to control the circuit geometry, or to adopt
signaling conventions that are less sensitive to coupled energy. A number of ground rules
can be established .
1. It is obviously not a good idea to allow the capacitance between two signal wires to
grow too large if one wants to keep cross talk at a minimum. It is, for instance, bad
practice to have two wires on the same layer run parallel for a long distance. One is often
tempted to do just that when distributing the two clocks in a two-phase system or when
routing a bus. Wires on adjacent layers should be run perpindicular.
2. Avoid floating nodes if at all possible. Nodes sensitive to cross talk problems, such
as precharged busses, should be equiped with keeper devices to reduce the impedance.
3. Sensitive nodes should be well-separated from full-swing signals.
4. Make the rise (fall) time as large as possible, subject to timing constraints.
5. Use differential signaling in sensitive low-swing wiring networks. This turns the
cross talk signal into a common-mode noise source that does not impact the operation
of the circuit.
6. If necessary, provide a shielding wireGND or VDDbetween the two signals
(Figure9.4). This effectively turns the interwire capacitance into a capacitance-toground
and eliminates interference.
7. The interwire capacitance between signals on different layers can be further reduced

by the addition of extra routing layers. When four or more routing layers are available,
we can fall back to an approach often used in printed circuit board design. Every signal
layer is interleaved with a GND or VDD metal plane (Figure 9.4).
Des

2C

2. Discuss the impact of interconnect resistive parasitics on the reliability, power

distribution and performance of an IC?
Ans:Current flowing through a resistive wire results in an ohmic voltage drop that
degrades the signal levels. This is especially important in the power distribution
network, where current levels can easily reach amperes, as illustrated in Figure 9.12
for the Compaq Alpha processor family. Consider now a 2 cm long VDD or GND
wire with a current of 1mA per m
Cross Ta

width. This current is about the maximum that can be sustained by an aluminum wire due

to electromigration, which is discussed in the subsequent section. Assuming a sheet

resistance of 0.05 W/q, the resistance of this wire (per mm width) equals 1 kW. A current
of 1 mA/mm would result in a voltage drop of 1 V. The altered value of the voltage
supply reduces noise margins and changes the logic levels as a function of the distance
from the supply terminals. This is demonstrated by the circuit in Figure 9.13, where an
inverter placed far from the power and ground pins connects to a device closer to the
supply. The difference in logic levels caused by the IR voltage drop over the supply rails
might partially turn on transistor M1. This can result in an accidental discharging of the
precharged, dynamic node X, or cause static power consumption if the connecting gate is
static. In short, the current pulses from the on-chip logic, memories and I/O pins cause
voltage drops over the power-distribution network, and are the major source for on-chip
powersupply noise. Beyond causing a reliability risk, IR drops on the supply network
also impact the performance of the system. A small drop in the supply voltage may cause
a significant increase in delay.The most obvious solution to this problem is to reduce the
maximum distance between the supply pins and the circuit supply connections. This is
most easily accomplished through a structured layout of the power distribution network.
A number of onchip power-distribution networks with peripheral bonding are shown in
Figure 9.14. In all cases, power and ground are brought onto the chip via bonding pads
located on the four sides of the chip. Which approach to use depends upon the number of
coarse metal layers (this is, thick, high pitch topmost metal layers) one wants to allocate
to power distribution. In the first approach (a), power and ground are routed vertically (or
horizontally) on the same layer. Power is brought in from two sides of the chip. Local
power strips are strapped to this upper grid, and then further routed on the lower metal
levels. Method (b) uses two coarse metal layers for the power distribution, and the power
is brought in from the four sides of the die. This approach was used in the EV5
generation of the Compaq Alpha processor [Herrick00]. The combination of power and
clock distribution occupied more than 90% of the 3rd and 4th Al layers. One further and
more aggressive step to take is to use two solid metal planes for the distribrution of Vdd
and GND (c). This approach has the advantage of drastically reducing the resistance of
the network. The metal planes also act as shields between data signalling layers, hence
reducing cross-talk. They also help to reduce the on-chip inductance. Obviously, this
approach is only feasible when sufficient metal layers are available.
The sizing of the power network is a non-trivial task. The power grid can be modeled
as a network of resistors (wires) and current sources (logic), containing hundreds of
millions of elements. Very often, many paths exist between the power pins and the supply
connections of a chip module or gate. While in general the current follows the path of the
lowest resistance, the exact flow depends upon factors such as the current draw from
neighboring modules that share the same network. The analysis is complicated by the fact
that peak currents drawn by the connected modules are distributed over time. IR drop is a
dynamic phenomenon due primarily to simultaneous switching events such as clocks, and
bus drivers. As large drivers begin to switch, the simultaneous demand from current from
the power network stresses the grid. At the same time, a worst-case analysis adding all
the peak currents may lead to a gross over dimensioning of the wires.

The above makes it clear that computer-aided design tools are a necessary companion
of the power-distribution network designer. Given the complexity of todays integrated
circuits, transistor-level analysis of the complete power-network requirements is just not
feasible. At the same time, partitioning of the problem over sub-sections might not result
in an accurate picture either. Changes to the power grid in one section tend to have a
global impact. This is illustrated in Figure 9.15, which shows the simulated IR voltage
drop of a complex digital circuit. A first implementation (a) suffers from a more than
acceptable drop in the upper right module of the design, because only the top portion of
the power grid feeds the large drivers at the top. The lower portions of the module are not
directly connected to the grid. Adding just one single strap to the network largely resolves
this problem, as shown in (b).
Therefore, an accurate picture of the IR risk cannot be obtained unless the entire chip is
verified as a single entity. Any tool used for this purpose must have the capacity to
analyze multi-million resistor grids. Fortunately, a number of efficient and quite accurate
power-grid analysis tools are currently available [Simplex, ]. They combine a dynamic
analysis of the current requirements of the circuit modules with a detailed modeling of
thepower network. Tools as such are quite indispensable in todays design process.