ie | ee ina) The Art of Analog Layout Second Edition [#] AlanHastings 3 EFL Lt MaACPO Un and esl Nira, Oe ee eee The Art of Analog Layout, Second Edition Ge a eel eke IRS CL be SBS teem Ge lane Ct aed pa Eee eRe ee See se Sle Liar mea oe ade peepee aa 1h ech Linea [ke Sabet ce ot ces | Mies ead ues Soest SMe Sees ae tae ee Ate ace Ie ceo EN RES Be 2 toe Ses clea I Lal Scat CIP SR Ee cm tt Wie ee ce al bP ERE ey 0 Ad LCN Reel ee BARD RE Ses ches CO Zab Rigi SLE ie MES ea ie te a oT CE Cae Lee ING Li imc ue seh. Catena BAe SRG Mee Sd be ead pA SARS Ssi2sc e tlee st dees cee ie pe A Re SRG a Ed cae b a cee weed) a] eis Reagent | sae ie bo UM i os ] I It Poem ose PE Ad Ce a oe ea ee ee ce oT) PaaS oe RoBUMEF Sik Sate RS ID FBSA S AR (8x8) (RH) The Art of Analog Layout Second Edition [XJ Alan Hastings 3 EFLE t wad Publishing House of Electronics Industry Aba + BEINGAse EF Alan Hestings 54s TA HOHE PERRET OAL SER, ABELL ALBA AS EET RARE PARES ED PPh ALE sO HO TFE MN... BP Tee TE PR EP SL | ARV SAE, APRN PAO RAY IIMEATS.: SREY. CMOS HEMET 2-41 BICMOS: TE. BAHT ABATE, ERT. REAM aT SM PARSE STORIE, SLR IE. TPS BUTE. AUER SDE, RUGSHAT HHT FREES A SARI, ARGO PE AKI OEE A ESE Bt , TTP AB th dt A HAMS S45. English reprint Copyright © 2006 by PEARSON EDUCATION ASIA LIMITED and Publishing House of Electronics ncntey. “The An of Analog Layout. Second Edition, ISBN: 0131462108 by Alan Fiastings. Copyright © 2006. Published hy arrangemcen with the original publisher, Pearson Education, Ine. publishing si Peeotice Hall, “This edition is authorized for sale-only in the People's Republic of Chins (excluding. the Special Adesinistentive Region of Hong, Kong, Macas and Taiwan). AAA FT ALE HE FT AY ASL At Pears Education $4 S95 88 GSE Ay PLS Ae IL, FA BA, ABIEF AS, HABEAS A ARB EAT R SY, AC TSTIMA Pearson Education S17E A ARR FAROLDI ERE, RESTA BE FEHR ARBCS BEF. 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EEE Su ASS KA BR MES, A SP SARAPARRSOASH ESS ASE diorabe Are. CPE BOR CROCK) eT JRABEE DESERET Pes COT HK, SAT BP MARAE BT LARA FRACS. ESE, SRS GH RELATED. BRE THE TBARS F DEAS EEA BAAR TAB AES BPS fee OR SEES PERSO ACRER. MAG. (SUE SER ER BESPreface to the Second Edition 1 originally wrote The Art of Analog Layout as a companion volume to a series ol lectures. Many people encouraged me to publish i. At first I was reluctant to do 50, for] thought that it would find a rather limited audience. Publication has proven my concems quite unfounded. To my astonishment, The Art of Analog Layott has even been translated into Chinese? “he passage of several years has alerted me to the limitations of the first edi- tion nnd prompled an extensive revision. Every chapter has been examined and corrected. Many new passages have been added, along with some SO new illusira- ‘Hons to accompany them. New topics introduced in tbe: second edition include the foltowing: Advanced metallization systems Dielectric isolation Failure mechanisms of MOS transistors Integrated inductors MOS safe operating area Nonvotatile memory In preparing this edition, have drawn extensively upon the experience and wis- dom of my colleagues at Texas Instruments.1 have also made constant reference 1o the resources available upon the IEEE Xplore website, most particularly those con tained in the LEEE Journal of Electron Devices. 1 thank all the many people who ‘have contributed to my own understanding or who have corrected may many mis- sakes. A work of this length and magnitude will never prove perfect. but the second edition greatly improves upon the first. ALAN HASTINGSPreface to the First Edition ‘An integrated circuit reveals its true appearance only under high magnification. The intricate tangle of microscopic wires covering its surface and the equally intricate patterns of doped silicon beneath st, ll follow a set of blueprints called a layout. The process of constructing Layouts for analog and mixct-signal amtegrated circuits has stnbhoraly defied ail attempts at automation. The shape and placement of every polygon requires thorough understanding of tbe principles of device physics,semi- conductor fabrication, and circuit theory. Despite 30 years of research, much re- mains uncertain. What information there is lies buried in obscure journal articles and unpublished manuscripts. This texthook assembles that information between a single set of covers. While primarily intended for use by practicing layout desigaers, it should also prove valuable to circuit designers whe desice a better understanding ‘of the relationship between circuits andl Iayouts, ‘The text bas been written for a broad wudience. some of whom have had valy Tim- ited exposure 10 higher mathematics and solid-state physies. The amount of mathe matics has been Kept fo an absolute minimum. and eare bas been taken to identify atl variables and to use the most accessible units. The reader need only have a fami ierity wih basic algebra and elementary electrons. Many of the exercises assume that the reader also has aocess to layout editing software; but those who lack such resources can complete matty of the exercises with pencil and paper, ‘The text consists of 14 chapters and five appendices, The first two chapters pro- wicke an overview of device physics and serniconductor processing. These chapters avoid mathematical derivations and instead emphasize simple verbal explanations and vieual models The third chapter presents three archetypal processes: standard bipolar. silicon-gate CMOS, and analog BKCMOS. The presentation focuses upon development of cross sections and the correlation of these cross sections to con- ventional layout views of Sample devices. The fourth chapter covers common Fait ure mechanisms and enaphasizes the role of layout in determining reliability. Chapters 5 and 6 cover the layour of resistors and caparitors. Chapter 7 preseals the principles of matching, using resistors and capacitors as examples. Chapters 8 theough 10 cover the layout af bipolar devices, while Chapters 11 and 12 cover the layout and matching of field-effect transistors. Chapters 13 aad 14 cover a variety ‘of advanced topics, inctuding device mergers, guard rings, ESD protection struc. tures. and floorplanning, The appendices include a list of acronyms,a discussion of, Miller indices, sample layout rules for use in working the exercises, and the deriva- lion of formulas used in the text, ALAN HASTInGsAcknowledgments ‘The information contained in this text has. been gathered through the hard work of many scientists, engineers, and technicians, the vast majority of whom must remain unacknowledged because their work bas not been published. [ have mcluded refer- ences to as many fundamental discoveries and principles as T could, but in many cases I have been unable to determine origanal sources. I thank my colleagues at Texns Instrusments for numerous suggestions. I am espe- clally grateful to Ken Bell, Walter Bucksch, Taylor Efland, Lou Hutter, Clif Jones, Alec Morton, Jet Smith, Fred Trafton, and Joe Trogolo. all of whom have provided Jenportant information for ths text. am also grateful for the encouragement of Bob- Borden, Nicolas Salaming, and Ming Chiang, without which this book woul! never have been written,Contents 1 Device Physics 1 11 Semiconductors 1 1.1. Generation and Recombination 4 1.1.2. Extrinsic Semiconductors 6 1.1.3. Diffusion and Dit 9 12 PN Junctions L241, Depletion Regions 11 1.2.2, PNDiodes 13 Schottky Diodes 16 Zener Diodes 18 Obmic Contacts 19 13° Bipolar Junction Transistors. 21. 13. Beta 23 1.32. 1-V Characteristics 24 14 MOSTransistors 25 14.1. Threshold Voltage 27 142, EV Characterisies 29 15 JFET Transistors 32 16 Summary 4 17 Exercises 35 2 Semiconductor Fabrication 37 21 Silicon Manufacture 37 21. Crystal Growth 38 212. Wafer Manufacturing 39 213. “The Crystal Structure of Siliom 39 22. Photolithography 41 22.1. Photoresists 41 222. Photomasks and Retices 42 223. Rarerning 43 23 Oxide Growth and Removal 43 231. Oxide Growth and Deposition 44 232. Oxide Removal 45 233. Other Effects of Oxide Growth and Removal 47 234, Local Oxidation of Silicon (LOCOS} 49 24 Diffusion and fon Implantetion 50 2A., Diffusion 3! 242. Other Effects of Diffusion 53 243. Ton Implantation 5525 27 28 29 Silicon Deposition and Etching 57 25.1. Epitaxy 57 252. Polysiicon Deposition $9 253. Dielectric Isolation 60 Metallization 62 26.1. Deposition and Removal of Aluminum 63 262. Refractory Barrier Metal 65 263. Silicidation 67 2.64. Interlevel Oxide, interlevel Nitride, and Protective Overcoat 69 2.65. Copper Metallization 71 Assembly 73 27.1. Mount and Bond 74 272 Packaging 77 Summary 78 Exercises 78 Representative Processes 80 al 32 -12- Standard Bipolar 81 Bu. Bseential Features 81 312. Fabrication Sequence 82 Starting Materiat 82 N-Buried Layer 82 Epitaxial Growth 83 Bolaion Diffusion 83 Deep-N+ 83 Base tnplant 84 Emitter Diffusion 4 Comact 85 Metallization 85 Protective Overcoat 86 3.13. Available Devices 86 NPN Tranststors 86 PNP Transistors 88 Resiscors 90 Capacitors 92 3.14. Process Extensions 93 Up-Down ksolation 93 Double-Level Metal 94 Schoitky Diodes 96 High-Sheet Resistors 94 Super-Beta Transistors 96 Polysiticon-Gate CMOS 96 3.21. Essential Features 97 322. Fabrication Sequence 98 Starting Material 98 Epitatiat Growth 98 N-Well Diffusion 98 Inverse Moat 99 Channel Stop Iraplants 100 LOCOS Processing and Dummy Gate Oxidation 100 Theeshotd Adjust 101323. 324, Polysiticon Deposition and Patierning 102 Source/Drain Implants 102 Contacts Wi Metatiizetion 103 Protective Overcoat 103 Available Devices 104 NMOS Transistors 104 ‘PMOS Transistors (06 Substrate PNP Transistors 107 Resistors (07 Capacitors 109 Process Extensions 140 Double-Lavel Metal HO Shallow Trench Irolaion #10 ‘Siicidation Ut Lightly Doped Drain (DB) Transistors 112. Extended-Drain, High-Voltage Transistors 113 33 Analog BiCMOS 114 33, 332. 333, ‘Fssential Features US Fabrication Sequence 116 Starting Material 116 N-Buried Layer 116 Epitaxiat Growth 117 N-Welt Diffusion anit Deep-N* 117 Bose implant U8 Inverse Meat 118 Channel Stop limplants U9 LOCOS Processing and Dummy Gate Oxidation 119 Threshold Adjust 119 Polystlican Deposivon and Pattem 120 Source/Drain implants DO ‘Meralization and Protective Overcom 120 Process Comparison 127 Available Devices 121 NPN Transistors 121 PNP Transistors 123 Resistors 125 Process Extensions 125 “Advanced Meral Syswems 126 Dielectric Isolation 126 34 Summary 130 39. Exercises 131 4 Failure Mechanisms 133 4,1 Electrical Overstress 133 418 412 Electrostatic Discharge (ESD) 134 Effects 135 Preventative Measures 135 Electromigration 136 Effects 136 Preventative Measures 137 “1B:43 44 45 46 41.3. Dielectric Breakdown 138 Effects 138 Prevenuative Measures 139 41.4, ‘The Antenna Effect 141 Effeces UI Preventative Measures 142 Contamination 143 421. DryCorroson 144 Effects 144 Preventative Measures 14S 422. Mobile ton Contamination 245 Effects 145 Preventative Measures 146 Surface Effects 148 43.1. Hot Carrier Injection 248 ffects 148 Preventative Measures 150 43.2. Zener Walkout 151 4 Fffects 151 Preventative Measures 152 43.3. Avalanche-Induced Beta Degradation 133 Effects 453 Preventative Measures 158 434, Negative Bias Temperature Instability 154 Pffects #55 Prevenuative Measures 155 435. Parasitic Channels and Charge Spreading 156 Effects 156 Preventative Ateasures (Standard Bipolar) 159 Preventative Measures (CMOS and BiCMOS) 162 Parasitics 164 44.8. Substrate Debiasing 165 Effects 166 Prevenuutive Measures 167 442. Minotity-Carrier Injection 160 Fffeces 169 Preventative Measures (Substrate Injection) 172 Preventative Measures (Cross-Injection) 178 443. Substrate Influence 180 Effects 180 Preventative Measures 180 Summary 183 Exercises 183 Resistors 185 51 52 53 14. Resistivity and Sheet Resistance 185 Resistor Layout 187 Resistor Variability 192 53.2, Process Variation 191 5.3.2. Temperature Variation 192533. Nonlinearity 193 534, Contact Resistance 196 5.4 Resistor Parasitics 197 5.5 Comparison of Available Resistors 200 S51. Base Resistors 200 552. Bimitter Resistors 201 553. Base Pmch Resistors 202 SSA. High-Sheet Resistors 202 555. Epi Pinch Resistors 205 556. Metal Resistors 206 557. Poly Resistors 208 558. NSD and PSD Resistors 211 559. N-WellResistors 211 55.10. Thin-Film Resistors 212 5.6 Adjusting Resistor Values 213 56.1. Tweaking Resistors 213 Sliding Contacts 214 Sliding Heads 218 Frombone Slides 215 ‘Meta? Options 215 56.2. ‘Trimming Resistors 226 Fuses 216 Zener Zaps 219 EPROM Trims 221 Laser Trims 222 5.7 Summary 223 5.8 Exercises 224 Cape tears ad laducars 226 1 Capacitance 226 6.11. Capacitor Variability 232 Process Variation 232 Voltage Modulation and Temperature Variation 233 612. Capacitor Parasitics 235 6.13. Comparison of Available Capacitors 237 Base-Emiter Junction Capacitors 237 MOS Capactiors 239 Poly-Poly Capacitors 241 Stack Capacitors 243 = ‘Lateral Flux Capactiors 245 High-Permeitivity Copacitors 246 62 Inductance 246 621, Inductor Parasitics 248, 622. Inductor Construction 250 Guidelines for Integrating Inductors 251 63 Summary 252 64 Exercises 253 Matching of Resistors and Capacitors 254 7.1 Measuring Mismatch 254 115+72 Causes of Mismatch 257 721 Random Variation 257 Capacitors 258 Resistors 258 Process Biases 260 Interconnection Parasitics 261 Pattern Shift 263 Etch Rete Variations 265 Photolithographic Effects 267 Diffusion Interactions 268 Hydrogenation 270 . Mechanical Stress and Package Shift. 271 |. Stress Gradients 274 Piezoresisivity 278 Gradients anal Cersroids 275 Common-Certroid Layout 277 Location and Orientation 281 72411, Ternperature Grodients and Thermoelecirics 283 Thermal Gradieras 285 Thermoelectric Effects 287 ‘7.2.12, Elccirostatic Interactions 288 Voltage Modulation 288 Charge Spreading 292 Diefectric Polarization 293 Dietectric Retaxation 294 73 Rules for Device Matching 295 7.3.1, Rules for Resistor Matching 296 73.2. Rules for Capacitor Matching 300 74 Summary 303 75 Exercises 304 Bipolar Transistors 306 8:1 Toplesin Bipolar Ransior Operation 306 Beta Rolloff 308 Avalanche Breakdown 308 “Thermal Runaway and Secondary Breakdown 310 Seturation in NPN Transistors 312 Saturation in Lateral PNP Transistors 315 Porasitics of Bipolar Transistors 318 82. Standard Bipolar Small Signal Transistors 320 82.1. The Standard Bipolar NPN Transistor 320 Construction of Smoall-Signal NPN Transistors 322 822. “Me Swondard Bipolar Substrate PNP ‘Transistor 326 Construction of Small-Signa! Substrate PNP Transistors 328 8.23. ‘The Standatd Bipolor Lateral PNP Transistor 330 Construction of Smalt-Signal Lateral PNP Transistors 332 8.24, High-Voltage Bipolar Transistors 337 825. Super-Beta NPN Transistors 340. 83 CMOS and BiCMOS Small-Signal Bipolar Transistors 342 831. CMOS PNP Transistors 341 ‘83.2. Shallow-Well Transistors 345 sie:10 83.3. Analog BICMOS Bipolar Transistors 347 834. Fast Bipolar Transistors 349 835. Polysilicon-Emitter Transistors 351 83.6 Oxide-leolsted Transistors 354 837. Sikeon-Germanium Transistors 356 84 Summary 358 BS Exercises 358 Applications of Bipolar Transistors 360 9.1 Power Bipolar Transistors 361 9.1.1. Failure Mechanisons of NPN Power Transistors 362 Emer Debiasing 362 ‘Thermal Runaway and Secondary Breskdown 364 Kirk Effect 306 9.12. Layout of Power NPN Transistors 368 The Interdigirated-Fritier Transistor 369 The Wide-Ematter Narrom-Contact Transistor 371 ‘The Christmas-Tree Device 372 The Cruciform-Fmnitter Transistor 373 Power Transistor Layout in Analog BiCMOS 374 Selecting a Power Transisior Layout 376 9.1.3. Power PNP Transistors 376 9.14. Saturation Detection and Limiting 378 9.2 Maiching Bipolar Transistors 381 92.1. Random Variations 382 922. Emitter Degeneration 384 923. NBL Shadow 386 924. ‘Thermal Gradients 387 925. Stress Gradients 391 926. Filler-Induced Stress 393 92.7. Other Causes of Systomatic Mismatch 395 9.3. Rules for Bipolar Transistor Matching 396 93.1. Rulles for Matching Verrical Transistors 397 9.32. Roles for Matching Latcral Transistors 402 94 Summary 402 9.5 Exercises 403 Diodes 406 10.1 Diodes in Standard Bipolar 406 20.1, Diode-Connected Transistors 406 1012. Zener Diodes 409 Surface Zener Diodes 410 Buried Zeners 412 10.1.3. Schottky Diodes 425 10.1.4. Power Diodes 420 10.2 Diodes in CMOS and BiCMOS Processes 422 102.1, CMOS Junetion Diodes 422 1022. CMOS and BiCMOS Schottky Diodes 423 10.3 Matching Diodes 425 103.1. Matching PN Junction Diodes 425 a7Nn 2 103.2, Matching Zener Diodes 426 103.3. Matching Schottky Diodes 428 104 Summary 428 10.5 Exercises 429 Field-Effect Transistors 430 11.1 Topics in MOS Transistor Operation 431 ULL. Modeling the MOS Transistor” 431 Device Tronsconductance 432 Threshold Voltage 434 TL12. Parasitics of MOS Transistors 438 Breakdown Mechanisms 460 CMOS Latchup 442 Leakage Mechanisms 443 11.2 Constructing CMOS Transistors 446 112.1 Coding the MOS Transistor 447 Widih and Length 488 11.2.2. N-Well and P-Well Processes 449 112.3. Channel Stop Implants 452 1124, Threshold Adjust Implants 453 1125. Scaling the Transistor 456 11.26, Variant Structures 459 Serpentine Transistors 461 Arinudar Transistors 462 11.27. Backgate Contacts 464 11.3 Floating-Gate Transistors 467 113.1. Principles of Floating-Gate Transistor Operation 469 1132. Single-Poly EEPROM Memory 472 114 The JFET Transistor 474 ULA1. Modeling the JFET 474 142. JFET Layout 476 11.5 Summary 479 11.6 Exercises 479 Applications of MOS Transistors 482 - 12.1 Extended-Vottage Transistors 482 1g 12.1, LDD and DDD Transistors 483 12.1.2. Extended-Drain Transistors 485 Extended-Drain NMOS Transistors 487 Extended-Prain PMOS Transistors 438 12.13. Muttiple Gate Oxides 489 12.2 Power MOS Transistors 491 1221. MOS Safe Operating Arca 492 Electrical SOA 493 Electrothermal SOA 496 Rapid Transient Overtoad 497 1222. Conventional MOS Power Transistors 498 The Rectangular Device 499 The Diagonal Device 500 Compraation of Ry SOL13 Ocher Considerations $02 Nonconwentional Structures 503 1223. DMOS Transistors 505 The Lateral DMOS Transistor 506 RESURF Teansisiors 508 The DMOS NPN 510 e 12.3 MOS Transistor Matching 511 123.1. Geometne Effects 313 Gate Area SIX Gaase Oxide Thickness 544 Channel Length Modulation 515 Orientation 515 1232. Diffusion and Etch Effects $16 Polysilicon Eich Rate Variaaons $16 Diffusion Penetration of Polysilicon 547 Contacts Over Active Gate SHB Diffusions Near the Charmet S18 PMOS versus NMOS Transistors 519 1233. Hydrogenation 520 PM Metal arad MOS Marching 524 1234 Thermaland Stress Effects 521 Oxide Thickness Gradients 522 Stress Gradients 522 Thermal Gradients 522 135. Common-Centroid Layout of MOS Transistors $23 12.4 Rules for MOS Transistor Maiching 528 12.5 Summary 531 126 Exercises 531 Special Topics 534 13.1 Merged Devices 534 IB.L1. Flawed Device Mergers 535 13.12. Successful Device Mergers 539 13.13. Low-Risk Merged Devices S41 13.14, Medium-Risk Merged Devices 542 13.15. Devising New Merged Devices S44 13.16. ‘The Role of Merged Deviess in Anslog BICMOS 544 13:2 Guard Rings 545 13.21, Standard Bipolar Electton Guard Rings 546 15.22. ‘Standard Bipolar Hole Guard Rings 547 13.2.3, Guard Rings in CMOS and BiMOS Designs Sa 13.3 Single-level Interconnection 551 13.3.1, Mock Layouts and Stick Diagrams S31 13.32. Techniques for Crossing Leads 553 1333. Types of Tunnels $85 13.4 Constructing the Padring 557 13.4.1. Scrthe Streets and Alignmem Markers 557 13.42. Bondpads Trimpads and Testpads 558 135 ESD Structures 562 13.51. Zener Clamp 563 1352. Two-Slage Zener Clamps 565 -4 13.53. Buffered Zener Clamp 566 1354. VorsClamp 368 1355. VecyClamp 569 13.56. Antiparallel Diode Clamps $70 1. Grounded-Gate NMOS Clamps 570 . CDM Clamps 572 Lateral SCR Clamps 573 Selecting ESD Structures 575 136 Exercises 578 Assembling the Die 581 14.1 Die Planning 581 14.11. Cell Area Estimation 582 Resistors 582 Capacitors 52 Vertical Bipolar Transistors 583 Loterat PNP Transistors 583 MOS Transistors 583 MOS Power Transistors 584 Computing Cell Area 584 14.12, Die Aren Estimation 584 14.1.3. Gross Profit Margin 587 142 Floorptanning 588 143 Top-Level interconnection 594 14.3.1. Peinciples of Channel Routing 594 1432. Special Routing Techaigues 596 Kelvin Connections 597 ‘Nolsy Signals and Sensitive Signals 508 1433, Electromigration 600 1434, Minimizing Stress Eifects 603 144 Conclusion 604 145 Exercises 605 Appendices A. Table of Acsonyms Used in the Text 607 B, The Miller Indices of a Cubic Crystal 611 G Sample Layout Rules 614 D. Mathematical Derivations 622 E, Sources for Layout Editor Software 627 Index 629Device Physics Before 1960, most ctectronie circuits depended upon vacuum tubes to perform the 1a3ks of amplification and rectification. An ordinary mass-produced AM radio required five tubes, while a color television needed no fewer than twenty, ‘Vacuum fubes were large, fragile, and expensive. They dissipated a lot of heat and were not very reliable, So long as electronics depended upon them, it was nearly im- possible to construct systems requiring thousands or millions of active devices. ‘The appearance of the bipolar junction transistos in 1947 marked the beginning of the solid-state revolution. These new devices were small, cheap, rugged, and reli- able, Solid-state circultry mede possible the development of packet transistor radios, and hearing aids, quartz watches and touch-tone phones, compact disc players and personal computers. A solid state device consists of a crystat with regions of imporities incorporated into its surface. These impurities modify the electricel properties of the crystal, al- lowing it Lo armplify or modulate clectrical signals. A working knowledge of device [physics is necessary to understand how this occurs. This chapter covers not only ele- mentary device physics but also the operation of three of the most important solid- state devices: the junction diode, the bipolar transistor, and the field-effect transistor. Chapter 2 explains the manufacturing processes used to-construct these ‘andl other solid state devices, ERB semiconvucrors “The inside front cover of the book depicts a long-form periodic table. The elements: are arranged so those with similar properties group together to form rows and columns. The elements on the left-hand side of the periodic table are called merads, while thase 00 the right-hand side are called nonmerals, Metals are usually good conductors of heat and electricity. They are also malleable and display a character- istic metallic luster. Noametals are poor conductors of heat and electricity, and those that are solid are brittle and lack the shiny luster of metals. A few elements in the middle of the periodic table, such as silicon and germanium, have electricalHEB the artot Analog Layout, second tition —_ FIOURE 1.1 Sicnplifedittstes- tions of various types of eben al bonding, a soa partof« metalially bonded sodsem verystal (A), » small part af an teescally bonded sodium chlo- Fide crystal {B), and 2 covaleat 1) donded chlorine ‘molecule (€), Properties that hie midway between those of metals and nonmetals These clemeats are called semiconductors. The differences between metals. serntconductors, and nonmetals result from differences in the electronic structure of their respective lems, Every atom consis of a positively charged nuclous surrounded by 3 cloud of electrons ‘The number of electrons in this loud equals the number of protons in the agleus, which also equals the atomic number of the element. Therefore, a carbon ‘tom has six electrons because carbon hasan atomic number of six. These electrons ‘occupy a series of shells that are somewhat analogous to the layers of an onion. As electrons ate added, the shells fill in order from innermost outward, The outermost oo valence shell muy remain unfilled, The elecirans occupying this outermost shell are called valence electrons, The number of valence electrons possessed by an cle- ‘ment determines most of its chemical and electronic properties Ench row of the periodic table corresponds to the filling of one stell. The tefunost Bandgap everges for S.Ge-B G Stren, Sots Sate Elem Devore 2 ed (Englenacd CMs NF Prentice-Hall, 1990) p. 445. Baap for C= WL Hany. ed. Semicondacsors (New York, Reinbold Publish. ng. 1959). .52.Condoctony for Sa B.C Weast.od CRC Hendoook of Chemusry and Physi. 62 ef (Boce Baton, FL: CRC Pres, 1981). pp FIS-F136 Orher values compuied Meling pois Wea, pp BS BM__ Chaplet 1 Device Physics _ tection vcaney FIGURE 1.3 Simplified diegram ‘el Fee electron of thetmall generation in intrinsic sil adjacent atom, As the vacancy % handed from atom te atom. it moves through the Iatlice. This moving electron vacancy is called a hole. Suppose an elecinc field is placed across the crystal. The negatively charged free electrons move toward the positive end of the crystal The holes hehave asif they wete posttively charged patticles.and move towerd the negative end of the crystal. Hotes in ‘sayslal lattice are like bubbles in Liquid. Just as a bubble is @ location devoid of fluid, hole isa location devord of valence electrons Bubbles mave upward because tie fluid around them sinks downward. Holes shift toward the negative end of the crystal because the surrounding electrons shift toward the positive end. Holes. are usually treated as if they were actual subatornic particles.‘The move- ment of a hole toward the negative end of the cfystal is explained by asvunting that holes are posanvely charged. Similarly. theit rate of movement through the crystal 35 measureal by a yuanbity called mobility, Holes have lower mobilities than electtons, typical values in bulk silicon arc 480 cm°V "s for holes and 139G.em"V"'s | for electrons The lower mobility of holes makes their ess efficient charge carriers. The behavior of a tevice therefore depends upon whether is operation involves holes OF electrons A fice electron and a hole are formed whenever a valence electron is rernoved from the lattice. Both particles are electrically charged and move under the influ cence of clectric ficlus, Flecizons move toward positive potentials, producing att elec tron current. Holes move toward negative potentials. producing a hole current. The total current equals the sum of the electron and the hole currents. Hokss and elec- trons are both called curriers because of their role in transporting electric charge. ‘Camicrs are always generated in pairs since the removall of a valence electron from the Lattice simultaneously forms « hole. The generation of electron-hole pairs ican occur whenever cnergy is absorbed by the lattice, Thermal vibration produces ceartiers. 25 do light, nuclear radiation, electron bombardment, rapid heating, me: ‘chanical friction, and afy ausiber of other processes. To consider only one example, ight of a sufficiently short wavelength can generate electron-hole pairs When a lat- tice atom absorbs a photon. the resulting energy transfercan break a covalent bond to produce & free electron and a fice hole, Optical generation will occur only if the photons have enough energy to break bonds. and this it tur requires light of a suf ficiently short wavelength. Visible ight has enough enexgy to produce electron-hole pairs in most semiconductors Solar cells make use of this phenomenon to convert ‘sunlight into electrical current, Photocells and solid-state camera detectors also em- ploy optical peneration. * Siretran.p 441,HG Tre artof Analog Layout, second Edition FIGURE LA Scheme cepresen- {ations of recombination -es:((A) direct recombination, in. which photon. A. generstes a hole, h'. and an electron.e that solide ad cert phew, nd {B) niece recorbrnateon.in ‘nbtch one of the carers sight bya traps, ana recombi natin takes place at the trap site {Nth the Heraton of heat 4e w wi Just as carriers are generated in pais tbey also recombine in pairs, The exnct mechanism of carrier recombination depends on the nature of the semiconductor. Recombination is particularly simple in the case of a direct-bandgap senstconductor. When an electron aad a hols collide, ihe electron falls into the hole and repairs the broken covalent bond. The energy gained by the electron is radiated away as a pho- ton (Figure 1.44). Direct-handgap semiconductors can, when propedly stimulated, ‘emit light. A fight-emiing diode (LED) produces light by electron-Siole recombi. tion. The color of light emitted by the LED depends on the bandgap energy of the semivoaductor used to manufacture it, Similarly, the so-called phosphors used im manufacturing glow-in-the-dark paints and plastics also contain direct-bandpap semiconductors. Blectron-hole pairs form whenever the phosphor is exposed 10 light. A large nunther of electrons and holes graduslly accumulate in the phosphor. ‘The slow recombination of these carriers causes the emission of light. Silicon and germanium are Jadirecr-bandgap semiconductors. In these semican- ‘ductors, the callision of a hole aod an electron will not cause the two carriers to re- ‘combine. The electron may momentarily fall into the hole, but quantum mechanical considerations prevent the genetation of a photon. Since the electron caanot shed ‘excess energy, it is quickly ejected fron the latiice and the electron-hole pair re- forms, In the case of an inditect-bandgsp semiconductor, recombination can only ‘occur at specific sites in the lattice, called traps, where flaws or foreign atoms distort the lattice (Figure 1.48). A trap can momentarily caplure a passing carrier. The trapped carrier becomes vulnerable ta recombination because the érap can absorb the liberated energy. ‘Traps that aid the recombination of carriers are called recombination centers. The ‘more recombination centers a semiconductor contains. the shorter the average time between the generation of a carrier and its recombination. ‘This quantity, called the carrier lifetime, lanits how rapidly a semiconductor device can switch on and off, Recombination centers are sometimes delibesately added to semiconductors to in ‘crease switchang speeds Gold atoms form highly efficient recombination centers in silicon, so high-speed diodes and transistors are sometimes made from silicon von- {aining a small amount of gold. Gold is not the only substance that can form recom- ‘bination centers Many transition metals such as iran and nickel have a similar (if tess (potent) effect. Some types of crystal defects can also serve as recombination centers. Solid-state devices must he fabricated from extremely pure single-crystal materials in ‘order to ensure adequate carrier fifetimes for proper device operation. 1.12. Extrinsic Semiconductors. ‘The conductivity of semiconductors depends upon their purity. Absolutety pure, or intrinsic, semiconductors have low conductivities because they contain unly a fewChapter 1 Device Physics (RAM thermally generated carriers. The addition of certain impurities preatly increases the number of available carriers. These daped, or extrinsic, scmiconduclors can approach the conductivity of a metal. A lightly doped semiconductor may contain only a few parts per billion of dopant. Even a heavily doped semeconductor contains only 2 few hundred parts per caillion due to the limited solid solubility of dopants in silicon. The extreme sensitivity of seruicanductors to the presence of dopants makes it nearly ém- possible to manufacture truly intrinsic matcrial. Practical sermiconduetor devices are. therefore. fabricated almest exclusively from extrinsic material Phosphorus-doped silicon is an example of an extrinsic seraiconductor. Suppose 4 small quantity of phosphorus is added to a silicon crystal, The phosphiorus atoms are incorporated into the crystal lattice in positions that would otherwise have been occupied by sitwon atoms (Figure 1.5). Phosphorus, a group-V lenient, has five va- Jence electrons, The phosphorus atom shares four of these with its four oeighboring atoms. Four bonding electron pairs give the phosphorus atom total of eight shared electrons These, combined with the onc remaining unshared electron, result in a total of nine valence electrons Since eight electrons entirely fill the valence shell. no room remains for the ninth electron. This electron is expelled from the phosphorus atom and wanders freely through the crystal lattice. Each phosphorus atom added to the silicon lattice thus generates one free electron, Preaphoras atom (donor? See eess Feoe elesteo “The loss of the ninth electron leaves the phosphorus ator with @ net positive ‘charge. Altbough this atom is ionized. it does not constitute # hole. Holes re elec tron vacancies created by the removal of electrons fram a filled valence shell. The Phosphorus atom has a full valence shell despite its positive charge, The charge as- sociated with the .onized phosphorus ecom és therefore immotile, ‘Other group-V clements will have the same effect as phosphorus. Each atom of a ‘group V element that is added tn the Lattice will produce one additional free clec- tron. Elemenis that donate electrons fo u semiconductor 9 this manner are calfed donors Arsenic. antimony. and phosphorus are all used in semiconductor processing 4s donors for silicon, A semiconductor doped with Farge number of donors has a preponderance of electrons as carriers. A few thermally generated holes still exist, but their numbers actually diminish in the presence ef extra electrons, This ovcurs because the extra electrons increase the probability that the hole will ind an electron and recombine, ‘The targe number of free electrous in N-type silicon greatly mcreases its conductiv- ity (and prcatly reduces its resistance). Asemiconductor doped with donors is said to he A-type, Heavily doped N-type sil icon js sometimes marked N+. lighily doped N-iype slicon N-. The plus and minus symbols denote the relative numbers of donors, not electrical charges. Electrons are FIGURE 1.5 Simplified erptat strectuxe of phospharas-doped siliconHE the Att of Analog t ayout, Second Exinon HGURE 1.8 Sinplifved extol structure of boron doped! sono, considered the anayarty curnters in N-type silicon due to their large numbers. Similarly. holes ate considered the nemority carers in N-type silicon. Stricily speakang. ttrinsic silicon has neither majority nor minority carriers because boty iypes are present in equal numbers Boron-doped silicon forms another type of extrinsic semiconductor. Suppose & small number of Moron atumns are addect to the silicon latuce (Figure 1.6). Boron. ‘group- [11 element, has three valence clectrons. Tie boron atom altempts ioshare its valence clectrons with its four neighboring atoms, but. because it has only chree- it ‘carinot complete the fourth bond. Asa result. there are only seven valence electrocis around the boron atom, The electron vacancy thus formed constitutes a hole, This hole is mobil: and soon moves away from the boron atom, Once the hole deparis. ‘the borcin atom is left with a negative charge caused by the presence of an extra electron in its valence shell. As in the case of phosphorus, his charge is immobile and does not coniribute to conduction. Each atom of baron added to the silicon contributes Une mobite hole. oron stom xcept eeeereeeete e6e0% @ 00000000000 Free hile ‘Other group-IE1 elements can also accept electrons and generate botes. Technical dhfGeulties prevent the use of any other eroup-IIl elements in silicon fabrication, bat in. dium és sometimes \sed to dope germarouro,* Any proup-Il] element used as.a dopant will accep electroms frum adjoining toms, so these elements ae celled acepdors A semiconductor doped with acceptors is said to be P-rype. Heavily doped P-type silicon ‘8 sometimes marked P+ and lightly doped P-lype silicon P-. Holes are the majcrity ‘carriers and electrons are the stinority carriers in P-type silicon. Table 1.2 summarizes some ol te Lerminology used to describe extrinsic semiconductors ‘A semiconductor can be doped with both aoveptors and donors. The dopant pres- ent in excess determines the ¢ype uf the siicun and the concentration of the carriers. Wis thus possible to invert P-type silicon to N-type by adding an excess of doours Similarly, str» possible co invert Neiype silicon to P-rype by adding an excess of ae ceptors. ‘The deliberate addition of an opposite-polarity dopant to invert the type of a semiconductor is called countendopeng, Most inodern semiconductors are made by selectively counterdopmg silicon to form a series of P- and N-type regions, Muct) more will be sail about this practice in the next chapter. * masediticutes ned limited sotd salty and income dopant cnceanen Indwn doped sion suf 3 the late: problem A cern amen cf energy eure Worries cepant wk a8 Io penerste & Ince carnes, Random sera vibetwnkslito ean Perea, choaphors arse and acon hc, ‘a entarn herowes fully sone oa at elevated teripratures. Tos etches rererthy bean exploit prodhce what tec very ip slPen. See H. Tien J Map, BTytoe, wane! Reka “A Comparative Stay fadiue and Hw Leyplanaed Sibeor Biles Tansitons"SEEE Thoms cm Elcom Desir, Vol AK. 031. 200 pp 25252824If counterdeping were taken to extremes, the entire crystal lattice would consist of an equal ratio of acceptor and donor atoms The to types of atonis would be present in exiclly equal unbers. The resulting crystal would have very few free cat Fiers and woud appear to be an intrinsic semiconductor. Sich compound semicon ductors actuatly exist The mest familiar exampte is gaia arsenide, a compound of galliuro (a group-ttf clement) and arsentc (a group:V clement), Materials of this Sort are called 1M-V compound semiconductors. They inelade nat only gallium ar- senide but also gallium phosphide, indium antimonide, and many others Many I1E-V Compounds are direct-bandgap semiconductors, and some are used in constructing, ight emitting dliodes and sernicanductor lasers. Gallium arsenide: is also employed oa imited extent for manufacturing very high-speed solid-state devices, including, integrated circuits IE-VI compound semiconductors are composed of equal mix- lures of group-H] and group-VI elements Cadmium sulfide isa typical IT-Vi com- Pound used to construct photosensors. Other H-VE compounds are used as Phosphors in cathode ray tubes. A final class of semiconductors includes IV-IV. ‘compaunds such as silicon earbide, ‘Compound semiconductors offer an oppurtunity to taifor the physical properties ‘of the material to the requirements of the application. They have proven co be of tremendous value ia the development of optical devices such as LEDs and lasers Unfortunately, manufacturing difficulties have hampered their use in integrated cit- cunts. Of all the possible compound materinis,anly germanium-doped silicon seems to be compatible with high-volume low-cost integrated circuit manufacture. 1.1.3. Diffusion and Drift ‘The motion of carriers Uhrough a silicon crystal results from two separate processes, Diffusion is a tandom process caused by thermal agitation, while drift is a unidicee tional movement of cartiers caused by electric iclds ‘The cartiers within a semiconductor are constantly in motion, Each cartier moves ina random direction until it strikes an atom, The carrier bounces off this atom and tcavels in a diferent direction until it steckes another atom. This process oocurs aver and over again. causing the cartier to leap and jerk about m an unpredictable fash- ion. like a drunkard staggering about in 2 darkened toons, Just 86 carriér$ arcin Con- stant motion. so is the semiconductor erystal lattice. The bonds that hold the lattice together act as liule springs A carrier striking an atom may lose enerpy.causing the safricr Lo move more slowly and the atom to begin vibrating. A carrier collicing with a vibrating atocs may actually gain energy.causing the carrier to move more quickly and the atom lo vibrate more slowly. The constant agitation of the crystal Lattice, as Most sevice pists une the terms nype and pay rather than Nype and ype Many sro signers, Including the ano. favor the late fara becouse of preference for eapralitng soch tera as NPN aren. ‘esor ara PR waictonThe Art of Analog Layout, Second Edition _ FIGURE LLY Comparison of enn- ‘Oostion mechanisms for an elec: roe: diffusion (A) and dri superimposed on diffusion (B) Notice the gradual motion of the eleciron foward the positive potenti ‘well as the motion of the carriers within it, creates the macroscopic phenomenon we ‘all heat. Higher temperatures correspond to faster carriers and mote vigorous lal tice vibrations, while lower lemperatures correspond to stawes carriers and less vig ‘orous vibsations. ‘So long as the carriers ate uniformly distributed, thetwaal agitation produces 90 net current flow. Ifa certain number of carriers happen to mave leftwards, on aver age an equal number move rightwords. However, thermal agitation can result ina net current flow if the carticrs are not uniformly distributed. Imagine a situation where 20 carsiers lic ko the ripht of a certain point, but only 10 carrecrs Li to the Heft, Of the 20 carriers an the right, about half (say. 10) move lefcwards. OF the [0 carriers fon the left, sbout half (say, 5} move rightwards. The difference between these 160 ‘constitutes a net current flow of five carriers 16 the right. This is an example of a diffusion current. Diffusion currems always Mow [rom a region of high carricr concentration to a region of low carrier concentration. Linless some mechanism replenishes the supply of carriers, the diffusion current will eventually redistribute the earners uniformly ‘throughout the erystal and then subside, ‘An electric field exerts » force on any carries within it Electrons arc pulled to- ward positive potentials. while holes are pulled toward negative potentials, These forces accelerate the carriers. If they did not collide with anything, the carriers ‘would soon be traveling at enormous speeds This docsn't happen, because the car- riers constantly collide with the atoms that form the erystal lnttios. Because lattice callisions occur so frequently. only intense clectric fields produce any perceptable increase un instantaneous carrier velocities. ‘Although weak electric fields bave negligible effects upon instantaneous carrier Vetoeities, over a long period of time they ean displace carriers and tbus cause elec- ric currents to fhow. Even the weakest electric field inexorably nudges electrons to- ‘ward positive potentials and holes toward negative ones After a sufficient length of time.a gradual shift in the positions of carracrs becomes evident (Figure 7B). The gradual movement of carsiers under an electric field is called drift. Electrons rift toward positive potentials and holes drift toward negative ones. The drift of catriers results in a rift current co D hols: A Bi standacd sees C.B- industey symbols (fo of «| -| terminal): Feindostry sya- Lan 4 as cs F 6 1 K 6, ie Subuektsomeisenp j voltage MOS symbols. @ ae feet eae ae " Syutols A.B. E.G. ard H arc used by varius aurbos:ste A.B. Grcbene, Bipolar and MOS Analog Iae- raed Ceows Design (New You: Soha Wiley aud Song 964), pp. 17-L13 ako FB. Gray aod RO. Meyes, Analys ond Design of Analog lterased Circuit 3408 (New York be, Wiey and Sos 1993). 9.60. The 4, Solat Steve Cie ana yes thee termonal MOS symbols tut diferemtates FMOS dence by plucion 6 Dabble ca eis gate ladeChapter1 Device Physics simitarities between MOS and bipolar circuits, Symbols E and F are often employed ‘when the backgates of the transistors connect to known potentials. Every MOS tran- sistor has @ backgate, so this terminal must always connect to something, Symbols E and F are potentially confusing, because the reader must infer the Backgate connee- tions These symbols are oonetheless very poptilar because they make schematics much more legible. Symbols G and H are often used for depletion-mode devices, where the solid bar from drain to source represents the channel present at zero bias ‘Symbols | and J are sometumcs employed tor asymmetric transistors with high-voltage eaing, and symbols K and L are used for symmetric transistors with high-voltage ter- ‘minions for bath source and drain, Versions of symbols G-L that mehide explicit backgate conneetions are also used. There arc many other schematic symbols for MOS transistors; the ones shown in Figure 1.24 form only a representative sample. Returning to the discussion of threshold voltage. the dielectric also plays an im- portant role in determining the threshuld voltage A thicker dielectric weakens the clectric ficid hy separating the charges by a greater distance. Nhus,thicker dielectrics increase the threshold voltage while Uuinner ones reduce it In theory. tbe material of the dielectric also affeets the electric field strength. fn practice, most MOS tran- sistors use pure silicon dioxide as the gate dielectric. This material can be grown in ‘extremely thin films of exceptional purity and uniformity: no other material bas comparable properties, Alternate dielectric materials therefore have very lnnited ‘application. ‘The gate electrode material also affects the threshold voltage of the transistor. ‘As mentioned previously. an electric field appears across tbe gate diclectrac when the gate nnd backpate are showted together. This field is proportionat to the contact, potential that would cxist if the gate and backgate materials touched, Most practi- ‘cal transistors use heavily doped polysilicon for the gate electrode. The threshold voltage of such a transistor can be varied to a limited degree by changing its gate in ‘A potentially troublesome source of threshold voage variation comes from the presence of excess charges in the gate oxide or along the interface between the ‘oxide nnd the silicon surface, These charges may consist of ionized impurity atoms, trapped carriers, or structural defects The presence of trapped electric charge in the diclectric or along its interfaces alters the electric field and therefore the threshold ‘Yollage- If the amount of trapped charge varies with time, temperature, or applied bias, then the threshold voltage will also vary. This subject is discussed in greater de~ tail in Section 4.2.2. 14.2. LV Characteristics ‘The performance of an MOS transistor ean be graphically illustrated by dcawing & family of I-V curves similar to those used for bipolar transistors. Figure 1.25 shows a {yPical set of curves for an enhancement NMOS. The source and backgate were con- nected together 10 obtain these particular curves. The vertical axis measures drain current Jp, while the horizontal axis measures train-to-souree voltage Vps. Fach curve represents a specific gate-to-source voltage Vs. The general character of the cucvcs resembles that of che bipolar transistor shown itt Figure 1.21, bue the family of curves for an MOS transistor are obtaloed by stepping gate voltage, while those for a bipolar transistor are obtained by stepping base current. Soe authors we toe erm made -ga field effect envisior((GFET to cfer to al) MCS-the trncetrs, cluding Gone with woncnide Oesse3The Art of Analog Layout, Second Edition FIOURE 1.25 Typical I-V plot of fan NMOS transistor. FIGURE 1.26 Behavior of a (MOS transistor under bias: (A) Vos = OV (trode region): (B) Vag ~ 10°V (saturetion re- ion). Seturation region 3V 6V OM RV SW BY At low drain-to-source vollages, the MOS chanine] behaves resistivety, aod the Grain current increases linearly with voltae. This region of operation is called the linear region, Ohmic region, of triode region. ‘This roughly cortesponds to the satu jan region of a bipolar transistor. At higher Grain-to-source voltages, the rate of increase of the drain current dimineshes. The drain current levels off ¢o an approxi- rmalely constant value when the drain-to-source voltage exceeds the difference be- tween the gate-to-source voltage and the threshold voltage. This region is called the Saturation region, and it roughly corresponds to the forward active region of a bipo- lar transistor. The term soturation this has very different meanings for MOS and bipolas transistors “The behavior of the MOS transistor in the linear region is easily explained. The ‘channel acts as a file of doped silicon with a characteristic resistance that depends tupan the carrier concentration. The current increascs linearly with voltage. exactly a3 ‘one would expect ofa resistor. Higher gate vollages produce larger carrier coaccn- tions and therefore lessen the resistance of the channel. PMOS transistors behave similarly to NMOS transistors, but, since holes bave lower mobilities than electrons, the apparent resistance of the channel is considerably greater. The effective resist- ance af att MOS transistor operating in the triode region ts symbolized Rasjo.). MOS transistors saturate because of a phcnomenon called pinch-off. While the drain-to-source voltage remains sinall, the channel remains of a uolform thickness (Figure 126A), As the drain voltage rises, the drift current in the channel sweeps carriers inta the érain and thins the drain end of the channel. Eventually, the drain ‘end of the channel vanishes entirely, and the channel is said to have pinched off (Figure 1.26B), Carriers move down the channel propelled by the relatively weak ov mov wy Deke Chunoes — LovatoChapter 1 Device Phy ‘electric ficld along, it When they reach the edge of the pinched-off region, they ace ‘sucked across the depletion region by the strong electric field. The voltage drop across ‘the channel does not increase as the drain voltage is increased; insted, the pinched ‘olf region widens. Thus, the eirain current reaches a limit and ceases 1a increase. “The drain current curves actually tilt stight’y upward in the saturation region. “This tilt is caused by channel length modulation, which és the MOS equivalent of the Early effect, Increases in drain voltage cause the pinched-otf region to widen and ithe channel fength to shorten, The shorter channel still has the same potentia) drop so the electric field intensifies and the carriers move more rapidly. The drain current thus increases slightly with increasing drain-fo-source voltage. The I-V curves of Figure 1.25 were obtained with the backgate of the transistor connected to the source, Ifthe backgate is biased independently of the source, then the appacent threshold voltage of the traasistor will vary. If the source of an NMOS stansistor is biased above its backgate, then its apparent threshold voltage increases. Ifthe source of a PMOS transistor is biased below its backpate, then its threshold voltage decreases (becemnes nore negative). This backate effector body effect. aris. es because the backgate-lo-source vollage modutates the depletion region beneath the channel, This depletion region widens as the backgate-to-source differential in: creases, and it intrudes into the chanel as well as into the backgate. A high back gale-to source differential will thin the channel, which in turn raises the apparent Threshold voltage. The intrusion of the depletion region into the channel becomes more significant ax the backgate doping rises, and cis in turn increases the magri- tude of the body effect. MOS transistors are normally considered majority carrier devices, which conduct only affer a channel forms. This simplistic view does mot explain the low levels of conduction that occur at gate-to-source wollages just below the threshold voltage. ‘The formation of a channel is a gracual process. As the gale-to-source voltage in- creases, a depletion region first forms, then the gale attracts smal) numbers of mi- nority curriers to the surface. The concentration of minority carriers rises as the voltage increases, When the gate-to-soutce voltage exceeds the threshold, the num. ber of minority carriers becomes so large that the surface of the silicon inverts and a channel forms. Before this o¢eurt, cunt cartiers.can still move from the source to the drain by diffusion. This suéthreshold conduction prociuces currents that are much smaller than those that would flow if a channel were present. However. they tare still many orders of magnitude greater than junction leakages Subthreshold conduction is typically significant only when the gate-to-source voltage (3 within, about 03 V of the threshold voltage. This is sufficient to case serious leakage prob- ems in low-¥V, devices. Some electrical circuits actually take advactage of the expo- ential voltage-to-current relationship of subthresbold conduction, but these circuits cannot operate at temperatures much in excess of 100°C because the junc= tion leakages become so large that they averwhelm the tiny subthreshold currents. As with bipolar transistors, MOS transistors can break down by either avalanche cor punchthrough. [fhe voluage across the depletion region at the drain becomes 50 large that avalaoche multiplication occurs. the draia current increases rapidly. Simitary, ifthe entire channel pinches off, then the source and drain will he shorted bby the resulting deplelion region and the transistor wll punch through. ‘The operating voltage of an MOS transistor is often iimited to a value consid erably helow the onset of avalanche or punchthrough breakdown hy a Fong-term degradation mechanism called hot carrier injection. Carriers that traverse the pinched-off partion of the drain are accelerated by the strong electric field present here. When these hot carriers collide with atoms near the silicon surface, some of them are deflected up into the gate oxide, and a few of these become trapped.The Art of Analog Layout, Second Edition FIGURE 1.27 Cross section of an N-channel BEET transistor ‘operating in the near region (A) nu in sanuration (B} tnboth diggrants.§ ~ Source, 1D» Draic. Gi ~ Gate. and BG = Backgate Slowly, over # fong period vf operation, the concentration of these trapped carzi- ‘urs increases aod the thresbold voleage shifts. Hot bole injection occurs less readi- Iy than hot electron injection because the lower mobility of holes limits their velocity and therefore their ability to surmount the oxide interface, For this rea- son, NMOS transistors are frequently limited to lower operating voltages thant PMOS transistors of similar consteuction, Various techniques have becn devised to limit bot carrier injection (Section 12.1) JFET TRANSISTORS ‘The MOS transistor represents only on¢ lype of field-effect transistor, Anwther is the junction field effect wansistor ar JFET. This device uses the depiction regions surrounding reverse-biased junctions as a gate diclectric. Figure: 1.27A shows 2 crosssection of an N-channel JFET This device consists of a bar: ‘of lightly doped N- type silicon called the body into which two P-type diffusions have been driven {rom Oppesite sides The chin region of Ntype sibcon remaining between the junctions Sours the channel of the SFET. The two diffusions act as the gate and the beckyare, ‘and the opposite ends of the body form the source and the drain. Piached-ot regia Pays type gave - Naype body p 5 D —G “ Paaype hackuane 8G Channel — ‘Suppose that ail four terminals of the N-channel JFET are geounded!. Dey regions form around the gate-body and hackgate-bedy junctions These depl exions extend into the lightly doped channe), hut they do not actually touch one an- ‘other. A chancel therefore existe from the drain to the source. Ifthe drain voltage fines above the source voltage, then current flows through the channel from drasn to snurce. The magnitude of this current depends on the resistance of the channel, which m turn depends on its dimensions and doping As tong as the drain-to-sousce voltage remains small, it does not significantly alter the depletion regions bounding, the channel. The resistance of the channel therefore remains constant and the drain- to-source voltage varies linearly with drain current. Under these conditions. the JFETT ts ssid to operate in its Linear region. This region of operation corresponds to the linear (or triode) region of an MOS (ransistor. Since a channel forms at Vejs ~ 0, the JFET resembles a depletion-mode MOSFET rather than an enhancement mode one. “The depletion regions at the drain end of the JFET widen as the drain voltage increases The channel becomes increasingly constricted by the encrimachment of the opposing depletion regions. Eventually, the depletion regions meet ane pinch off the channel (Figure 1.278}, Drain current still flows dirough the transistor even though the channel bas pinched off. This current originates at the source terminalChapter 1 Device Physics EE and consists of majority carriers (electrons). These carriers move down the channel Until they reach the pinched off region. The large latcral clectricficid across this z¢- ‘gion draws the carriers across into the neutral drain. Further increases in deain voltage bave little effect once the channel has pinched ol The pinched-off region widens slightly. but the dimensions of the channel remain ahout the same. The resistance of the channel determines the magnitude of the drain current. so this #lso reruains approximately constant, Under these conditions, the JET is said to operate in sanzration. “The gate and backgate electrodes also influence the current that flaws through the channel. As magnitudes of the gate-hody and backgute-body voltages increase, the reverse biases across the gate-body and backgate-body junctions slow)y increase. The depletion repions that surround these junctions widen and the channel constvicts. Less current can flow through the consiricted channel. and the drain-to-sovurce volt- ‘age required to pinch off the channel decreases As the magnitudes af the gate and bbackgate voltages conbnue to increase, eventually the channel will pinch off even ax Vos = 0. Once this occurs, no curtent can flow through the transistor regardless of drain-to-source voltape, and the transistor i said to operate in curoff Strictly speak- ing itis not the depletion region that blocks the casrier flow, but rather the electric field within the depletion region. In cutoff, the fiekd Is oriented to that the pinched- off portion of the N-JFET channe! is negative with respest ko the source, thus pre- venting electrons from flowing across the depletion region. By contrast, the pinched-uff portion of a sarurated N-IFET channel is positive with respect to the source. and electrons can therefore freely flow across the depletion region from cchanne} to drain, Figure 1.28 shows the I-V characteristics of 20 N-channel SFET whose gate and backgite clocirodes have been connected to one another. Each curve represents a differcrt value of the gate-to-source voltage Vac. The drain currents are at their gremtest when Vis = 0, and they decrease as the magnitude of the gate voltage in- creases, Conduction ceases entirely when the gate voltagc equals the turnoff voliage ¥,. The turnoff voltage qualitatively conresponds to the threshold voltage of at MOS transistor. The comparison must not be taken too far. however, as the conduc tion equations of the two devices difler considerably. ‘The rain current curves of the N-JFET tlt slightly upward in saturation due to channel length modulation. This effect is analogous to that which occurs in MOS teansistors. The pintched-off region of the JFET lengthens as the drain-to-source voltage increases. Any increase in the length of the pinched-olf region produces FIGURE 1.28 “Typical I-V plot of ‘ao NJFET transistor with Ve = “BY. 3¥ wv av wy Zy xvThe Art of Analog Layout, Second Edition a FIGURE 1.29 Symbols for an N- chanoet JFET (A) and a P- chanel FFET (B). corresponding decrease in the length of the channel. The effect of cheonel leogth ‘modulation is usually quite small because the channel length greatly exceeds the length of the pinched-off region Either of «wo mechanisms can cause drain-to-source breakdown in the JFET. It the deain-to source voltage is sufficient fo deplete the device from drain contact 10 source contact. then punehthrough will occur. The dimensions of practical SFETS are such that they seidom, if ever, experience punchthrough before impact ioniza- tion begins within the depletion region. Once impact sonization begins, the device avalanches in much the same manner as a reverse-hiased PN jnnctlon. ‘The source and drain terminals of a JFET can often be interchanged without af- fecting the performance of the device. The SFET structure of Figure 1.27A is an ex- ample of such a symmetnc device. More complex JFET structures sometimes ‘exbibit differences in source and drain geometries that render them asymmetric. ‘Most JFET steuctures short the gate and backgate serminals. Consider the device ‘of Figure 1.27A. The channel is bounded on the left by the source,on the right by the drain, on the top by the gate, and on the botiom by the backgate. The drawing does not show what bounds the channel on the front or the reat. In most cases, these sides ‘of the channel are also bounded by reverse-biased junctions that are extensions of the gate-body and backgate-body junctions, This arrangement necessitates shorting the gate and backgate. Figure 1.29 shows the conventional schematie symbols for N-channel and P-channel JFET transistors The arrowhead on the gate lead shows the orientation of the PN junc- tion between the gate and the body of the device. The symbol does not explicity iden- Lily the source and drain terminals, but most circuit designers orient the devices s0 that ‘he drain of ani N-JFET and the source of a P.IFET lie on top. i ‘ . a —L : 4 w " SUMMARY Device physics is a complex and ever-evolving science. Researchers constantly de- vyelop new devices and refine existing ones Much of this ongoing research is highly thenretical and therefore lies beyond the scope of this text. The functionality of most semiconductor devices can be satisfactorily explained with relatively simple and imtuitive concepts ‘This chapter emphasizes the role of majority and minority catrier conduction ‘aeross PN junetions Ita junction is reverse-biased, then the majority carers oo either side of it are repelled and a depletion region forms. If the junction is forward-biased, then majority earners diffuse across and recombine to create a net current flow across tbe PN junction. The PIN junction diode employs this phenomenon to rectify signals, ‘When two junctions are placed in close proximity, carriers emitted by one junc- tion can be collected by the other betore they can recombine. The bipolar junctionChapter 1 Device Physics transistor (BIT) consists of just such # pair of closely spaced junctions The voltage cross the base-emitter junction of the BUT controls the current owing from col- Jeetor to emitter. If the transistor propecly designed, then a smal base current.can control a moch larger collector current The BIT therefore serves as an amplifier ca- pable of transforming weak signals into much stronger ones. Thus. for example, a BIT can amplify a weak signal picked up by a radio receiver into a signal strong enough to drive a loudspeaker. ‘The metal-oxide-semiconductor (MOS) transistor relies upon electrical fields pro- Jected across a dielectric to modulate the conductivity of a semiconductor material. A Suitable valtage placed upon the gate of a MOS transistor produces an electric Fietd that attracts minority carners to form a conductive channel. The gate is insulated from the remainder of the transistor,so no gate current is required to maintain con- duction MOS circuitry can thus potentially operate at very low power levels. ‘The junction diode, the bipolar junction transistor, and the MOS transistor are the thre: most important semiconductor devices, Together With resistoxs and capac itors. they form the vast majority of the elements used in modern integrated circuits, ‘The nest chapter will examine how these devices are fabricated in u production en- vironment EXERCISES |, What are the relative proportions of aluminom, gallium. and arsenic atoms in intrinsic sluninam gaitum arsenide? 1.2. A sample of pure sitcom ts doped with exactty 10" atoms‘cn? of baron and exactly 10" cyomscrn' of phosphorus. ts the doped sample P-type or N-ype? 1B. The istantaneous vetosily of carsieesin silicon is almost unaffected by weak etectic fields yet the average velocity changes deamattcally, Explain this observation in teste of eft and éfusion. 1A. Allsyer of mtsinic silicon tym thick & sandwiched hetween leyers of Paype and] Nype ‘ican, oth heavily doped. Draw diagram hisrating the depletion eegioes that form se the resulting strc LS. A cenain process incorporates two different N+ diffusions that can be combined with aP- daffasion to produce Zencr diodes. One of the resulting diodes has a breakdown voltage of 7 V. while the other hasa breakdown voltage of 10 V. What causes the liffeenee in breakdown voltages? Je When the collector and emitter leads of an integrated NPN transistor are swapped, the sistas continues to Function, but exhibits a greatly reduced beta, There are several possble reasons for this behavior, explain at least one- 17. It certain transistor has a beta of 2nd annthe: transstor has a base wie 28 wide and hall as heavily doped, thea what is the approximate beta of the second transistor? ‘What other electra characteristics of the Gevices will vary.and how? 18. A curtame MOS transistor bas a threshold vollage of —2.5 V. Ifa small amouat af boron s added to the channel regson, the threshold voltage shifts to ~0.6 V. ts the ltursistor PMOS o NMOS, and sit an enhancement or a depletion device? 19. te PIMOS transistor has thresbold voltage of 0.5 V when constrocted ustag, 2200 ene wt hictbresbold wehape increase ox decease he onde hickened toa AP 1.10. 4 certar NMOS transistor asa threshold voltage of 05 Vethe gate-to-source voltage Yas ofthe tarssor inset 102 V, end the deain-to-source voltage Vic is set (0.4 What is the relative effect of doubling the gate to-source voltage versus doubling the dain o-souree voltage. sed why? LIILA certain silicon PN junction diode exhbits a forvard voltage drop of 620 mV when ‘operated ata Forward current of 25 pA ata temperature of 25°C. Whit is the appronnaate forward drop of this éiodc at ~ 40°C? At 125°C? EEEa The Art of Analog Layout, Second Edition 112-Two JFET teansistors differ ooly in the separation between their gatc and backgate; ‘none transistor these two regions arc twice as fae apart as in the other transistor In ‘what ways do the electrical properties of the two transistors differ? 1A3.A voliage of 30 V 3 piaecd across a 1000 ym-king uniformly doped monocrystalline silicon resistoz, Wil this resistor obey Ohm's law? Why? 114, Based or an analogy with MOS transistors, suggest an appropriate symbol for a SFET having separate gate and backgate connections 1.5.A revere-biased PN junction exhzbitsa characteristic capacitance that diminishes as the voltage across she junction increases Explain what causes this capacitance and its behavior with changing voltages.Semiconductor Fabrication ‘Semiconductor devices have long been used in electronics The first solid-state rect fiers were developed in the late nineteenth century. The galena erystal detector, in- vented in 1907, was widely used to consizuct crystal radio sets, By 1947, the physics of semiconductors was sufficiently understood to allow Bardeen and Brattain to ‘consttuict the first bipolar junction transistor. In 195%, Kilby constructed the first in- tegrated circuit, ushering in the era of modern semiconductor manufacture. “The impediments to manufacturing latge quantities of reliable semiconductor devices were essentially technological, not sclentific. The need for extraordinarily Pure materials and precise dimensional cantrol prevented early transistors and inte- rated circuits from reaching their full potential. The farst devices were little more ‘than lahoratary curiosities. An entire new tech nology was required to: mass produce them. aind this technology is still rapidly evolving. ‘This chapter pravides a brief overview of the process technologies currently used to manufacture integrated circuits. Chapter 3 then examines three representative process flows used for manufacturing specific types of analog integrated circuits, SILICON MANUFACTURE Integrated circuits are usually fabricated from silicon, a very common and widely distrsbuted element. The mineral quartz consists cntircly of silicon dioxide, also known as silica. Ordinary sand is chiefly composed of finy grains of quartz and is therefore also mostly silica, Despite the abundance of its compounds, elemental silicon does not occur natu- rally. The clement can be artificially produced hy heating silica and carbon an an electric furnace. The carbon unites with the oxygen contained in the silica, leaving ‘more-or-less pure molten silicon. As this cools, numerous minute crystals form and 70W together into a fine-grained pray soli. This fornt ef silicon is said to be poly: ystaltine because it contaims a multitude of crystals. Impurities and. a disordered crystal structure make this mevaiturgical-grade polysilicon unsuited for semicomduc~ tor manufacture.The Art of Analog Layout, Second Edition Houme 21 Crocheats process ec eternal ‘for growing silicon eryseals, Metatlurgical-grade silicon can be further refined 1 produce an extremely pure semiconductor-grade polysilicon. Purification begins with the conversion of the exude silicon into a volatile compound, usually trichlorosilane. After repeated distil lation, the extremely pure ttichlorosilane is reduced to clemental silicon by means of hydrogen gas. The final product is exceptionally pure. but sti) polyerystalline. Practical integrated cireaits can only be fabricated from single-crystal material, so the next step consists of grewing a suitable crystal 21.1. Crystal Growth ‘The principles of crystal growing are both simple and (arniliar, Suppose a few csys- tals of sugar are added to @ saturated solution that subsequently evaporates. The sugar erystals serve as seeds for the deposition of sdditional sugar molecules Eventually the crystals grow to be very large: Crystal growth would occur even in the absence of a seed, but the product would consist of a welter of small intergrown crystals The use of a sced allows the growth of larger. more perfect exystals by sup> pressing undesired nucleation st Jn principle.silicon erystals can be-grown in much the'same manner as supar erys- ls. In practice. no suitable solvent exists for silicon, and the crystals must be grown from the molten clement at temperatures in excess of 1400°C. The resulting crystals fate at least a meter in Length andl ten centimeters in diameter, and they must have a nearly perfect crystal structure if they are to be useful to the semconductor indus: ‘ty. These requirements make the process technicaly challenging. “The usual eoethod for growing semiconductor grade silicon crystals is called the ‘Crochraiska process. This process, illustrated in Figure 2.1, uses a silica crucible charged with pieces of semi-grade polycrystalline silicon. An eleetric furnace raises the temperature of the crucible until all of the silicon melts, The temperature es then reduced slightly and a small seed crystal is lowered inte the crucible. ‘Controlled coolme of the melt causes layers of silicon atoms ta deposit upon the seed crystal. The 10d holding the seed slowly rises so that only the lower portion of the growing crystal feanains in contact with the molten silicon. In this suanner, laepe silicon crystal can be pulled centimeter by centimeter from the melt. The shaft holding the crystaf rotates slowly to ensure uniform growth, The high surface ten- ‘sion of molten silicon distorts the crystal into 4 cylindrical rod rather than the ex- pected faceted prism. ‘The Czochralski process requires. carcful controt to prowide crystals of the de- ‘sired purity and dimensions Abtomated systems regulate the temperature of the. Siison crystal Seederysal — Men sianGhapter2 Semiconductor Fabrication IEE melt and the rate of crystal growih. A. small amount of doped polysilicon added to the mill se%s the duping concentration in the crystal. ln addition to the deliberately introduced impurities, oxygen from the silica crucible ond carbon from the heating slemenis dissalve in the motien silicon and hecome incorporated into the growing. crystal. These impurities subtly influence the elcetrical properties of the resulting sil icon. Once the crysta} has reached its final dimensions. it i lifted from the melt and. is allowed to slowly cool to roam temperature. The resulting cylinder of monocrys+ talline silicon is called an ingot Since integrated circuits are formed upon the surface of a silicon crystal and pen- erate this surface to no great depth, the ingot is customarily sliced into numerous thin circular sections called wafers. Each water yiekis hundreds or even thousands of integrated circuits The larger the wafer. the more integrated circuits it holds and the greater the resulting economies of scale: Most modern analog. processes employ either 150 inm (6°) or 200 mm (8°) wafers. State-of-the-art digital processes now ese 300 mim (12”) wafers, typical ingot measures between I and 2meters in length sand cari provide hundreds of wafers. 21.2. Wafer Manufacturing, ‘The manufacture of wafers consists of a series of mechanical processes. The two ta- peted ends of the ingot are sliced off and dliscarded. The remainder is then ground : imo a AOCOS:A New HC Testnatony.” Micreelactroncs ant Reba: Vol 19,1971 pp 41-472 ~ Recuc HF. Yu, eno Manisclen,"Topolny of Silcon Sonicures enh Recened S003" Elkcrachem, Soe, VoL LRAT, 1974 pp 1729-1037 OURE 2.13 Elfects of dopant enhanced oxidation. FIGURE 2.14 Local oxidution of silicon (LOCOS) processEGE the Artot Analog Layout, Second Eston RIGURE 245 The Kovi effect caused by mtride that grows tunaler the hn’ heak (AD. ‘preventing formation of gate foxx dueing subsequent cnxidalion (B} ‘Once oaidation is complete, the nitride layer is stripped away to reveal the pat- termed oxide CMOS and BiCMOS processes employ LOCOS to gfow a thick field aude over elecicically inactive regions of the wafer The areas not covered by field oxide are ‘ealled mour regions because they form shaliow depressions in the topography of the wafer. A very hin, high-quality gate oxide subsequently grown in the moat regions forms the gate dickectric of the MOS transistors, ‘A mechanism called the Kooi effect complicates the growth of gate oxide." The water vapor typically used to accelerate LOCOS oxidation also attacks the surface of the mitnde film to produce amenonia, some of which migrates bercath the pad oxide near the edges of the nitride window. There it reacts with the underlying silicon 10 form silicon nitride again (Figure 2.15). Since these nitride deposits lic beneath the pad onide, they remain even after the LOCOS nitride ss stripped. Removing the pad ‘oxide prior to growing the gate oxide does not eliminate these deposits because this ‘ich is selective to oxide, nox to nitride. During gate oxidation, the nitride residues act as. an unintentional LOCOS mask that retards oxide growth around the edges of the moat region. The pate oxide at these points may not be sufficiently thick to withstand the full operating voltage. The Kooi effect can be circumvented by first growing @ thin oxide layer and theo stripping it away: Because silicon nitride slowly oxidizes, ths divremy gate oxidation removes the nitride residues and improves the integrity of the true gate oxide grown immediately afterward. Detective ~ — Stiean @ 5 Payne weer nite DIFFUSION AND ION IMPLANTATION Discrete diodes and transistors can he fabricated by forming jonetions into a silicon ingot ducing erystal growth, Suppose tht thessilicon ingot begins as a P-type crystal. ‘After a short peried of growth, the molten silicon is counteriloped by the addition of a controlled amount of phosphorus. Continued crystal growth will naw produce a PN junction embedded in the ingot. Suocessive counterdopings can produce multi- ple junctions in the crystal, allowing the fabrication of grewr-junction transistors. Integrated circuits cannot be grown hecause there iso way to produce differently doped regions in different portions of the wafer. Even the manufacture of simple ‘grown-junction transistors presents 3 challenge, because the thickness and planarity © Kooi Q:vun Lietop end 1 A, Appele"Formatioa of Stevo Naride at 0 S1-S10>tnertice rig Loca ‘Onuotion of Siicon ant aurvan Heat Tiearaneri o¥ Oxidtred Scan in NH; Gand Elecrstem Ses. Ve YEA. 196 pp HHIT-1120,Chapter2 Semiconductor Fabrication [EI of grawn junctions are difficutt to control, Each ccunterdoping also zaiscs the total dopant eoneentretuun, Sore properties of silicon (such as minority eacricr lfetinne) depend upon the total concentration of duping atoms, not just upon the excess of ‘one dopant spccses over the other. The repeated counterdopiogs therefore progres- sively depratle the electrical properties of the silicon. Historically, the grown junction process was soun abandoned in favor of the much more versatile planar process This psocess is used to fabricate virtually all undern integrated circuits as well as the vast majority of modern discrete devices Fipure 2.16shows how a wafer of discrete diodes can be fabricated using planar pro- cessing. A uniformly coped silicon crystal is fist seed to form individual wafers An ‘onde film grown on these waters is photolithographically patterned and etched. A dopant source spun onto the patterned wafers touekes the silicon only where the ‘oxide has been previously removed, The wafers arc then heated in a furnace to drive the dopant into the silicon. which forms shallow counterdoped regions. The Einished wafer can be diced to form hundreds or thousands of individual diedes. The planar process docs not require so many counterdopings of the silicon ingot. thereby al- lowing more precise control of junction depths and dopant distributions, FIGURE 2.16 Formation of dif- ' wie Ne feed Onde ee, rource ‘the planar process. " ES a ie ‘Step 1: Oxide removal Step 2: Deposit dopant Nope dition Step: Driven oupara ‘LA.L. Diffusion Dopant atormscan move through the silicon lattice by thermal diffusion in much the some way 4s carricrs mevy by diffusion (Section 11.3). The dopant atoms arc heay- ter ind more tightly bound to the erystal latte. so temperatures of 800°C wo 1250°C re required to obtain reasonable diffusion rates. Once the dopants have been driv= ‘en to the desired junction depth. the wafer 1s cooled and the dopa atoms become immobilized within the lattice. A doped region formed in this manner is called a difvivon: “The usual process for creating @ diffusion consists of two steps: an initial deposition (or predeposinon) and & subsequent drive (or drive-in). Deposition con- sists of heating the wafer it contact with an external source of dopant atoms. Some lf these diffuse from the source into the surface wf the silicon waler to form a shal low heavily doped region. The external dopant source 18 then removed and the ‘wafer is cated toa higher temperature for a prolonged pend of time The departsThe Art of Analog Layout, Second Eaition TABLE 2.2 Representanee unetion depts sn microns P? stomsicm’ source, stomnsicm’ hockgrcund, 15 deposition. Thr drive). FIGURE 2.17 Simplified dia. gram of a phosphors diftuston furnace using a POC source. introduced ducing deposition are now driven down to form 4 much deeper and Jess. concentrated diffusion. Ifa very heavily doped junction is required, then it is usual- ly unnecessary 1 strip the dopant source from the wafer, and the deposition and subsequent drive can be conducted as a single operation, Four dopants find widespread use in silicon processing: boron, phosphorus. ar- serie. and antimony. Only boron is an acceptor: the other theee are afl donors, Boron and phosphorus clifiusc relatively rapidly, while arsenic and antimony difiuse much more slowly (Table 2.2), Arsenic and antimony are used wherc slow rates of diffusion are advantageous—for example, when very shallow junctions are desired, Even boron and phosphorus do not diffuse appreciably at temperatures below ‘800°C. necessitating the use of special high-temperature diffusion furnaces. Dopam = 980 100°C 100°C Deere | Roxon 0 1s 36 3 Phosphorus as 16 46 “Antimony: on 21 Arsenic a7 20 Figure 2.17 shows a simplified diagram of a typical apparatus for condvcting a phosphiorus diffusion. A long fused silica tube passes through an electric furnace that is constructed to produce a very stable heating:-zone in the middle of the tube. After the walers are loaded into a wafer boat, they are slowly pushed into the fur- nace by means of a mechanical arrangement that conteols the insertion ratc. Dry ‘oxygen is blown through a flask containing liquid phosphorus oxychlorede (POCh, often pronounced “pockle"}. A small amount of POCI, evaporates and is carried by the gas stream over the wafers. Phosphosus atoms released by the decompost- tinn of the POC, diffose into the oxide film. forming a doped oxide that acts ax a deposition source. When enough time has passed to deposit sufficient dupant in the silicon. the wafers are removed (fom the fumiace and the doped oxide is stopped "hee dopants were chosen because they ready woe and beens shy are sificenay soluble tia to Form nes doped ditusigns See FA Twumpote, “Sad SONDDIies of Lapully Elepteslais Gersanian ‘Silico ” Bel Set Feeh J, Vol 29.91.1980, pp 208-288, ‘Colcuiaies using difiesvtes from RS Mller and T Karrine, Devi Bhecirues fr frmpries Cire, 74 ‘ed (New Yor: ohn Wiley so Sons, 198), AS.Chapter2 Semiconductor Fabrication [ERM away (a process called deglazing). The wafers are then reloaded into another fur nace, where they arc heated to drive the phosphorus down to forin the desired dif- fusion. Ifa very concentrated phosphorus diffusion is desired. then the wafers need not be removed for deglazing prior to che drive. With suitable modifications to the dopant source. this apparatus can diffuse any of the four common dopants. Many alternative depesition soorces have heen developed. A gaseous dopant such a8 dihorane (for boron) oF pleosphine (for phosphorus) can be injected direct- ly anto the cartier gas stream. Thin disks of boron nitride ptaced between silicon wafers can serve as.a solid deposition source for boron. In 3 high-temperature ox- izing atmosphere. a little boron trioxide outgases from thése disks to the adjacent wafers Various proprietary spin-on glasses axe also sold as dopant sources, These are purchased in the form of a liquid, After the solution is spun onto a wafer, a brief bake drives out the solvent and leaves a doped oxide layer on the wafer. This $0- ‘called glass then serves as a dopant source for the subsequent diffusion. ‘None of these deposition schemes are particularty well controlled, Even with gaseous sources (which can be precisely metered), nonuniform gas flow around the vwaler inevitably produces doping watiations, For less-demanding processes such && standard bipolar, any of these schemes can give adequate results. Modern-CMOS and BiCMOS processes require more accurate cantrol of doping levels and junction depths than conventional deposition techniques can achieve. Jon implantation {Section 2.4.3) can provide the necessary accuracy at the expense of much more cormplex and costly apparatus. POC, is still used to produce heavily doped N-type regions that cannot be economically fabricated by ion implantation, 2.4.2. Other Effects of Diffusion ‘The diffusion process suffers from a nuniber of limitations, Diffusions can only be performed from the surface of the wafer. limiting the geometries that can be fabri- cated, Dopants diffuse unevenly. so the resulting diffusions do not have constant doping profiles. Subsequent high-temperature process steps continue the drive of previously deposited dopants, so junctions formed early in the process are driven substantially docper during later processing, Dopants ont-

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