Design Techniques and Tradeoffs in Implementing Non-destructive Field Test
Using Logic BIST Self-test
Amit Dutta, Malav Shah, Swathi G. and Rubin A. Parekhji
Texas Instruments, Bangalore, India.
Email:[amitd,m-shah1,swathig,parekhji]@ti.com
Abstract
Periodic testing of electronic devices on the field during
application execution is becoming increasingly
important. In addition, some of these applications are
embedded and real-time, requiring the system to be
operational for extended periods. In such applications,
field test must be cleverly interleaved with normal
operation, such that the latter is not impacted, while at
the same time guaranteeing the correct operation of the
device, and identification of any malfunction or defects
within a reasonable time. This paper discusses the design
techniques and tradeoffs in implementing non-destructive
field test using logic BIST self-test. Three specific
designs aspects are discussed, namely (i) choice of logic
BIST self-test architecture, (ii) optimizations in test time
and additional memory requirements for attaining a
given coverage, and (iii) DUT interface to self-test DFT
logic to enable such form of test and application
interleaving. Data is presented for an IP core, which is
presently being designed in Texas Instruments (India),
wherein such tests are being supported for use in
automotive applications.
Keywords: Non-destructive test, field test, built-in self-test,
logic BIST, system test.
1 Introduction
Safety critical applications require that the hardware on
which they execute be fault free. While traditionally
manufacturing testing with adequate life-time stress tests
has been adequate to guarantee the reliability of the
electronic devices, such form of one-time testing is no
longer adequate for newer process technologies due to
process marginalities and degradation. As a result,
periodic testing on the field during application execution
is becoming increasingly important [1]. Examples of
such applications include medical electronic and
automotive electronic systems. (The latter are governed
by the SIL3 standard [2] to ensure functional correctness
by safeguarding against life-time reliability issues). The
embedded and real-time nature of these applications
requires them to be operational for extended periods. As
a result, it is necessary to interleave the normal
functional operation with the test operation. In such
situations, the field test may have to be performed across
several intervals of normal application execution,
resulting in the need for a non-destructive field test
mechanism.
This paper describes the design techniques and tradeoffs
in implementing non-destructive field test using logic
978-1-4244-4595-0/09/$25.00 
c 2009 IEEE
BIST self-test. Different architecture options are
reviewed and issues in interfacing the DUT with the test
logic for supporting non-destructive field test are
discussed. Various tradeoffs in obtaining the desired test
coverage in a given time interval are examined for
different test data volumes. Some experimental results
are presented for implementations on an IP core which is
currently being designed. It is shown thereby that a
proper choice of the test architecture, test schedule and
DUT interface can significantly improve the quality of
the field test solution. While the tradeoffs are illustrated
and computed for a specific IP core design with a certain
time span (window) available for functional and test
mode operation, the methods described in this paper are
generic and can be adopted on other design modules as
well which require such form of field test support. They
also highlight the advantages and flexibility of adopting
traditional logic BIST based self-test for the purpose of
field test, as also some limitations of such techniques in
meeting very high coverage requirements.
This paper is organized into six sections. Section 2
provides the motivation for the non-destructive field test,
and the associated application requirements. Methods to
interleave functional mode and test mode of operation
are discussed in Section 3, together with specific design
and implementation considerations. Various architecture
options and their tradeoffs are presented in Section 4.
Different seed generation techniques are presented in
Section 5 together with experimental results. Section 6
concludes the paper.
2 Motivation
For the applications being considered, there are a few
important field test considerations to be met for SOCs
being used in automotive systems.
(a) The application is real-time and embedded. As a
result, the functional mode of operation is always
on. Hence offline testing is not an option. The test
mode must hence be interleaved with the functional
operation. This implies that the two modes of
operation be mutually non-destructive, and requires
context switching. Also, the window of operation for
these two modes is not fixed. Hence the test
scheduler must also support variable test execution
time.
(b) While it is desirable to concurrently perform the
dual operations demanded by the application and
required for test, it is so possible only if the DUT
237
 has natural partitions wherein selective portions of
the logic can be manipulated in test mode, without
disturbing the state of the remaining portions. This
also requires a complex control mechanism to
switch between these portions of the DUT. For the
sizes of the modules being considered, such
partitioning was considered infeasible. Hence while
test is performed online, the two modes of operation
are mutually exclusive.
(c) The application takes priority over the test mode of
operation. Hence the test schedule must be created
to provide a specified coverage across various
windows of test mode operation. For the same
reason, while there is no requirement on the latency
incurred to report the detection of a fault, it is
expected that the application can roll-back to a safe
state on the first indication of such detection. As a
result, the fault detection status is reported at the end
of each window of test operation.
Given the above requirements, the decision to support
field test based on logic BIST self-test techniques was
driven by the following important observations:
(i) High structural coverage is possible per window of
test operation, as compared to functional coverage.
Such coverage is measurable, and can also be
selectively directed or augmented as required in
different windows of operation. Also, it is possible
to create a test schedule where some portions of the
DUT are tested more often or on higher priority than
the others. (While this is possible using functional
patterns [3], such forms of directed, selective and
improved coverage are more easily driven through
structural ATPG techniques. Besides scan overhead
has to be incurred to support context save and
restore given the homogeneity of the IP module
being considered).
(ii) Logic BIST offers the advantages of a built-in
decompressor (PRPG) for generating test patterns
and a built-in compactor (MISR) for capturing the
DUTs (with STUMPS architecture) response to the
test patterns [4]. As a result, both the test hardware
requirements and test data storage requirements are
minimized. However, a given sequence of logic
BIST patterns generally provides high coverage
improvement for the first few patterns, and then the
coverage improvement rapidly tapers off. Higher
coverage is possible only through re-seeding
techniques. The re-seeding mechanism also provides
a fit into a window based test scheduling
mechanism, wherein a new seed can be loaded at the
start of a window and the DUT response can be
compared at the end.
(iii) Deterministic BIST (DBIST) from Synopsys has
been considered for primary structural test pattern
generation and application mechanism, since it
238 2009 15th IEEE International On-Line Testing Symposium (IOLTS 2009)
combines the advantages of logic BIST together
with re-seeding [5,6]. (More details are provided in
Section 4. The same solution is also used for
production test on previously designed cores and
SOCs, and hence there is no additional hardware
overhead). The DBIST engine can be driven to
generate patterns based on desired tradeoffs in test
coverage (for a given test time and number of
seeds), test time (for a given test coverage and
number of seeds) and seed storage memory (for a
given test coverage and test time).
It is important to note that logic BIST (and DBIST)
techniques use the STUMPS architecture which naturally
also provides test data volume compaction. While
compaction is indeed desirable since it directly
influences the on-chip memory requirements, it also
forces the test patterns to be dense, i.e. with fewer dont
care-bits, so as to meet the overall entropy requirements
[7]. As a result, the seeds used in such re-seeding
techniques do not have many non-care-bits, and
generation of new seeds from existing seeds is not easy.
Several re-seeding schemes are discussed in the
literature [8,9,10,11,12,13]. However, in this paper, we
have considered a commercial BIST engine which
supports re-seeding, where a given seed is used to
generate a certain (variable) number of patterns, before
being replaced with a new one. (Refer to Section 5).
3 Architecture Considerations for Field Test
As explained previously, periodic field test is necessary
in safety critical applications. A power-on field test tests
the device only when it is powered up. (Schemes for
such form of logic and memory self-test are discussed in
[14]). The solution proposed here is based on a hardware
BIST technique which can be periodically triggered
during an application execution. The technique must be
non-destructive since the functional and test modes are
interleaved. (In this paper, field test for logic alone is
considered, since there are different architectural
tradeoffs. Field test for memories can be implemented
using existing memory BIST techniques).
3.1 Sequence of Operation
Fig. 1 shows the field test controller block diagram and
architecture. The master controller controls the field test
activity. The context save/reload controller manages
DUT content during field test. The self-test engine is
based on deterministic built-in-self-test (DBIST) which
provides scan data to DUT. Fig. 2 depicts the steps
involved in executing non-destructive field test.
3.2 Interleaving Functional and Test Operations
There are several design considerations which must be
met to optimally interleave test operation with functional
operation. These include:
(a) Time slots in the application firmware which are
 available for test must be identified without frozen during the test mode. (iii) Reset and NMI
compromising on the response time of the embedded (non-maskable interrupt) inputs to the DUT should
application. A representative scheme is shown in not be gated off, thereby enabling the application to
Fig. 3. regain control of the DUT. (iv) The state of non-scan
(b) Different slots may not have identical duration and flip-flops must be preserved adequately during the
may not be equally spaced, given the real time test operation, since scan based context save and
nature of the application. Hence both the application restore is not possible. (v) There should be no
firmware and test schedule must interface with each pending instruction in the CPU pipeline or any
other at the window boundaries to save and restore pending request or acknowledgement for the DUT
the application as well as the test context of the from any external module before starting field test
DUT. For example, the application must resume at operation.
Time A2, from where it was halted at Time A1. (d) The DUT state (context) can be saved using scan
Also, the test schedule must resume at Time T2, shifts onto on-chip memory at the end of application
from where it was halted at Time T1. The best window. At the end of the test window, it can be
implementation requires the minimum number of similarly restored. At the end of test window, the
test intervals and minimum test time, (? T over all pass / fail status is generated by comparing the
intervals) without impacting the throughput as well signature in the MISR with the expected one. A new
as the application time ( ? A over all intervals). technique is proposed to ensure that the context
Field test master
restore is correctly done without any cycle mis-
controller matches or state corruption. Two MISRs are
incorporated at the DUT scan inputs and outputs
Context
(Refer to Fig. 4). The MISR at the scan outputs is
Self-test engine (BIST Context
+ control logic) save/reload save activated during context save and that at the scan
controller memory inputs is activated during context restore. A mis-
Scan out
match in the signature in the two MISRs indicates
that the restore operation was corrupted. (This points
Rest of DUT to incorrect data being read from the on-chip
memory used for context data storage). An
CPU additional cycling of the data in the STUMPS
Self-test or
context reload DUT channels can also be done to ensure that the value
shifted into the STUMPS channels of the DUT
Fig. 1: Architecture for non-destructive field test. during the restore operation is also correct.
Application running Application on Context reload/Self-test
L
F Scan in Scan out
No Idle DUT Context reload DUT
S Memory
Yes R (scan chains)
Configure field- Store result
MISR MISR
test controller
Yes
Self-test complete ?
Isolate DUT No Fig. 4: Two pass sanity check.
4 Implementation and Evaluation of Logic
Run
Context save self-test BIST Techniques
Fig. 2: Flow diagram for non-destructive field test. This section describes the implementation choices
available using DBIST to implement logic BIST.
Normal application Test application Various schemes for field test using logic BIST are
analyzed.
4.1 Implementation Considerations
A1 T1 A2 T2 A3 T3 A4
The non-destructive self-test mechanism is being
implemented for an IP core at 90nm process technology
Fig. 3: Interleaving application and test execution cycles. node, operating at 130MHz, as part of an SOC being
(c) There are other IP core specific requirements: (i) targeted for automotive applications. This core has a total
During test, the DUT I/Os are bound to prevent of 3500 flip-flops, which are re-grouped into a STUMPS
external inputs from impacting DUT test, and DUT architecture with 512 scan chains with an average scan
outputs from impacting other modules. (ii) Similarly chain length of 7 flip-flops.
the contents of the memory inside the DUT must be

2009 15th IEEE International On-Line Testing Symposium (IOLTS 2009) 239
 As discussed in Section 2, re-seeding based DBIST from
Synopsys is used for the implementation of field test.
Fig. 5 shows the DBIST architecture. It has been
augmented in multiple forms to support self-test [15,16].
The DBIST tool supported configuration has a PRPG
(and shadow register) of 257 bits, an MISR of 128 bits,
and 256 / 512 STUMPS channels. The reduced STUMPS
length does not influence the result of the test since the
limits are set by the entropy bounds [7]. On the other
hand, it is efficient in terms of test time compression
since with 512 scan chains, the chain length is reduced.
The support for shadow register and MISR make DBIST
a better candidate for field test. The shadow register is
used to load a new seed at the same time that the existing
seed is being unrolled into a pattern that is being shifted
into the STUMPS channels. Higher the width of the
shadow register inputs, the lesser is the seed loading
time. Hence 12 shadow register inputs (maximum
permissible) have been chosen. (These are internal
signals. For production testing with multi-site
capabilities, fewer pins are desirable, and hence fewer
shadow register inputs may be desirable). A 257 bit seed
is therefore composed of 12 segments each of 22 bits.
The MISR is a 128 bit signature register which is read by
a 16 bit CPU bus. Thus, it takes 8 cycles to copy the
signature into internal memory for comparison. Several
enhancements have been made to the DBIST controller
to support field test. These include re-seeding through
the device internal interface to the DBIST controller,
programmable pattern counter for each seed, internal
clock selection, signature storage and comparison, etc.
Shadow scan in
BIST_cl
Shadow register BIST
controller
PRPG
Phase shifter
DUT
Core_Clk
Compactor
MISR
MISR_scan_out
Fig. 5: DBIST architecture.
4.2 Evaluation of Different Schemes for Field Test
The analysis in this section gives an insight into how the
logic BIST engine can be employed for performing the
non-destructive self-test at regular intervals during the
application. Such an analysis helps to make smarter
selections such as:
For a given bound on test time, (i.e. number of
intervals * time per interval), what is the minimal
coverage desirable and maximal coverage attainable.
240 2009 15th IEEE International On-Line Testing Symposium (IOLTS 2009)
For a given coverage requirement, what is the
maximum test time affordable and minimum test
time required.
For given bounds on test time and coverage, (i) how
many seeds are required, (since the methodology is
based on expanding seeds to obtain as high field
coverage in as minimal a time as is possible), and
(ii) how are the seeds generated and loaded in the
core logic which is being tested.
Importantly, these options bring out the optimality trade-
offs in seed storage memory, test time and test coverage
based on the various design and application constraints,
resulting in different implementation scenarios.
Based on the application, it has been determined that
about 10% of the functional MIPS can be utilized for
test, and based on the firmware architected, an
application window is about 40s. Accordingly, for each
such window, 36s are used for functional operation, and
4s for test operation. At 130MHz operation, this
corresponds to about 520 cycles. An analysis was done
on various feasible options with bounds on seed storage
memory, coverage and test time. The available 520
cycles per test window need to be shared amongst the
following steps of self-test. (Refer to Table 1):
(i) Context save and restore operations: For IP core
under consideration with STUMPS length of 7 flip-
flops, context save and restore will require 7 shift
cycles each to shift out all 3500 flops. Since an extra
sanity check phase (as explained in section 3.2(d) is
involved, additional 7 cycles are required, making a
total of (3*7) = 21 cycles.
(ii) New seed loading: This requires ~22 cycles (257 /
12) for loading a single seed and 22*S cycles where
S is the number of seeds required per window.
(iii) Pattern shifting: Shifting the test pattern into the
STUMPS channels requires 7*P for shifting P
patterns.
(iv) Response capture: IP has 16 bit width data bus.
Unloading of 128 bit MISR (signature) register at
the end of each window (slot) hence takes 8 (128 /
16) cycles. The MISR shift out is done only once per
window to reduce the MISR storage memory and
also to optimize on test time. This results in a
detection latency of 4s in the worst case.
Based on these cycle count numbers, the general
equation to determine the number of patterns that can be
applied for each of the five schemes in Tables 1 and 2
can be given as:
21 (context save / re-load cycles) + 22*S (seed loading
cycles) + 7*P (scan shift cycles) + 8 (MISR unload
cycles) =520
where S is the number of seeds per window and P is the
number of patterns that can be applied in a given
window. For parallel loading of new seed and pattern
scan shift, only one from the terms (ii) and (iii) of the for 85% coverage requires 150 seeds, and then using
above equation, whichever is greater, is applicable. Scheme B for 95% coverage requires another 2267
(Refer to methods D and E discussed below). seeds, resulting in a total of 2417 seeds. On the other
hand,3584 seeds are required with Scheme B standalone.
Five different schemes are possible with tradeoffs in seed
Table 1: Pattern and seed computation for different
storage memory, test time and coverage: techniques.
A. Load one seed per window and generate as many Number of cycles
Schemes P S
patterns as possible per window. Seed loading into (i) (ii) (iii) (iv)
shadow register and pattern shifting into the DUT A 3*7 22*S 7*P 8 67 1
are done serially. This is a simple implementation B 3*7 22*S 7*P(=S) 8 16 16
C 3*7 22*S 7*P(=2S) 8 26 13
for steadily improving coverage. D 3*7 22*S NA (P=S) 8 22 22
B. Load a new seed for every pattern. Seed loading and E 3*7 22*S NA(P=2S) 8 44 22
pattern shifting are done serially. This Table 2: Tradeoffs with different techniques.
implementation gives fast coverage. Memory Time
Schemes Coverage Seeds Windows
C. Load a new seed for every two patterns. Seed (Kbits) (ms)
loading and pattern shifting are done serially. The 75% 16 16 6.16 0.84
results of this implementation are between (A) and 80% 46 46 17.71 2.36
A
90% 555 555 213.67 20.84
(B) above. 95% 1782 1782 686.07 71
D. Parallel (Concurrent) loading of new seed and scan 75% 192 12 50.88 0.48
shift. Load a new seed for every pattern. 80% 352 22 93.28 0.88
B
E. Parallel (Concurrent) loading of new seed and scan 90% 1440 90 381.6 3.6
shift. Load a new seed for every two patterns. 95% 3584 224 949.76 8.96
75% 131 11 35.08 0.44
For these five schemes, Table 1 lists the number of C
80% 242 19 64.63 0.76
patterns (P) which can be applied and number of seeds 90% 1044 81 278.676 3.24
(S) required per window. The number of cycles required 95% 3046 235 812.9 9.4
75% 192 9 50.5 0.36
for each of the four steps described above is also shown. 80% 352 16 92.51 0.64
Table 2 lists the overall number of patterns and seeds D
90% 1440 66 378.53 2.64
required for obtaining a given coverage, and the 95% 3584 163 941.95 6.52
associated test time and seed storage memory 75% 131 6 34.44 0.24
requirements. The number of windows denotes the 80% 242 11 63.6 0.44
E
90% 1044 48 274.45 1.92
number of test slots required for self-test during the 95% 3046 139 800.61 5.56
application execution. The memory required includes the
seed and result (MISR) storage and excludes the context Using some of the novel techniques discussed in the next
save memory of 3500 bits (this is a constant, irrespective section, the overhead of seed storage using the additional
of the scheme selected). on-chip memory can be further alleviated.
As an example, for Scheme B, a new seed is loaded for 5 Handling Seed Generation and Loading
every pattern. As shown in Table 2, 192 seeds are
The seeds for logic BIST self-test can come from the
required to reach 75% coverage. Since the seeds per
following sources:
window is 16 it will take 12 (192 / 16) windows of
On-chip memory (RAM): The ATPG tool generated
application to reach this coverage. The total test time is
0.48ms (12 windows * 40s). The total memory required seeds can be stored in the on-chip memory. These
is 49.344 Kbits (257 bits per seed * 192 seeds + 128 bit seeds are loaded into the BIST engine during self-
MISR * 12 windows). test execution. As seen in Table 2, this requires
additional memory for test purposes.
The results in the Table 2 highlight the various tradeoffs Through application firmware: Instead of storing
that can be exploited to meet the requirements of seeds on chip, they can also be provided externally
coverage, test time and storage memory. For example, a through application firmware. Only the seeds to be
given coverage can be obtained with lower (higher) test used in a given window of execution must be
time with more (fewer) seeds. The overhead in terms of downloaded in a cache (RAM).
test time and seed memory can be suitably controlled to On-chip generator: This is described in Sec. 5.1.
obtain higher coverage. Combinations of the schemes
can also be used based on coverage needs and memory 5.1 On-chip Seed Generation Techniques
available on chip. A better scheme could be to use On-chip seed generation techniques can be used to attain
combinations of Scheme A for achieving a certain the desired coverage [12,13]. A small sub-set of seeds
coverage, followed by Scheme B, to save seed memory are stored on-chip and the rest of the seeds are derived by
requirements. Experiments show that using Scheme A various seed manipulation techniques.

2009 15th IEEE International On-Line Testing Symposium (IOLTS 2009) 241
 Combinational operations: These include arithmetic
and logic operations like bit inversion, pair-wise and
group-wise bit rotation, or Boolean operations on
pairs and groups of bits, (e.g. XORing groups of
adjacent bits).
Counter approach: A counter is initially loaded with
a stored seed. Once the counter runs for few cycles,
the new counter state can be used as another seed. A
large seed (e.g. 257 bits) can also be split into
smaller sets (e.g. 8 bits each), such that each set of
registers can be operated as counters independently.
LFSR approach: An additional LFSR can be used to
generate new seeds based on another seed. This is
the classical logic BIST technique.
In this work, various combinations of the above
techniques have been considered, and their effectiveness
in terms of coverage improvements, test time
requirements, and reduction in the number of external
seeds required is ascertained. With every one seed taken
from ATPG tool, nine new seeds are generated using
these approaches. The results are shown in Table 3. The
second column gives the coverage results with the tool
generated seeds, whereas the other columns give the
coverage taking these seeds as well as internal
derivatives of these seeds using above techniques. These
results are obtained using stuck-at fault model.
As can be seen from Table 3, using a counter approach,
82%-83% coverage can be obtained with just 40 seeds,
as against 100 seeds required in the ATPG process. The
graph in Fig. 6 shows how much improvement in
coverage can be obtained for a given memory size, using
on-chip seed generation techniques.
Table 3: Coverage results with on-chip seed generation
techniques.
ATPG Coverage
tool ATPG
Combinational Counter
generated tool
operations Approach
seeds results
10 71.33% 79.25%
20 74.79% 80.95%
30 76.62% 81.93%
100 82.80% 85.65%
87%
85%
83%
Coverage
combinational operations, nine simple logic operations
are chosen to be performed on the initial stored seeds.
This requires only ~700 2-input equivalent NAND gates.
The equivalent memory overhead to store the number of
seeds will be much larger.
The above techniques can help to reduce the number of
seeds required to be stored on-chip to obtain coverage
upto a certain number. However, for coverage in excess
of 87%-90%, deterministic seeds generated from the
ATPG tool may be required to be stored.
6 Conclusion
This paper reviews the design implementation techniques
and tradeoffs incurred in implementing field test using
traditional logic BIST self-test techniques. Different
schemes for self-test for coverage improvement, test time
reduction and test data storage reduction are considered.
Experimental results are presented for an IP core in
which such support is being incorporated. The
advantages and limitations of different schemes are also
highlighted. The paper suggests a framework together
with recommendations on how logic BIST self-test can
be extended to support field test. Future work in this area
includes optimizations in test data volume and additional
on-chip seed generation techniques so as to reduce the
overall memory requirements as also the test time.
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242 2009 15th IEEE International On-Line Testing Symposium (IOLTS 2009)