Talk EDA

CAD for VLSI
Chittaranjan Mandal
Dept of Computer Sc & Engg

and
School of Information Technology
IIT Kharagpur
August 16, 2016
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Chittaranjan Mandal (IIT Kharagpur) CAD for VLSI August 16, 2016 1 / 565
Table of Parts I
Part I: VLSI CAD
Part II: High level synthesis
Part III: Equivalence checking
Part IV: Basic concepts in logic synthesis
Part V: Use of unateness in logic synthesis
Part VI: The Espresso logic synthesis tool OF

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Table of Parts II
Part VII: Multi-level logic synthesis
Part VIII: Partitioning
Part IX: Floorplanning
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Part I
VLSI CAD
1 Complexity notations
2 NP complete problems
3 CAD and VLSI
4 VLSI design choices
5 Iterative improvement search TE

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Complexity notations
Section outline
1 Complexity notations
Asymtotic upper bound
Other upper bounds
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Complexity notations Asymtotic upper bound
Definition (Big-O Notation)

T (n) 2 O (f (n)) if there exist positive constants k and n0 such that
jT (n)j k jf (n)j for all n > n0.
Now f (n) is an upper bound of T (n)
T (n) usually represents the running time of a procedure taking the
input size n as a paramenter
Running time will depend of the supplied inputs, but T (n) is
independent of any particular input
T (n) must refer to some statistical aspect of the running time
maximum or worst case, minimum or best case, average case,
weighted average, etc
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Asymtotic upper bound (contd.)
In general T (n) is a complicated function whose behaviour may

be hard to follow
f (n) is usually a simple enough function that tells us enough about
T (n); for relatively large values of n
n0 helps us ignore behaviour for relatively small values of n
O (1) < O (log n) < O (n) < O (n log n) < O (n2 ) < O (n3 ) <
O (2n ) < O (n!)
An algorithm with smaller complexity is normally preferable to one
with larger complexity
Tuning an algorithm without affecting its complexity is usually not
as good as finding an algorithm with better complexity
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be hard to follow
O (2n ) < O (n!)
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be hard to follow
O (2n ) < O (n!)
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Complexity notations Other upper bounds
Other upper bounds
Definition (Big-omega Notation)

A function T (n) 2
(f (n)) if there exist positive constants k and n0
such that jT (n)j k jf (n)j for all n > n0
Now f (n) is a lower bound of T (n)

Definition (Big-theta Notation)
A function T (n) 2 (f (n)) if T (n) 2 O (f (n)) and f (n) 2 O (T (n))
Now f (n) is a tight bound of T (n)
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NP complete problems
Section outline
2 NP complete problems
CNF satisfiability (SAT)
Nondeterministic algorithm
3-SAT and SAT
Polynomial time reducibility
NP completeness
A few reductions
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NP complete problems CNF satisfiability (SAT)
CNF satisfiability (SAT)

Consider Boolean formulas of the form
F = (vi ; _ vi ; _ : : : _ vi ; ) ^ (vi ; _ vi ; _ : : : _ vi ; ) ^ : : : ^ (vi ; _ vi ; _ : : : _ vi ; )

1 1 1 2 1 k1 2 1 2 2 2 k2 l 1 l 2 l kl
Example (CNF formula)
= (x _ y _ u _ v ) ^ (x _ z _ w _ v )
F
This formula is easily satisfied, x = 1 and z = 1 satisfies F
Aim is to determine truth assignments of the variables, if possible, to

make F true
Currently no method is known to determine such an assignment or
declare absence thereof in polynomial time in the number of variables
Easy to check (in poly time in n) whether a given assignment satisfies F
Straightforward to work out CNF satisfiability (SAT) in O (2n ) time
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NP complete problems Nondeterministic algorithm
Nondeterministic algorithm
In decision problems we aim to decide whether or not a statement is true
A nondeterminstic algorithm for a decision problem has two phases:
1 (nondeterministically) guessing values of decision variables (each
in O (1) time)
2 checking feasibility of the candidate solution
It terminates unsuccessfully iff there exists no set of choices leading to a
feasible solution
If the checking stage of a nondeterministic algorithm is of poly time in
the size of the input, this algorithm is called an NP (nondeterministic
polynomial) algorithm, the problem is said to be in the class NP
A deterministic interpretation of a non-deterministic algorithm can be
made by allowing sufficient (e.g. exponential) parallelism in computation
In optimisation problems we aim to find the solution with the best
possible score according to some scoring scheme can be either
maximization or minimization TE
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Can be recast as decision problems yog, km s kOflm^
NP complete problems Nondeterministic algorithm
SAT
Example (ND algorithm for SAT)
/ / n o n d e t e r m i n i s t i c guessing
f o r each d i s t i n c t Boolean v a r i a b l e i n F
f v a l : = choose ( 0 , 1 ) ;
i f val = 0 f
Assign f a l s e t o t h e Boolean v a r i a b l e ;
g else f
Assign t r u e t o t h e Boolean v a r i a b l e ;
g
g
/ / checking
E v a l u a t e F u s i n g t h e guessed t r u t h v a l u e s
Both parts take polynomial time, thus SAT is in NP

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NP complete problems 3-SAT and SAT
3-SAT and SAT

Definition (3-SAT)
The restriction of SAT so that each clause contains at most three literals is
call 3-SAT
From SAT to 3-SAT

Let C = v1 _ v2 _ v3 _ : : : _ vn , n > 3 be a clause of a SAT formula
Let
C0 = u (v3 _ : : : _ vn )
= (u ) (v3 _ : : : _ vn )) ^ ((v3 _ : : : _ vn ) ) u )
= (u _ (v3 _ : : : _ vn )) ^ (:(v3 _ : : : _ vn ) _ u ) [x ) y x _ y ]
= (u _ v3 _ : : : _ vn ) ^ ((v3 ^ : : : ^ v3 ) _ u )
= (u _ v3 _ : : : _ vn ) ^ (v3 _ u ) ^ : : : ^ (vn _ u )
It can be easily verified that C (v1 _ v2 _ u) ^ C 0
C can be transformed to a 3-SAT clause by repeated application of the TE
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above construction in poly time
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NP complete problems 3-SAT and SAT
3-SAT and SAT (contd.)
Given any SAT formula F , it is possible to construct a 3-SAT

formula F 0 ( F ) in poly time
A solution for the 3-SAT formula can be used to derive a solution
for the original SAT formula, also in poly time
We say that SAT is reducible to 3-SAT in poly time
It is clear that if we can solve 3-SAT in poly time, then we can also
solve SAT in poly time 3-SAT is at least as hard as SAT to solve
in poly time
It may by noted that the above reduction does not work to reduce
SAT to 2-SAT (which is solvable in poly time, i.e. 2-SAT2 P)
SAT solvers often take advantage of 2-SAT to solve SAT formulas
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NP complete problems Polynomial time reducibility
Polynomial time reducibility

A decision problem D is polynomial-time reducible to another decision
problem E (D P E) if an algorithm A1 can be given to do the
following:
given an instance d of D, it is possible to generate an instance e
of E in poly time
the solution for e can be used to construct a solution for d in poly
time such that e is true iff d is true
Such a reduction (D P E) shows that if E can be solved in
polynomial-time, then D can also be solved in polynomial time
NP and SAT
The Cook-Levin construction enables any problem in NP to be reduced
to SAT in poly time, using the nondeterministic polynomial algorithm for
that problem to construct a SAT formula TE
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1
that can be programmed into a Turing m/c
NP complete problems NP completeness
NP completeness
Let E be a problem in NP (E 2 NP)

By the (construction mechanism used in the) Cook-Levin theorem,
E P SAT
Also suppose there are E1 ; E2 ; : : : ; Ek 2 NP such that SAT P E1 ,
E1 P E2 , . . . , Ek P E, then fSAT; E1 ; : : : ; Ek ; E g form a set of
NP-complete problems
Note that this process starts with SAT, establishing that the
singleton set fSATg is a set of NP-complete problems
If any problem in this set can be solved in poly time, then all the
problems in this set can also be solved in poly time (as
polynomials are closed under addition and multiplication)
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NP complete problems A few reductions
A few reductions
SAT P 3-SAT P Vertex Cover

Vertex Cover P Clique
Vertex Cover P Set Cover
Vertex Cover P Subset Sum P Knapsack
Vertex Cover P Hamiltonian Cycle P TSP
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CAD and VLSI
Section outline
3 CAD and VLSI

Moores Law
Design flow
Books
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CAD and VLSI Moores Law
Moores Law
In 1965, Gordon Moore noted that the number of transistors on a chip

doubled every 18 to 24 months
Serious implications for VLSI chip design shows that problem sizes TE
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that need to be handled are increasing at an exponential pace (locally,
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not asymptotically)
CAD and VLSI Moores Law
Moores Law (contd.)
Models of circuits that need to be used are also becoming more

complex
Circuit simulation models have been evolving through bsim4
Deep submicron effects need to be taken into account for routing
In the early days only gate delays were important, now
interconnect delays dominate
Optimisation objectives of CAD algorithms keep changing, e.g.
contemporary architectural synthesis techniques should
synthesise so that wire lengths are minimised in the later stages
involving physical design; earlier techniques did not have to
consider this aspect
CAD techniques seriously lab behind developments in chip
manufacturing TE
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CAD and VLSI Design flow
RTL design flow
HDL
RTL Synthesis
netlist manual design/module generator
Library logic minimisation
netlist manual design/module generators
physical design
layout
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Physical design flow
read NL partitioning region ordering compation
floorplanning placement detailed routing output layout
routing regions global routing costs
costs
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Scope of VLSI CAD
Design of electronic systems and semiconductor components are completely

dependent on computer-aided design/electronic design automation tools
Revenues from varius sectors in the
year 2000 are as follows:
Electronic systems ($1 trillion)
depend on
Semiconductor industry ($160B)
depends on
EDA industry $3B
CAD/EDA software companies
have a significant presence in the
world software market
They are important and are there
Software services: $229.8B to stay TE
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CAD and VLSI Books
Books
Algorithms for VLSI Design Automation; Sabih H. Gerez; John Wiley &
Sons, (ISBN) 978-0-471-98489-4
High-level synthesis: introduction to chip and system design; D D Gajski,
N D Dutt, A C-H Wu, S Y-L Lin; Kluwer Academic Publishers, (ISBN)
978-0-7923-9194-4
An introduction to physical design; M. Sarrafzadeh, C.K. Wong;
McGrawHill, (ISBN) 978-0-0705-7194-5
Practical Problems in VLSI Physical Design Automation; Sung Kyu Lim;
Springer, (ISBN) 978-1-4020-6626-9
Logic Synthesis; Srinivas Devadas, Abhijit Ghosh; McGrawHill, (ISBN)
978-0-07016500-7
Chandan Karfa, Dipankar Sarkar, Chittaranjan Mandal, Verification and
Synthesis of Digital Circuits: High-level Synthesis and Equivalence
Checking; C Karfa, D Sarkar, C Mandal; LAMBERT Academic TE
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Publishing, (ISBN) 978-3-8383-9813-6
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VLSI design choices
Section outline
4 VLSI design choices

Design choices
Standard cell based design
Macro cells
Design flow
Evolution of design abstraction
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VLSI design choices Design choices
Design choices
In Full-custom design most of the components are individually

designed for best performance
highly expensive
used for designing analog components
used for designing new components for use with other design styles
Semi-custom is the main arena for advanced CAD tools TE
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VLSI design choices Design choices
Design choices
In Full-custom design most of the components are individually

designed for best performance
highly expensive
used for designing analog components
used for designing new components for use with other design styles
Semi-custom is the main arena for advanced CAD tools TE
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VLSI design choices Standard cell based design
Standard cell based design

Standard cells are components stored in the design library
Cells of a family have the same height by vary in width
Suitable for placing in rows side-by-side
Gaps between rows are channels used for interconnecting
terminals of the cells c.f. channel routing problem
Newer fab technologies permit over the cell routing
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VLSI design choices Macro cells
Macro cells
Hard macro
Precompiled component that can be instantiated in a
design
Detailed model of component available for simulation
at various levels
Layout-level details may not be supplied to protect IP
Tied to a particular fab, low flexibility
Firm macro
Netlist is supplied
Physical design done at site
More flexibility of layout, less IP protection
Soft macro
RTL design is supplied
Logic design done at site TE
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Most flexibility, least IP protection

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Macro cells
Hard macro
design
at various levels
Firm macro
Netlist is supplied
Soft macro
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Macro cells
Hard macro
design
at various levels
Firm macro
Netlist is supplied
Soft macro
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VLSI design choices Design flow
Design flow
HDL
RTL Synthesis
netlist manual design/module generator
Library logic minimisation
netlist manual design/module generators
physical design
layout
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VLSI design choices Design flow
Physical design flow
read NL init placement region ordering compation
floorplanning routing regions detailed routing output layout
global routing costs
costs
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Floor planning Routing Output
IND
Placement

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VLSI design choices Evolution of design abstraction
Evolution of design abstraction
Year Level Man months for

10M Transistors
1978 Transistor entry 62,500
1985 Schematic Entry 6,250
1992 RTL Synthesis 625
2000 Behavioural Synthesis 125
Domain specific 63
Quality of design by CAD tool is best for combinatorial designs and
become more variable at higher levels of abstractions
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Iterative improvement search
Section outline
5 Iterative improvement search

Hill-climbing
Randomized Hill-climbing
Simulated Annealing
Genetic Algorithm
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Iterative improvement search
Iterative Improvement
Consider a landscape of hills, hillocks, peaks, depressions and

abysses.
An abyss is a forbidden region.
We want to find the highest point.
By iterative improvement we mean to:
start at a random position (configuration)
repeatedly consider various moves
some moves may be invalid
restart if stuck
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Iterative improvement search Hill-climbing
Hill-climbing
Hill-climbing: Attempt to maximize Eval(X) by moving to the highest

configuration in our moveset. If theyre all lower, we are stuck at a
local optimum.
1. Let X := initial config

2. Let E := Eval(X )
3. Let N = moveset size(X )
4. For ( i := 0 ; i<N ; i := i+1)
Let Ei := Eval(move(X ,i))
5. If all Ei s are E, terminate, return X
6. Else let i = argmaxi Ei
7. X := move(X , i )
8. E := Ei
9. Goto 3 OF
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Iterative improvement search Randomized Hill-climbing
Randomized Hill-climbing

3. Let i = random move from the moveset
4. Let Ei := Eval(move(X ,i))
5. If E < Ei then
X := move(X ,i)
E := Ei
6. Goto 3 or quit if no improvement
What stopping criterion should be used?

Comparison with greedy hill-climbing?
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Iterative improvement search Simulated Annealing
Simulated Annealing

3. Let i = random move from the move-set
4. Let Ei := Eval(move(X ,i))
5. If E < Ei then
X := move(X , i); E := Ei
else
with some probability (e (E Ei )=Ti , Ti being the
decreasing temparature, Ti = Ti 1 , = 0:85 (say)),
accept the move even though things get worse
X := move(X , i); E := Ei
6. Goto 3 or quit if no improvement or
temperature is low enough
High temparature random walk

Low temparature stochastic hill climbing
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Iterative improvement search Genetic Algorithm
Genetic Algorithm
A set of bit-strings represent a pool of tentative solutions (generation)

Let the first generation consist of random bit-strings.
Produce a new generation from an old generation:
Let G be the current generation of N bit-strings.
P (call them b0 ; b1 ; : : : bN 1 ), define
For each bit-string
pi = Eval(bi ) / j Eval(bj )
Form G0 be the next generation as:
For k = 0 ; k < N =2 ; k = k+1
Choose two parents each with probability Prob(Parent = bi ) = pi
Randomly swap bits in the two parents to obtain two new bit-strings
For each bit in the new bit-string, randomly invert it with some low
probability
Add the two new bit-strings to G0
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Part II
High level synthesis
6 RTL v/s HLS
7 How HLS works
8 Scheduling in HLS
9 Force directed scheduling
10 Allocation and binding

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11 Structured architecture synthesis

RTL v/s HLS
Section outline
6 RTL v/s HLS

Designing using HDLs
Dataflow model
Prevelance of RTL
Relevance of HLS
Behavioural specification to RTL
RTL v/s HLS
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RTL v/s HLS Designing using HDLs
Designing using HDLs

Design capture is often done via hardware description languages
Common HDLs: Verilog, VHDL
Helpful for describing: structure, dataflow, behaviour
Structure indicates interconnection between components much
like wiring chips on a breadboard
dataflow indicates how signals within a system are defined in
terms of other signals primary inputs or internal signals
behavioural representation may indicate behaviour of system over
time as a state machine includes data processing in each time
step also called register transfer level (RTL) behaviour
RTL behaviour implies complete scheduling of operations over
time steps controller can be automatically synthesised from RTL
behaviour
another form of behavioural representation is just the input/output TE
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behaviour modern HDLs have provision for both

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RTL v/s HLS Dataflow model
Dataflow model
Dataflow model may be timed or untimed
Given times may be used for simulation
Example (SR latch without Example (SR latch with

timing) timing)
entity latch is entity latch is
port (s,r : in bit; port (s,r : in bit;
q,nq : out bit); q,nq : out bit);
end latch; end latch;
architecture dataflow architecture dataflow

of latch is of latch is
begin begin
q<=r nor nq; q<=r nor nq after 1ns;
nq<=s nor q; nq<=s nor q after 1ns; TE
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end dataflow; end dataflow;

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RTL v/s HLS Prevelance of RTL
Prevelance of RTL
Before advent of Verilog and VHDL, designer had to work out all
the details
Large part of the design is mechanical formation of data paths,
derivation of controller (just a finite state transducer)
Verilog and VHDL represented a major advance at the time of
introduction
Designer could now create the RTL design
Mechanical steps of data path formation and controller generation
could be done by the tool
Even at RTL design could be at varying levels of details FU
formation may or may not have been done
Accepted practice in design community now
But do we really think in RTL terms?
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RTL v/s HLS Relevance of HLS
Relevance of HLS
We think behaviourally more like C-programming

Operations in a behavioural specification are not scheduled
Only the input/output behaviour is captured
Design is at a relatively high level of abstraction
Many decisions yet to be taken to take this design to RTL
Decisions affect cost and optimality of design
Yard sticks: performance, hardware cost and power requirements
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RTL v/s HLS Behavioural specification to RTL
Behavioural specification to RTL

We consider the behaviour of a differential equation solver for
y 00 + 3xy 0 + 3y = 0
// reading data from port p1

read(p1, dx);
read(p2, x);
v4 := u * dx;
read(p1, y);
y := y + v4;
read(p2, u);
x := x + dx;
read(p3, a);
v11 := x < a;
while (x < a) loop
end loop;
v1 := u * dx;
// outputing data to port p1
v2 := 3 * x;
write(p1, x);
v3 := 3 * y;
write(p1, u);
v5 := v1 * v2;
write(p2, y);
v6 := dx * v3;
v7 := u - v5; TE
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u := v7 - v6;
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Sample datapath
storage elements: most variables get mapped into these

functional units: most operations get mapped into these
interconnect elements (buses and switches): for realising data transfers TE
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switches: to regulate interconnections over time

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Sample controller
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Sample controller (contd.)
Datapath elements being controlled are also shown

Controller is a Mealy machine to control the operation of the
datapath to realise the desired behaviour
The set of states (S) are all the control steps in the RTL
The intial state (s0 ) is the starting point in the RTL
Inputs for the state m/c () are status signals from the datapath
these mostly originate from condition tests in the given behaviour
e.g.: x < a
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Sample controller (contd.)
Outputs ( ) are control signals to control various parts of the

datapath
FU control: selection of operation of FU
storage control: controls reading and writing to storage
interconnect control: to control flow of data by turning switches on
and off
The output function ( ) generates the control signals to control the
various parts of the data path
The state transition function ( ) follows the control flow of the
scheduled behaviour
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RTL v/s HLS RTL v/s HLS
RTL v/s HLS
Behavioural specification is at a higher level of abstraction

Huge gap between behavioural level and RTL
Design of RTL manually is an error prone process
Hardware is still a clean slate
Large number of decisions to be taken
Decisions affect optimality of design wrt performance, cost and
power requirements
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How HLS works
Section outline
7 How HLS works

Steps in HLS
Sequencing of HLS steps
Resolution of dependencies
Intermediate representation
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How HLS works Steps in HLS
Steps in HLS
Preprocessing: Given textual behaviour is parsed and converted into

an intermediate form called the control dataflow graph
(CDFG) suitable for later steps
Code optimisation: Various optimisations may be applied to the
CDFG to improve the optimality of the design
Allocation: There is no datapath as yet; it is necessary to determine
the resources that will be needed for the design, such as:
FUs, registers and interconnects
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How HLS works Steps in HLS
Steps in HLS (contd.)
Scheduling: The high level behaviour is not scheduled, however, for

h/w realisation, scheduling is generally required; as a
result of scheduling, operations are partitioned into sets
which are executed simultaneously; also execution of
these sets is ordered in time
Binding: Determination of which high level operation is to be bound
to which physical unit: which operation to which FU,
which variable to which storage element, which transfer to
which buses
Datapath and controller generation: Final step, based on design
generated through the previous steps
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How HLS works Sequencing of HLS steps
Sequencing of HLS steps
Position of some of the steps are obvious the first step and last
step
Other steps have interdependencies
Scheduling requires knowledge of available resources
FU allocation requires knowledge of distribution of operations (in
time)
Storage allocation depends on dataflows across time steps
Interconnect allocation depends on dataflows between datapath
elements depends on scheduling and FU/storage
allocation/binding
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How HLS works Resolution of dependencies
Resolution of dependencies
HLS is guided by user supplied parameters related to

performance and cost
These may be used to estimate resources
E.g.: if the the number of time steps for scheduling is given, then a
resource estimate may be made to guide scheduling
Scheduling and allocation may be jointly optimised
computationally more expensive
User supplied may also be used for interconnect allocations
Such parameters should be easy to specify
Parameter values may be inconsistent user may have to workout
variations
Variations may also be explored automatically to generate a
design space
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How HLS works Intermediate representation
Intermediate representation
CDFG most common also called flow graph (FG)

Obtained via basic block (BB) decomposition of given behaviour
BB is straight line code with single entry and single exit may be to
multiple locations if conditional branch is involved
FG is a directed graph of BB nodes
Each BB node, in turn, may be represented as a data flow graph (DFG)
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Basic block and its DFG
Example (DFG of do-while block of diffeq example (rather that the while block))
v1 := u * dx; v2 := 3 * x;
v3 := 3 * y; v5 := v1 * v2;
v6 := dx * v3; v7 := u - v5;
u := v7 - v6;
v4 := u * dx; // v4=v1, redundant
y := y + v4;
x := x + dx;
v11 := x < a;
square nodes represent program variables

crossing BB boundaries
duplicate square nodes indicate earliest
consistent redefinition of program variables
each node in diagram defines a variable
v11 represents a status condition flag (on
updated x, for do-while rather than while) TE
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Flow graph of BBs (CDFG)

Example (Flow graph of BB for diffeq example)
Four basic blocks are derived from the given code; these are listed below; the flow graph
comprising these BBs is illustrated; BBs are in 3-address form; each basic block has a single
entry point and a single exit point; exits may be to one multiple locations
I5
read(p1, dx);
read(p2, x); B1 10
read(p1, y);
v1 := u * dx;
read(p2, u);
v2 := 3 * x;
read(p3, a);
v3 := 3 * y;
v5 := v1 * v2;
C1 v6 := dx * v3;
v7 := u - v5;
x < a ?;
u := v7 - v6;
BBs are in 3-address form; v4 := u * dx;
B2 3 each basic block has a single entry y := y + v4;
point and a single exit point; x := x + dx;
write(p1, x);
write(p1, u);
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Scheduling in HLS
Section outline
8 Scheduling in HLS
Types of scheduling algorithms
Considerations for scheduling for HLS
ASAP scheduling
ALAP scheduling
List scheduling
Simple LP formulation of ASAP scheduling
Complexity of scheduling
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Scheduling in HLS Types of scheduling algorithms
Types of scheduling algorithms

Unconstrained
As Soon As Possible (ASAP)
As Late As Possible (ALAP)
Resource Constrained
List scheduling
Time Constrained
Force Directed Scheduling (FDS)
Exact scheduling
Integer Linear Programming (ILP)
Stochastic programming oriented
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Simulated annealing based
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Scheduling in HLS Considerations for scheduling for HLS
Considerations for scheduling for HLS
Different BBs are generally scheduled independently

Simple operations can be scheduled in a single time step
More complex operations may require multiple time steps
multicycling
Pipelined operation units (e.g. pipelined multipliers) may be used
new set of data can be taken after completing a pipeline stage
delay (usually one clock cycle, but may be more) pipelining
Multiple operations having data dependencies may be scheduled
in a single time step, if it is sufficiently long operation chaining
Multicycling, pipelining and chaining can be used in various
combinations
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Scheduling in HLS ASAP scheduling
ASAP scheduling
Schedule operations at the earliest possible time

Operations not depending on any other operations are scheduled
first; time step in BB is advanced
Operations whose predecessors have completed are scheduled
next; time step in BB is advanced
Repeat procedure until all operations are scheduled
Forward breath first traversal may be used
ASAP schedule can be expensive in terms of resource
requirements
Usually used in conjunction with ALAP scheduling to compute
metrics rather than for creating a final schedule of operations
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Scheduling in HLS ALAP scheduling
ALAP scheduling
In ALAP scheduling operations are scheduled as late as possible

Operations on which no other operations depend are scheduled
last; time step in BB is retracted
Operations, all whose successors have been scheduled are
scheduled next; time step in BB is retracted
Repeat procedure until all operations are scheduled
Reverse breath first traversal may be used
Expensive in terms of resource requirements
Usually used in conjunction with ASAP scheduling to compute
metrics
Difference between ALAP and ASAP schedule times of an
operation is called its freedom
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Scheduling in HLS List scheduling
List scheduling
Operations that are ready to be scheduled are maintained in a list
hence list scheduling
A record of resources marked as busy or available is maintained
An operation is selected from the list if a resource for it is available
Ties between operations are resolved on the basis of metrics,
such as the freedom and number of successors
Scheduling goes on until all operations in the BB are scheduled
It is not enough to only look at FU resources
Storage requirements are also important, but much harder to
predict
Desirable to schedule operations to reduce storage requirements
also
List scheduling reduces to ASAP schedule, in the absence of TE
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resource constraints; it heuristically reduces scheduling time
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Scheduling in HLS Simple LP formulation of ASAP scheduling
Simple LP formulation of ASAP scheduling

Tj time to complete operation-j (integral)
sj starting control step of operation-j
ej ending control step of operation-j
8j (sj 1) start from control step-1, expands to one constraint per
operation
8j (ej = sj + Tj ) ending control step of operation-j
8(oi oj )(sj > ei ) ensure precedence constraints
Let there be a sink operation with index-l
Optimisation: minimise el , subject to above constraints, all variables
being integers
Note that above formulation is just an LP and leads to ASAP scheduling
and can be solved in polynomial time
NB: LP formulation but integer solution special class of LP problems TE
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Resource constraints can be handled with more complicated ILP models

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Scheduling in HLS Complexity of scheduling
Complexity of scheduling
Theorem
The problem of scheduling a set of chains corresponding to two different types of operations in
two FUs (one for each type of operation) given a deadline D is NP-complete.
Corollary
The problem of scheduling a single rooted binary tree of two operation types on two FUs, one of
each type, is NP-complete.
Theorem
Absolute approximation of scheduling DAGs is NP-hard for the problem of minimization of
schedule length.
Theorem
Absolute approximation of scheduling DAGs with multiple operation types, given a deadline, is
NP-hard for the problem of minimization of the number of FUs.
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Force directed scheduling
Section outline
9 Force directed scheduling

Outline of FDS
Force computation for FDS
Example of force computation
FDS for multiple BB designs
FDLS
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Force directed scheduling Outline of FDS
Outline of FDS
It a time constrained scheduling technique for heuristically

minimising resource requirement (in 1989)
Determine time frame of each operation from ASAP and ALAP
schedules to get operation freedoms
Probability of an operation being scheduled in any of its time
frame slots: freedom of1 operation
Operations can be partitioned into groups, e.g.
adder/subtractor/comparator or multiplier
Compute operation distribution graphs for each time step (t ) over
(o) of type O whose time frames include t:
operationsP
DGO (t ) = o Prob(o; t )
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Force directed scheduling Outline of FDS
FDS example
Example (FDS for diffeq example in four time steps)
ASAP schedule ALAP schedule
DG for +: ;< DG for TE

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Force directed scheduling Force computation for FDS
Force computation for FDS
DGs indicate level of concurrency in various time steps

Force computation designed to reflect net change in concurrency
Mechanical analogy: Force = constant displacement (Hookes
law)
constant = distribution of operations of a class
displacement = change in probability as a result of tentatively
scheduling an operation at a particular time step
Necessary to compute forces arising from
change of probability of operation under consideration (self forces)
change of probability of predecessor and successor operations
(predecessor/successor forces)
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Force directed scheduling Force computation for FDS
Force computation for FDS (contd.)
Lower value (preferably -ve) of force reflects lowering of

concurrency
Higher value value of force reflects increasing of concurrency
leading to greater resource requirements
Forces computed for all operations for all possible times where it
can be scheduled
Choice leading to lowest force is chosen
FDS works in polynomial time
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Force directed scheduling Example of force computation
Example of force computation
Example
Attempt to schedule multiplication (v6 ) preceeding last subtraction
in time step 2
self force in time step 2: (1 + 2 + 2 + 3)
1 1 1
(1 2)
1
= 1:167
self force in time step 3: ( 12 + 3)
1
(0 12 ) = :417
predecessor force in time step 1 (as its preceeding is now
constrained to this time step): (1 + 1 + 12 + 31 ) (1 12 ) = 1:417
predecessor force in time step 2:
(1 + 21 + 12 + 31 ) (0 12 ) = 1:617
Net force: 1
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Force directed scheduling FDS for multiple BB designs
FDS for multiple BB designs
Scheduling of operations of different BBs have a global effect on

resource requirement max of resources for each BB
DGs may be constructed for all BBs together for global picture
Effect of altering BB completion times can be evaluated (using
forces)
Predecessor/successor forces on other BBs is always zero,
thereby sensitivity is reduced
Joint scheduling of operations in some BBs may be considered,
but computationally more expensive
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Minimization of Bus Costs
FDS can be refined to consider additional cost factors

Number of buses number of concurrent data transfers
Number of buses = maximum transfers in any C-step
Create modified
PDG to include transfers: Transfer DG
Trans DG(i) = [Prob (op,i) Opn No InOuts]
Opn No InOuts combined distinct in/outputs for Op
Add Trans DG force to self force
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Minimization of Register Costs
Minimum registers required is given by the largest number of data

arcs crossing a C-step boundary
Create Storage Operations, at output of any operation that
transfers a value to a destination in a later C-step
Generate Storage DG for these operations
Length of storage operation depends on final schedule
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Minimization of Register Costs
Avg life = (ASAP life + MAX life + ALAP life)/3

Storage DG(i) = (avg life - overlap) / (MAX life - overlap), where
overlap overlap between ASAP and ALAP life spans
Add Storage DG force to self force
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Force directed scheduling FDLS
FDLS
Force-Directed List Scheduling utilizes the features of FDS and list

scheduling
FDLS is similar to list scheduling except using force is the priority
function, rather than mobility
Mobility metrics do not give a picture of resource usage as a result
of deferring operations
The set of operations to be scheduled now are based on least
force
Multiple rather than single decisions may be considered jointly for
force computation
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Allocation and binding
Section outline
10 Allocation and binding

Notion of allocation and binding
Illustration of allocation and binding
Formulation of allocation-binding
Conflict-Compatibility duality
Variable compatibility graph
Register allocation by left edge
A total HLS example
Register-interconnect optimisation
Algorithm for RIO
Illustration of RIO
ILP for resource constrained scheduling
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Allocation and binding Notion of allocation and binding
Notion of allocation and binding
Allocation means just making resources available; e.g. two

adders, one multiplier, two buses
Binding means mapping microoperations to available resources
Allocation and binding often happen together
Allocation usually requires resource estimation, e.g. via
distribution graphs (DGs)
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Allocation and binding Illustration of allocation and binding
Illustration of allocation and binding
Example (Binding decisions)
o1 ; o3 ) ADD1
o2 ; o4 ) ADD2
a ) r1
b; e; g ) r2
c; f ; h ) r3
d ) r4
ADD1 output ) r2
ADD2 output ) r3
Commutativity of Datapath derived after allocation
operations may be and binding
used to simplify
interconnections Scheduled operations
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Allocation and binding Formulation of allocation-binding
Formulation of allocation-binding
Consider the schedule to illustrate

Example (Conflict graph for allocation-binding
binding decisions
example)
Clearly o1 and o2 cannot be mapped
to the same adder o1 o2
Similarly o3 and o4 cannot be

mapped to the same adder
These are incompatible or are in
conflict, because they are scheduled
in the same time step o3 o4
Conflicts can be modeled as a graph

Nodes for items in conflict are
Two sets of colourings are shown:
connected by an edge
hf gf gi hf
o1 ; o3 ; o2 ; o4 and o1 ; o4 ; o2 ; o3gf gi
Some sets of operations may be
marked incompatible, such as
hf gf gi
The set o1 ; o3 ; o2 ; o4 leads to the
f g f g
; + , ; FP simple interconnections shown in the datapath
in the example
Grouping of compatible operations
done by graph colouring
hf gf gi
The other set o1 ; o4 ; o2 ; o3 would give
rise to a more complicated datapath TE
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Allocation and binding Conflict-Compatibility duality
Conflict-Compatibility duality
Conflict graph indicates nodes that cannot be combined
Aim is to form colour classes of vertices; no pair of vertices in a colour class are adjacent
Compatibility graph indicates nodes that can be combined
Aim is to form cliques of vertices; each pair of vertices in a clique are adjacent
One graph can be converted to the other by complementing the set of edges
Algorithm are given for colouring or for clique formation
Example (Conflict graph and corresponding compatibility graph)
o1 o2 o1 o2
o3 o4 o3 o4
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Allocation and binding Variable compatibility graph
Variable compatibility graph
Vertices of the graph correspond to variables

Example (Variable compatibility
Edge between variables if and only if they are not graph for example)
live at the same time
Graph can be constructed by manual inspection a b c d
(for toy examples)
Constructed automatically by live variable
analysis which is a dataflow analysis technique
Variable compatibility information for single DAG
e f
(without program variable updation) may be
represented as an interval graph each variable
live only for a contiguous interval of time
Optimal clique identification in interval graph
possible using left edge algorithm
In general case of multiple BBs and variable g h
updation, clique identification necessary in
compatibility graph Dark green edges indicate live intervals;
hf g f gf
groupings a , b; e; g ; c ; f ; h and g
Each BB (with variable updation) produces
circular interval graph can be used to guide fg
d are readily evident TE
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Allocation and binding Register allocation by left edge
Register allocation by left edge

Variable lifetime spans are sorted in increasing order of their start time
Leftmost lifetime is assigned to the first register
Next variable with start time beyond end time of previous value also placed in same register
Continued until no more variables can be packed into current register
Continued with new register until all variables have been mapped
Example
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Allocation and binding A total HLS example
A total HLS example

Example (HLS example)
Example of Scheduling and Allocation
Version 2, September 2000
Jaap Hofstede
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A total HLS example (contd.)

Example (HLS example (contd.))
#define m1
#define m2
#define m3
#define m4
main()
{ float t, i1, o1, d1=0.0, d2=0.0;
while (1) {
in(i1);
t = i1 + m3*d2 + m1*d1;
o1 = t + m4*d2 + m2*d1;
d2 = d1; d1 = t;
out(o1);
}
}
Specification in C
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Original dataflow graph 3 TE

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D1 D2
m1 m3 m2 m4
:=
C4 C3 C6 C5
I1
+ +
C1 C7
+
C2
+
C8
D2 D1 O1
ASAP (4)
4 TE
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D1 D2
m3

C3
m1 I1 m2 m4
+
C4 C1 C6 C5
:= + +
C2 C7
+
C8
D2 D1 O1
ALAP (4)
5 TE
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D1 D2
m3

C3
m1 I1
+
C4 C1
m2
+
C2
C6
m4
:= ??
C5
+
C7
+
C8
1 Adder, 1 multiplier (6)
D2 D1 O1 6 TE
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D1 D2
m3

C3
m1

C4
I1 m2
+
C1
C6
m4
:= +
C2 C5
+
C7
+ 1 Adder, 1 multiplier (6)

C8
C1, C2 moved down
D2 D1 O1 7 TE
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D1 N2 N1 D2
I1 m2
+
C1
C6
m4
:= +
C2 C5
m3
+
C7
C3
m1
+ 1 Adder, 1 multiplier (4)
C4 C8
loop pipeline
N1 D2 N2 D1 O1 8 TE
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D1 N2 N1 D2
I1 m2
+
C1
C6
V1 V2
m4
:= +
C2 C5
V3 V4 V5
m3
+
C7
C3
V6 V7
m1
+
C4 C8
V8 V9
9 Registers included
N1 D2 N2 D1 O1
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1 2 3 4
V1
V2
V3
V4
V5
V6
V7
V8
V9
Lifetimes of registers
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3:=
5 1+
4+
8 7+ 2 6
9+
Lifetime compatibility graph

(+ := is source of data)
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R4
R1 R2
3
5 1
R5
4
8 7 2 6
R6
9
R3
Clique partitioning
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I1I1 R3 m2 R5
R2 R1 m4 R4
R3 R1 m3 R4
R5 R2 m1 R5
Numbers
are time 1 2 3 4 1 2 3 4 1 2 3 4 1 2 3 4
steps
Corresponding
non-optimised
data path +
Numbers
are time 1,3 4 2 2 2,4 1,3
steps
R2 R6 R5 R4 R1 R3
R2 R5 R4 R1 R3 13
O1
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I1
R3 I1 m2 R5
R2 R1 m4 R4
R3 R1 m3 R4
R2 R5 m1 R5
1 2 3 4 1 2 3 4 1 2 3 4 1 2 3 4
Multiplexers
optimised by
commutative +
property
1,3 4 2 2 2,4 1,3
R2 R6 R5 R4 R1 R3
R2 R5 R4 R1 R3 14
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I1
R3 I1 m2 R5
R2 R1 m4 R4
m3
R5 m1
1,3 2,4 1 2,3 4 1 2 3 4 1,4 2,3
M1 M2 M3 M4
Size of
multiplexers
reduced +
1,3 4 2 2 2,4 1,3
R2 R6 R5 R4 R1 R3
R2 R5 R4 R1 R3 15
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Controller-1
All six registers have an enable input, ena
Rx.ena
M1 and M4 have 1 control input, s:
Mx.s
M2 and M3 have 2 control inputs, s1 and s0:
Mx.s1 and Mx.s0
Controller has four states:
State1, State2, State3, State4
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Controller-2
enable M1 M2 M3 M4
State R1 R2 R3 R4 R5 R6 s s1 s0 s1 s0 s
1 0 1 1 0 0 0 0 0 0 0 0 0
2 1 0 0 1 1 0 1 0 1 0 1 1
3 0 1 1 0 0 0 0 0 1 1 0 1
4 1 0 0 0 0 1 1 1 0 1 1 0
R1.ena = M1.s = M3.s0 = State2 + State4

R2.ena = R3.ena = State1 + State3
R4.ena = R5.ena = State2
R6.ena = M2.s1 = State4
M2.s0 = M4.s = State2 + State3
M3.s1 = State3 + State4
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Allocation and binding Register-interconnect optimisation
Initially each variable is trivially mapped to a single register
Subsequently, sets of variables are merged to reduce the number
of registers in the design
Each set of variables is a clique in the variable compatibility graph
With the merger of a pair of registers it becomes necessary to
update
the compatibility information of the variables
the interconnection information of the design
Let initial compatibility matrix be s0

After each merger let compatibility matrix be updated from sl to
sl +1 , (by fTS ) as follows:
assume that after merging ri and rj , the merged register is ri
sl +1 is obtained by deleting the j-th row and column from sl
element sil ;+k1 = 1 only if sil ;k = sjl ;k = 1; k < j or
sil ;k +1 = sjl ;k +1 = 1; k j
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Initially each variable is trivially mapped to a single register
Subsequently, sets of variables are merged to reduce the number
of registers in the design
Each set of variables is a clique in the variable compatibility graph
With the merger of a pair of registers it becomes necessary to
update
the compatibility information of the variables
the interconnection information of the design
Let initial compatibility matrix be s0

After each merger let compatibility matrix be updated from sl to
sl +1 , (by fTS ) as follows:
assume that after merging ri and rj , the merged register is ri
sl +1 is obtained by deleting the j-th row and column from sl
element sil ;+k1 = 1 only if sil ;k = sjl ;k = 1; k < j or
sil ;k +1 = sjl ;k +1 = 1; k j
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Register-interconnect optimisation (contd.)
Interconnect information is updated (by fTR ) as follows:

all the sources that were initially feeding to ri and rj now feed only to
ri
all the points that were receiving from rj now receive only from ri
fTR and fTS have to be used together on the current design and the
current compatibility matrix for each merger, which may be
considered as a move
Let fCR = w1 CR + w2 CM denote the sum of the register storage
cost and the interconnect cost (measured as the total cost of the
multiplexer channels) of the design
Generalisation to include FU formation is straight forward
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Allocation and binding Algorithm for RIO
Algorithm for RIO
Merging of two registers in general produces a saving in area

Algorithm must attempt to find register pairs that yield maximal
reduction in the interconnect cost
Simplistic approach could choose pairs that rapidly deplete the
edges in the compatibility graph
This will reduce chances of future mergings and generate a
design with too many registers
Balance between the two optimization criteria is necessary
Following definitions enable a concise presentation of the
algorithm.
Common vertex A vertex v is said to be common to vertices v1
and v2 if sv ;v1 = 1 and sv ;v2 = 1. Here s is the
compatibility matrix. TE
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Algorithm for RIO (contd.)
Deletable edge An edge (v ; v1 ) is said to be deletable on merging

v1 and v2 if sv ;v1 = 1 and sv ;v2 = 0. The function
de(v1 ; v2 ) returns the number of edges deletable on
merging v1 and v2 .
Clique factor Let Pi be the vertex pairs inSs having precisely i
common vertices. Let Qi = j ;j i Pj . The clique factor
2jQi j
associated with Qi is cf (Q ; i ) = .
(i + 2)(i + 1)
(n + 2)(n + 1)
In a clique of n + 2 vertices there are edges, and
2
every edge has n common vertices. Thus for the presence of a
n + 2 member clique a necessary condition is that cf (Q ; n) 1
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Algorithm for RIO (contd.)

The algorithm may now be outlined as follows.
procedure reg min
1. dR = dR0 /* initial interconnect information */
2. s = s0 /* the initial compatibility matrix */
3. while (d 6= 0) do
4. f Determine the maximum x and the corresponding
Q such that cf (Q ; x ) 1; in the absence of such an x,
let Q include all the compatible variable pairs in s.
5. Determine the member (v1 ; v2 ) of Q which
de(v1 ; v2 )
has the minimum value of
fCR (dR ) fCR (fTR (dR ; vi ; vj ))
6. dR = fTR (dR ; v1 ; v2 )
7. s = fTS (s; v1 ; v2 )
8. g
9. dRf = dR
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Allocation and binding Illustration of RIO
Illustration of RIO
Example
Consider the code sequence given below.
v3 = v1 + v2 v 12 = v 1
v5 = v3 v4
v6 = v3 + v5 v 7 = v 8=v 5
op = v 4 & v 7
Let the two FUs used for this design be h+, -, &i and h/i
Thus the operations +, - and and are realized on the same FU, while
/ is realized on the other FU
The final assignment is made to op which is an output port
The life times are as follows:
L means that the variable is live TE
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Illustration of RIO (contd.)

Example (contd.)
time step v1 v2 v3 v4 v5 v6 v7 v8
1 L L D L D D D L
2 D D L L D D D L
3 D D L D L D D L
4 D D D D D L L D
In the first iteration reg min finds the following variable pairs satisfying
the clique factor criterion for a four member clique: hv1 ; v3 i; hv1 ; v6 i;
hv1 ; v7 i; hv3 ; v6 i; hv3 ; v7 i; hv1 ; v5 i; hv5 ; v6 i; hv5 ; v7 i; hv2 ; v3 i; hv2 ; v6 i;
hv2 ; v7 i; hv2 ; v5 i; hv4 ; v5 i
Actually a four member clique cannot be formed, but this is obscured by
the large number of edges present
Among these edges hv1 ; v3 i has the maximum multiplexer saving and
one of the least deletable edge count and this edge is selected for TE
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merging
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Example (contd.)
The merged variable takes the name v1
In the second iteration the following edges are found satisfying the clique
factor for a four member clique: hv5 ; v6 i; hv5 ; v7 i; hv2 ; v3 i; hv2 ; v6 i;
hv2 ; v7 i; hv2 ; v5 i; hv4 ; v5 i:
Among these edges hv2 ; v5 i has the one of the maximum multiplexer
saving and one of the least deletable edge count.
Thus this edge is selected for merging
In the third iteration the following edges are found satisfying the clique
factor for a three member clique: hv1 ; v6 i; hv1 ; v7 i; hv2 ; v6 i; hv2 ; v7 i;
hv4 ; v6 i; hv4 ; v7 i TE
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Example (contd.)
We select edge hv1 ; v6 i which has the one of the maximum multiplexer
saving and one of the least deletable edge count.
Finally the edges hv2 ; v7 i; hv4 ; v7 i and hv8 ; v7 i satisfy the clique factor for
a two member clique
The edge hv2 ; v7 i is selected
The merged variable takes the name v2 .
The final groupings turn out to be hv1 ; v3 ; v6 i; hv2 ; v5 ; v7 i; hv4 i and hv8 i:
For this grouping four multiplexer channels are needed
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Allocation and binding ILP for resource constrained scheduling
ILP for resource constrained scheduling
I set of control steps

i 2I control step-i
J set of operations
j 2J operation-j 2J
F set of final operations
K index set of resource instances
k 2K resource unit-k 2K
R function R : J ! 2I , possible (contiguous) starting times for op-j
Cj K compatible units for op-j
D function D : J K ! I, delay of op-j on unit-k
xi ;j ;k 2 f0; 1g op-j started on compatible unit-k at control step-i
z2I
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the finishing time
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Allocation and binding ILP for resource constrained scheduling
ILP for resource constrained scheduling (contd.)

Start once on one unit 8j 2 J : Pi 2R(j ) k 2C xi j k = 1
; j
; ;
For each operation j, ensure that it can start exactly at one

time step i, i 2 R (j ) on one of the permissible operation
units k , k 2 Cj
Since 0=1 decision variables are involved, this constraint
ensures that exactly one of these variables is 1
Execute one operation within
P its period of latency 8j 2 J ; 8i 2 R (j ); 8k 2
Cj : xi ;j ;k + j 0 2J ;i 0 2R (j 0 );i i 0 <i +D(i ;j );k 2Cj 0 xi 0 ;j 0 ;k 1
Precedence constraintsP 8 j 2 J ; 8 i 2 R ( j ) ; 8 k 2 Cj :
xi ;j ;k + j 0 j ;i 0 2R (j 0 );i 0 <i +D(i ;j );k 0 2Cj 0 xi 0 ;j 0 ;k 0 1
Finishing time 8j 2 J ; 8k 2 Fj : z (i + D (j ; k ) 1) xi ;j ;k [N.B.
i + D (j ; k ) 1 is a constant]
Objective function minimize z, subject to above constraints
Main problem runtime exponential in number of independent decision TE
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Structured architecture synthesis
Section outline
11 Structured architecture synthesis

Why SA?
A-Block based datapaths
A-Block details
Scheduling decision for SA
Sample schedule
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Structured architecture synthesis Why SA?
Why SA?
Interconnect prediction is poor, so go for a datapath framework with
predictable interconnection structure
Sum of component costs may be reduced but the real interconnect cost
of real estate occupied by buses is mostly overlooked
Synthesis technique to synthesis datapath in one-go scope for greater
optimality
FUs are formed as the schedule progresses
Data transfers between A-blocks need to be scheduled using available
buses
Use stochastic optimisation, because too many decisions are involved
In this case genetic algorithm has been used details skipped
Inherit some scheduling decisions, use multiple heuristics for solution
completion and iterate several times
High level architectural parameters taken from user, details of design
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Structured architecture synthesis A-Block based datapaths
A-Block based datapaths
Global Buses
F. U. Local Memory
A-Block
Global Memory
Controller
F. U. Local Memory
A-Block
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Structured architecture synthesis A-Block details
A-Block details
global
buses
access width muxes

out
switches
demux
mux1
mux2
in registers
switches
ALU
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to controller
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Hardconnection
Structured architecture synthesis Scheduling decision for SA
Scheduling decision for SA
times of fetching
source operands *
source Ablock of operand *
source operands of operation

time of initiation of time steps
operation *
an operation
Ablock in which operation

is scheduled *
time frame of operation
...
Group of operations
to be scheduled in TE
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* marked entries correspond to design decisions related to the

scheduling of the operation that need to be taken.
Structured architecture synthesis Sample schedule
Sample schedule
Example (SA schedule for diffeq)

v0 = dx * u (0) v1 = 3 * x (1) x = x + dx (2)
v2 = v0 * v1 (3) v3 = 3 * y (4) x < a (5)
v4 = u - v2 (6) v5 = dx * v3 (7) v6 = u * dx (8)
u = v4 - v5 (9) y = y + v6 (10)
Time Bus transfer variable definition Schedule of operations

1 u(2 ! 0) h0, *i h1, *i
2 x(1 ! 2) j *j j *j h2, +i
3 1(1 ! 0) h3, *i h4, *i j 1j
4 2(2 ! 1) 2(2) ! x(1) j *j j *j
5 3(0 ! 2) h8, *i h7, *i h6, -i
6 7(1 ! 2) j *j j *j h5, <i
8(0 ! 1)
10(1) !
y(1) 9(2)
h10, +i h9, -i
7
! u(2)
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Part III
Equivalence checking
12 Finite state machine model
13 Determining equivalence of two finite automata
14 Finite state transducers
15 FSMD model
16 Computation paths
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17 Modeling of systems using FSMDs

Finite state machine model
Section outline
12 Finite state machine model

Finite automata
FA illustrated
Non-uniqueness of FA representation
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Finite state machine model Finite automata
Finite automata
A machine with a finite number of states is a finite state machine.

It is a loose term, instead a finite automaton or finite state transducer
should be used.
Finite state automaton is a mechanism to check whether a given
sequence of symbols is acceptable or not.
An finite automaton (FA) is characterised by:

a finite set of states, denoted by S
an initial state, denoted by s0
a set of symbols which can be given to the FA as inputs;
this is called the input alphabet of the FA, denoted by
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Finite state machine model Finite automata
Finite automata (contd.)
on receipt of an input, the FA makes a transition from the current state to

another state;
this transition mechanism is represented as the state transition function,
denoted by : S ! S
the transition to the next state depends on the input symbol and the
current state of the FA
a set of states of the FA (possibly empty), denoted by F are designated
as final/accepting states;
the FA is said to accept sequences of symbols that causes it to make
transitions, starting with the initial state and eventually move to any
final/accepting state;
the set of all such sequences of symbols is called the language
accepted by the FA
an FA formally characterised by the above five components is called a
finite automata and denoted by the quintuple: h; S ; s0 ; ; F i
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Finite state machine model FA illustrated
FA illustrated
Example (A FA to accept even 0s and odd 1s)

What is the quintuple
1 representation of this FA?
= f0; 1g
EE EO
1 S = fEE; EO; OE; OOg
s = EE
0 0 0 0 :S!S
0 1
1
EE OE EO
OE OO EO OO EE
1 OE EE OO
OO EO OE
F = fEOg TE
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Finite state machine model FA illustrated
FA illustrated
Example (A FA to accept even 0s and odd 1s)

What is the quintuple
1 representation of this FA?
= f0; 1g
EE EO
1 S = fEE; EO; OE; OOg
s = EE
0 0 0 0 :S!S
0 1
1
EE OE EO
OE OO EO OO EE
1 OE EE OO
OO EO OE
F = fEOg TE
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Finite state machine model Non-uniqueness of FA representation
FA representation is not unique

1
1
EO 0
1
EE EO EE
1 EO
1
0 0 0 0 0 0 0
0 0
1 1
OE OO OE OO
1 1
Both the m/cs accept the same language of strings over
= f0; 1g
In that sense the two FA are equivalent but not identical
FA optimisation results in another optimised by equivalent FA
Optimiser might have flaws FA equivalence is an important TE
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Determining equivalence of two finite automata
Section outline
13 Determining equivalence of two finite automata

Notion of equivalence of finite automata
Procedure for FA equivalence
Illustration of FA equivalence
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Determining equivalence of two finite automata Notion of equivalence of finite automata
Equivalence of finite automata
Definition
Two finite automata (FA) over are equivalent if they accept the same
set of strings over .
By corollary, when two FA are not equivalent, with both the FA starting
from the initial state, there must be a string w for which one of the two
FA reaches a final/accepting state, while the other FA does not.
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Determining equivalence of two finite automata Procedure for FA equivalence
Procedure for FA equivalence

Consider two FA M0 = ; S0 ; s00 ; 0 ; F0 and M1 = ; S1 ; s10 ; 1 ; F1
Construct a table with jj + 1 columns; each column is for pairs of
states for the form hp; q i, where p 2 S0 ; q 2 S1 ;
the last columns are associated with symbols in , one each
if a row has hp; q i in the first column, then the tuple hpa ; q a i is
formed so that pa = 0 (p; a) and q a = 1 (q ; a)
a1 ::: ajj
hp; q i hpa1 ; q a1 i : : : hpajj ; q ajj i
:::
for each tuple hp; q i in any of the last jj columns of any row, a
new row with hp; q i in the first column is introduced, if it not
already present
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Determining equivalence of two finite automata Procedure for FA equivalence
Procedure for FA equivalence (contd.)

construction of the table is started with the row for s00 ; s01
construction of the table terminates because there are at most
S0 S1 distinct tuples of states (and therefore rows in the table)
construction of the table is prematurely terminated if a tuple
hpa ; q a i is generated such that pa 2 F0 ^ q a 2= F1 or
pa 2= F0 ^ q a 2 F1
if construction terminates abruptly then M0 = M1, otherwise
M0 M1
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Determining equivalence of two finite automata Illustration of FA equivalence
Illustration of FA equivalence
Example
c c
p1 q1 c q4
c
d d d c
c
c
d d
d
p2 p3 q2 q3
c
M0 M1
c d M0 and M1 are not equivalent
hp1; q1i hp1; q1i hp2; q2i as p1 is a final state, while q3
hp2; q2i hp3; q4i hp1; q3i
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is a non-final state
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Finite state transducers
Section outline
14 Finite state transducers

Automata and transducers
Moore machine
Mealy machine
Equivalence of m/c classes
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Finite state transducers Automata and transducers
Automata and transducers
Starting at an initial state, a finite automata recognises a set of

strings by going to an accept state and rejects the complementary
set of strings by not going to the accept state
A finite state transducer generates outputs, using an output
function, on receipt of inputs; there is no designated final state
Let the output alphabet be
Two schemes of generating outputs:
Moore Output function depends only on the current state:
:S!
Mealy Output function depends only on the current state
and the present input: : S !
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Finite state transducers Moore machine
Moore machine
An Moore machine is characterised by:

the input alphabet, denoted by
the state transition function, denoted by : S ! S
the output alphabet, denoted by
the output function, denoted by : S !
h; ; S; s0; ; i
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Finite state transducers Mealy machine
Mealy machine
An Mealy machine is characterised by:

the input alphabet, denoted by
the state transition function, denoted by : S ! S
the output alphabet, denoted by
the output function, denoted by : S !
h; ; S; s0; ; i
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Finite state transducers Equivalence of m/c classes
Equivalence of m/c classes

All these three finite state m/c classes are ultimately equivalent:
Moore to Mealy Just associate the output of the state to the output on
receipt of any input
if Moore (s) = o, (8a 2 )Mealy (s; a) = o

1; s 2 F
FA to Moore = f0; 1g, (s) =
0; s 2=F
Mealy to FA Just treat the i/o pairs on the transitions as labels
= fhi ; oi j(9s 2 S ; 9i 2 ) (s; i ) = og
designate b 2 as the acceptance indicator
any state u reached by a transition output b is
duplicated to v so that all transitions to u having b as
output are sent to v and v is designated an accept
state; output transitions of v are same as u
F = fv j(9s; 9a 2 ) (s; a) = b; (s; a) = v g TE
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N.B. Finite state controllers are Mealy machines

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FSMD model
Section outline
15 FSMD model
Overview
FSMD model
FSMD model for GCD computation
Why use FSMDs
Why FSMD rather than FSM
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FSMD model Overview
Overview
Formal method for checking equivalence between two

descriptions of the target system, (before and after scheduling)
Based on equivalence checking of FSMDs (finite state machines
with data paths) to model hardware
(Roughly) Find cutpoints in one FSMD to break loops, Visualize
computations as concatenation of paths from cutpoints to
cutpoints Identify equivalent finite path segments in the other
FSMD
Repeat with the FSMDs interchanged
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FSMD model Overview
Scope of application
Basic block based scheduling.

Path-based scheduling where path segments are merged by the
scheduler. Most of the existing algorithms fail in this case.
Can handle many arithmetic transformations.
Supports simple code motions.
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FSMD model FSMD model
FSMD
An FSMD (finite state machine with data-path) is a universal

specification model, proposed by Gajski et al., which can
represent all hardware designs.
The model is used in the present work with the addition of a reset
state, for encoding the designs to be verified.
This reset state is also called the start state of the FSMD.
The FSMD is defined as an ordered tuple hQ ; q0 ; I ; V ; O ; f ; hi
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FSMD (contd.)
1 Q = fq0 ; q1 ; q2 ; : : : ; qn g is the finite set of control states,

2 q0 2 Q is the reset state,
3 I is the set of primary input signals,
4 V is the set of storage variables,
5 O is the set of primary output signals,
6 f : Q 2S ! Q, is the state transition function and
7 h : Q 2S ! U, is the update function of the output and the
storage variables, where S and U are as defined below.
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FSMD (contd.)
1 S = fL [ ER j L is the set of Boolean literals of the form b or :b,

b 2 B V is a Boolean variable
2 ER = fe R 0 j e 2 EA gg; it represents a set of status expressions
over I [ V , where
EA represents a set of arithmetic expressions over the set I [ V of
input and storage variables and R is any arithmetic relation.
3 R 2 f==; 6=; >; ; <; g.
4 U = fx ( e j x 2 O [ V and e 2 EA [ ER g represents a set of
storage or output assignments.
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FSMD (contd.)
Conjunction is assumed to be the implicit connective among the

relational expressions belonging to 2S .
Parallel edges between two states capture disjunction of status
expressions.
Thus, the next (control and data) state and the output depend not
only on the present state and the input signals but also on the
conjunction of the status expressions that indicate whether a
predicate holds on the data state of the storage and the input
variables.
An FSMD is inherently deterministic, that is, the state transition
function f satisfies the property sj = sk ) f (qi ; sj ) = f (qi ; sk ).
It may be noted that we have not introduced final states in the
FSMD model as we assume that a system works in an infinite OF
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FSMD model FSMD model for GCD computation
Behavioural description of GCD

begin
main_process: process
Input: P0; P1;
Output: yout;
Variable : res; y 1; y2 : integer;
begin
mainloop: loop
y 1 ( P0;
y 2 ( P1;
res ( 1;
while(!(y1 == y 2)) loop
if(even(y 1)) then
if(even(y 2)) then
begin
res ( res 2;
y 1 ( y 1=2;
y 2 ( y 2=2;
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end
Behavioural description of GCD (contd.)
else
y1 ( y 1=2;
else if(even(y 2)) then
y 2 ( y 2=2;
else if(y1 > y 2) then
y 1 ( y 1 y 2;
else
y 2 ( y 2 y 1;
end if;
end loop;
res ( res y 1;
yout ( res;
end loop mainloop;
end process main_process;
end behv; TE
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FSMD for GCD Example

q00
=y1 ( P00 ; y2 ( P10 ; res (1

y 1 == y2=res ( res y 1 q01
y1 > y2=y1 ( y1 y2
even(y2)= !(y1 == y2)=

res ( res 2
y1 (y1=2;
=OUT (yout ; res )
y2 (y2=2 even(y2)=
y2( y2=2
!even(y2)= q02 !y 1 > y2=
y1 ( y1 =2
!even(y1)=
y2 ( y2 y1
q04
q06
even(y1)=
!even(y2)=
q05
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q03
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FSMD for GCD Example (contd.)
Example (Equivalence of FSMDs for GCD)

The FSMD model M0 for the behavioural specification of GCD example
is given below and depicted in the figure.
M0 =hQ ; q0 ; I ; V ; O ; f ; hi, where
Q = fq00 ; q01 ; q02 ; q03 ; q04 ; q05 ; q06 g,
q0 = q00 ,
V = fres; y 1; y 2g,
I = fP00 ; P10 g,
O = fyout g,
U = fy1 ( P00 ; y2 ( P10 ; res ( res 2; y1 ( y 1=2; y2 (
y 2=2; y 1 ( y1 y2; y2 ( y2 y 1g,
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FSMD for GCD Example (contd.)

Example (Equivalence of FSMDs for GCD (contd.))
S = feven(y1); even(y 2); y 1 > y2g, where even(y) indicates
y mod 2 = 0,
f and h are defined as in the transition graph shown in the figure.
Some typical values of f and h are as follows:
f (q00 ; true) = q01 ,
f (q05 ; y1 > y2) = q02 ,
h(q05 ; y1 > y 2) = fy1 ( y 1 y 2g,
h(q03 ; even(y 2)) = fres ( res 2g.
A path, say , is indicated by the bold arrows in the figure.
q00 !
q01 !(y1==y2!) q02 !(even(y1!) q04 even(y2!) q01 .
Since there may be more than one transition from a state qi to a
state qj (with different conditions cl associated with them), a
sequence of states alone does not uniquely characterize a path. TE
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FSMD model Why FSMD rather than FSM
Why FSMD rather than FSM
The general equivalence problem of FSMDs (EPFSMD) is

undecidable and not even partially decidable
System implementations are ultimately finite, e.g. synthesised
hardware has finite datapath
Why not model finite systems as finite state machines
Their equivalence could be checked via FSM equivalence and
posed as the equivalence problem of FSM models (EPFSM)
EPFSM is decidable; BUT ...
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Why FSMD rather than FSM (contd.)
Inclusion of data states into the state space leads to the state
explosion
An n-bit datapath results in a number of states of the order 2kn ; a
data path usually has a good number of such registers
The benifit of having a tractable formulation is lost due to state
explosion
Important to keep data states out of state space representation
Even otherwise, FSM modeling may not be suitable for analysing
equivalence
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Why FSMD rather than FSM (contd.)
Operations may be scheduled in different steps, but end result

may be equivalent
This aspect is not captured via FSM modeling, be easily captured
via FSMD modeling
Hence look for tractable, though partial solutions using FSMDs...
Note that the a complete solution to EPFSMD is undecidable, but
an efficient partial solution may be possible
Partial solution will not handle all problem instances but handle a
sufficiently wide variety of useful cases
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Computation paths
Section outline
16 Computation paths
Notion of paths
Condition of execution of a path
Simple data transformation of a path
Computation of R and r
Illustration of path construction
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Computation paths Notion of paths
Notion relating to paths
Path from qm to qn
A finite transition sequence.
All intermediate qj are distinct, qn may be equal to
qm .
R Condition of execution of
Logical expression over variables.
If R is satisfied at the beginning of , then is
executed.
r Data transformation over
r = hS ; O i, where
S is transformation of variables
O is the output list along the path .
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Computation paths Notion of paths
Path from qi to qj
Definition
A (finite) path from qi to qj , where qi ; qj 2 Q, is a finite transition
sequence of states of the form hqi = q1 ! c1 q2 c2 : : : cn 1 qn = qj i such
! !
that 8l ; 1 l n 1; 9cl 2 2S such that f (ql ; cl ) = ql +1 , and qk ,
1 k n 1, are all distinct.
The end state of the path, i.e., qn , may be identical to any state qk ,
i k n 1, along the path.
A path does not cross itself, but may terminate on an intermediate
node.
The condition that needs to be satisfied for making a transition
from qi to qi +1 is ci
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Computation paths Condition of execution of a path
Condition of execution of a path (R )
Definition
Let = hql0 c0 ql1 c1 ql2 : : :
! ! ck
!1 qlk i be a path.
The condition of execution R of the path is a logical expression over
I [ V such that R is satisfied by the (initial) data state at ql0 iff the path
is traversed.
R is the weakest precondition of the path .
Example
The condition of execution R of the path of the FSMD figure is
!(P00 == P10 ) ^ !even(P00 ) ^ even(P00 )

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Computation paths Simple data transformation of a path
Simple data transformation of a path over V (s )
Definition
It is an ordered tuple hei i of algebraic expressions over the variables in
V and the inputs in I such that the expression ei represents the value
of the variable vi after the execution of the path in terms of the initial
data state (i.e., the values of the variables at the initial control state) of
the path
Example
The data transformation s of the path in the FSMD figure is
hP00; P10=2; 1i, where the order of the variables is y 1 y2 res.
This definition needs to be extened to capture outputs that are
generated to encompass the overall data transformation of a path. TE
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Computation paths Computation of R and r
Computation of R and r
Computation of the condition of execution R can be by backward

substitution or by forward substitution. The former is based on the
following rule:
If a predicate c (y ) is true after assignment y g (y ), then the
predicate c (g (y )) must have been true before the assignment.
The transformation s is found indirectly using the same principle.
The forward substitution method of finding R is based on
symbolic execution.
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Computation paths Computation of R and r
Computation of R by backward substitution
Example
q0 ?
After the assignment a a+5
/a a+5
suppose a > 18 is true in q1
What condition must be true in q0 ?
q1 a > 18
That can be computed as
(a + 5) > 18 ) a > 13
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Computation paths Illustration of path construction
Example of computation of R and r

[c3 (g2 (g1 (v ) ^ c2 (g1 (v )) ^ c1 ( v ) ;
qi [true; v ]
g3 (g2 (g1 (v )))]
forward substitution
c1 (v )=v ( g1 (v )
[c3 (g2 (v )) ^ c2 (v ); g3 (g2 (v ))] qi +1 [c1 (v ); g1 (v )]
backward substitution
c2 (v )=v ( g2 (v )
[c3 (v ); g3 (v )] qi +2 [c2 (g1 (v )) ^ c1 (v ); g2 (g1 (v ))]
c3 (v )=v ( g3 (v )
[true; v ] qi +3 [c3 (g2 (g1 (v ))) ^

c2 (g1 (v )) ^ c1 (v ); TE
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g3 (g2 (g1 (v )))]
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Chittaranjan Mandal (IIT Kharagpur)

of (R ; s ) at that point.
CAD for VLSI
The ordered pairs represent values August 16, 2016 156 / 565
Computation paths Illustration of path construction
Data transformation of a path over V (r )
Definition
It is the ordered pair hs ; O i, where s is the simple data
transformation of and the output list
O = [OUT (Pi1 ; e1 ); OUT (Pi2 ; e2 ); : : :]
For every expression e output to port P along the path , there is a

member of the form OUT (P ; e) in the list, in the order in which the
outputs occurred.
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Modeling of systems using FSMDs
Section outline
17 Modeling of systems using FSMDs

Computation in an FSMD
Capturing inputs
Path equivalence
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Modeling of systems using FSMDs Computation in an FSMD
Computation in an FSMD
A finite walk from the reset state back to itself without intermediate
occurrences of the reset state.
Computation can be represented as concatenation of paths. Two
computations c1 and c2 are equivalent if Rc1 = Rc2 ^ rc1 = rc2 .
Checking Rc1 = Rc2 ^ rc1 = rc2 could involve the whole of integer
arithmetic which is an undecidable problem (validity problem of
first order logic).
In this work, we use a syntactic approximation normal forms for
expressions
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Modeling of systems using FSMDs Capturing inputs
Capturing inputs
It is assumed that the inputs and the outputs occur through named
ports.
The i th input from port P is a value represented as Pi .
Thus, if some variable v stores an input from port P (for the i th
time along a path), it is equivalent to the assignment v ( Pi .
The variable y 1 in the GCD algorithm of the example is updated
by the 0th input from the port P0. This is shown as y 1 ( P00 in
the corresponding FSMD in the FSMD figure.
Similarly, the variable y2 stores the 0th input from the port P1 and
is shown accordingly as y 2 ( P10 in the FSMD in the FSMD
figure.
In essence, Pi s comprise the input variable set I. TECHNO
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Modeling of systems using FSMDs Path equivalence
Correctness problem
Equivalence of two FSMDs: For any computation c0 of M0, there

exists a computation c1 in M1 so that c0 = c1 and
vice-versa.
Problem with this scheme: There might be an infinite number of
computations in one FSMD. Finding all possible
computations in an FSMD is impossible.
Need: A finite representation of the infinite number of
computations.
Observation: Computation can be looked upon as a concatenation of
paths
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Modeling of systems using FSMDs Path equivalence
Correctness problem (contd.)
Finite Path Cover A set P = fp0 ; p1 ; p2 ; : : : ; pk g of FSMD M is said to

be a path cover of M iff any computation of M can be
viewed as a concatenation of paths from P.
Equivalence of two FSMDs For any computation c0 of M0 , there
exists an equivalent computation c1 in M1 and vice-versa.
In other words, there exists a finite path cover of M0 , such
that each path has a corresponding equivalent in M1 (with
consistency for corresponding endpoints), and vice-versa.
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FSMD equivalence
Section outline
18 FSMD equivalence
Basic equivalence checking method
Corresponding states
Equivalence of two FSMDs
Illustration of path equivalence
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FSMD equivalence Basic equivalence checking method
Basic equivalence checking method
The basic equivalence checking method: Let M0 and M1 be two

FSMDs.
1 Find the path cover, P0, in M0 .
2 For every path in P0, find an equivalent path in M1 .
3 Repeat step 1 and 2 with FSMDs interchanged.
Problem with finding Path Cover: Loops in FSMD.
Solution scheme: Based on Floyd-Hoares method of program
verification
1 Put cutpoints in FSMD s.t. each loop is cut at least
one cutpoint.
2 Set of paths from one cutpoint to other without having
any intermediate one is a path cover.
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FSMD equivalence Corresponding states
Corresponding states
Definition
Let M0 = hQ0 ; q00 ; I ; V0 ; O ; f0 ; h0 i and
M1 = hQ1 ; q10 ; I ; V1 ; O ; f1 ; h1 i be two FSMDs having identical input
and output sets, I and O, respectively, and q0i ; q0k 2 Q0 and
q1j ; q1l 2 Q1 .
The respective reset states q00 ; q10 are corresponding states.
If q0i 2 Q0 and q1j 2 Q1 are corresponding states and there exist
q0k 2 Q0 and q1l 2 Q1 such that, for some path from q0i to q0k in
M0 , there exists a path from q1j to q1l in M1 such that ' ,
then q0k and q1l are corresponding states.
Corresponding states help us to start from the reset state (also

corresponding states) and continue checking after paths starting from OF
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FSMD equivalence Equivalence of two FSMDs
Checking equivalence of M0 and M1

For machines M0 and M1 keep track of:
pairs of corresponding states (found so far)
matched pairs of paths (found so far)
unmatched paths to be processed
1 Identify initial cutpoints in M0 to break loops:

Reset state + states with more than one output transition
2 (Main loop)
Process an unmatched path from M0 (succeed when none left).
Use findEquivalent (, q) on M1 where q corresponds to start of
may find direct corresponding path in M1 , or
may require path to be extended (creating new cutpoints and new paths to match), or
may fail with no possible extension (exit with failure)
3 Identify initial cutpoints in M1 .
4 Repeat the same procedure as described in step 2 with roles of M0 and M1 interchanged.
5 If succeed for both step 2 and 4 then M0 and M1 are computationally equivalent, otherwise
report a failure. TE
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FSMD equivalence Illustration of path equivalence
Example for path equivalence
Example
(
q10
(
q00 / v1 3*x
( u * dx ( ( v6 u*dx
( 3*dx
(( (
- / v0 u*dx, v1 3*x, 1. v1
( u*dx
1. v0 q11
( 3*x v3 3*y, v6 u*dx,
( 2. v6
( u*dx
2. v1 x x+dx
( x+dx (
/ v0 u*dx
3. v0
( 3*y
3. x q01 v3 3*y
(3*y ( ( q12
(
4. v3
( v0*v1
4. v3 - / v2 v0*v1, v5 dx*v3
( u*dx ( (
/ v2 v0*v1 5. v2
( y+v6
5. v6 y y+v6
( v0*v1 q02 q13
y y+v6
6. y
( u-v2
6. v2
( dx * v3 ( u-v2 ((
7. v4
( dx*v3
7. v5 / v4 u-v2
( y+v6
-/v4
v5 dx*v3 8. v5
( x+dx
8. y
( u -v2
q03 q14
( v4-v5 / x ( x+dx 9. x
( v4 - v5
9. v4
10. u ( v4 -v5 q04
-/u
q15
u ( v4-v5 10. u
(a) Original (b) FSMD M0 (c) FSMD M1 (d) Scheduled
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Example for path equivalence (contd.)
Example
The FSMDs M0 and M1 are shown in parts (b) and (c) of the
figure, respectively.
It is clear from the figures that the order of the operations are
changed by the scheduler; for example, the operations
x ( x + dx is moved from the 3rd step to the 9th step.
Also, the scheduler introduces one state in the scheduled
behaviour; specifically, the FSMD M0 has five states whereas the
FSMD M1 has six states.
A new state is inserted in the scheduled behaviour due to
resource constraints.
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Equivalence checking example
Example
> = (
!(y 1 == y 2) & !even(y1)& !even(y 2)
&!y 1 y 2 y2 y2 y1
q00 q10
=OUT yout ; res =y 1 ( P0 ; y 2 ( P10 , =y 1 ( P0; y 2 ( P1; res ( 1 !(y 1 == y2) &
( y 2==2
!even(y 1)
res ( 1 0
( ) even(y 2)
y 2=res ( res y 1
y2
y1 > y2 =
y 2=res ( res yq1
y1
y 1 ( y1
==
y1 == y2 q11
01
=
!(y 1 == y 2) & even(y 1)
= ( res 2
&even(y 2)
(
even(y 2)
( y 1=2;
res
( =
( == ;
res res !(
2y1 == y 2) y1
y 2 ( y 2=2
( ==
y1 y1 2
y2 y2 2 even(y2)
y2 y2 2
even y 2 = q02
y 1 ( y 1=2
(>y 2y2= y 1
! ( ) q12
!y 1
!even(y 1) = y2
/
!(y1 ==
&!even(y 2) =y 1 ( y1=2
y 2) & even(y 1)
=yout ( res
q04
q06 even(y 1) = = > = (
!(y 1 == y 2) & !even(y 1)& !even(y 2)
!even(y 2)
q05 &y 1 y2 y1 y1 y2
q13
q03 (a) (b)
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Equivalence checking example (contd.)
Example
The initial set of cutpoints is fq00 ; q01 ; q02 ; q03 ; q04 ; q05 g.
The algorithm first finds q10 ! q11 as the equivalent path of
q00 ! q01 .
It next takes q01 (y1==y2!) q0e ! q00 and finds
q11 (y1==y2!) q12 ! q1e ! q10 as its equivalent path.
It next considers the path q01 !(y1==y2!) q02 and fails to find its
equivalent path (as this path has been merged with its successor
paths by the scheduler).
So, this path will be extended.
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Example
The extended paths are q01 !(y1==y2!) q02 even(y1!) q03 and
q01 !(y1==y2!) q02 !even(y1!) q04 .
The algorithm then considers the path
q01 !(y1==y2!) q02 even(y1!) q03 .
This path also needs to be extended and the extended paths are
q01 !(y1==y2!) q02 even(y1!) q03 even(y2!) q01 and
q01 !(y1==y2!) q02 even(y1!) q03 !even(y2!) q01 .
The algorithm finds the paths q11 !(y1==y2) ^ even(y 1) ^ even(y2!) q11
and q11 !(y1==y2) ^ even(y1) ^ !even(y2!) q11 as the respective
equivalent paths.
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Example
Similarly, the path q01 !(y1==y2!) q02 !even(y1!) q04 is also extended.
The extended paths are q01 !(y1==y2!) q02 !even(y1!) q04 even(y! q
2) 01
! ! !
and q01 !(y1==y2) q02 !even(y1) q04 !even(y2) q05 .
The equivalent path of q01 !(y1==y2!) q02 !even(y1!) q04 even(y2!) q01 is
q11 !(y1==y2) ^ !even(y1) ^ even(y2!) q11 .
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Example
The path q01 !(y 1==y2!) q02 !even(y1!) q04 !even(y2!) q05 will again be
extended and the extended paths are q01 !(y1==y2!) q02 !even(y1!) q04
!even(y2!) q05 y1>y2
! q01 and
q01 !(y1==y2!) q02 !even(y1!) q04 !even(y2!) q05 !(y1>y2!) q01 .
The paths q11 !(y1==y2) ^ !even(y1) ^ !even(y2) ^ (y1>y2!) q11 and
q11 !(y1==y2) ^ !even(y1) ^ !even(y2) ^ !(y1>y2!) q11 are found as the
respective equivalent paths by the algorithm.
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Equivalence of arithmetic expressions
Section outline
19 Equivalence of arithmetic expressions

Normalization of arithmetic expressions
Grammar of normalized sum
Simplifications
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Equivalence of arithmetic expressions Normalization of arithmetic expressions
Normalization of Arithmetic Expressions
A condition of execution (formula) of a path is a conjunction of

relational and Boolean literals.
A Boolean literal is a Boolean variable or its negation.
A relational literal is an arithmetic relation of the form s r 0; where
s is a normalized sum and r 2 f; ; =; 6=g:
The relation > (<) can be reduced to () over integers.
Negated relational literals are suitably modified to absorb the
negation.
Example
x y > 0 can be reduced to x y 1 >= 0.
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Equivalence of arithmetic expressions Normalization of arithmetic expressions
Normalization of arithmetic expressions (contd.)
The data transformation of a path is an ordered tuple hei i of

algebraic expressions such that the expression ei represents the
value of the variable vi after execution of the path in terms of the
initial data state.
So, each arithmetic expression in data transformation can be
represented in the normalized sum form.
A normalized sum is a sum of terms with at least one constant
term
Each term is a product of primaries with a non-zero constant
primary
Each primary is a storage variable, an input variable or of the form
abs(s); mod(s1 ; s2 ); exp(s1 ; s2 ) or div(s1 ; s2 ); where s; s1 ; and s2
are normalized sums. TE
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Equivalence of arithmetic expressions Grammar of normalized sum
Grammar of normalized sum
1 S ! S + T j cs , where cs is any integer.

2 T ! T P j ct , where ct is any integer.
3 P !
S " Ce j abs (S) j (S) mod (S) j S Cd j cm , where cm is
a symbolic constant.
4 Ce ! S " Ce j S
5 Cd ! S Cd j S.
Thus, the exponentiation and the (integer) division are depicted by infix
notation and all functions have arguments in the form of normalized
sums.
In addition to the above structure, any normalized sum is arranged by
lexicographic ordering of its constituent subexpressions from the
bottom-most level, i.e., from the level of simple primaries. TE
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Equivalence of arithmetic expressions Grammar of normalized sum
Example of normalisation
Example
The expression
(x + 3y + 7 0 ^ 4x 2 + 3yz + 2 6= 0 ^ x " y 0)
will have the normal form
[1 x + 3 y + 7 0] ^
[4 x x + 3 y z + 2 6= 0] ^
[(1 x + 0) " (1 y + 0) + 0 0]
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Equivalence of arithmetic expressions Simplifications
Simplifications for normalisation
Simplification at the arithmetic expression (normalized sum) level

Any expression involving only integer constants is immediately
evaluated
Example
(5 2) is evaluated to 2.
In an expression, common sub-expressions are collected together

Example
x 2 + 3x + 5z + 4x is reduced to x 2 + 7x + 5z.
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Simplifications for normalisation (contd.)
Simplifications at the relational expression (relational literal) level

Any relational expression built from constant arithmetic
expressions may be immediately evaluated to true or false.
Example
4 1 0 is evaluated to true.
Common constant factors are extracted from the normalized sum

and the relational expression is consequently simplified.
Example
3x 2 + 9xy + 6z + 7 0 is mapped to
x 2 + 3xy + 2z + 2 0, where b7 3c = 2 (on account of
integer arithmetic) TE
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Simplification at the formula level

Some (Boolean or relational) literals of the formula can be deleted
by the rule if (A ! B ) then (A ^ B A).
For this step of simplification, it becomes necessary to detect
implication among literals.
It is possible to detect whether a relational literal implies another
relational literal when they involve the same non-constant sums.
Let the literals be l1 : (s1 + c1 )R1 0 and l2 : (s2 + c2 )R2 0. If
s1 = s2 = s, then the table given next depicts the relationship
between the constants c1 and c2 depending upon R1 and R2 ,
which must be satisfied for l1 to imply l2 .
Removal of repetitions of literals in a formula is possible using this
rule as for any literal l1 , l1 ! l1 is always true. TE
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Simplification at the formula level (contd.)
Example
The literal a b has multiple occurrences in the formula
a b ^ c d ^ a b. So, this formula is simplified to
a b ^ c d.
During this phase of simplification it is also checked whether

l1 ! :l2 , whereupon l1 ^ l2 is reduced to false.
Example
The formula a b ^ c d ^ !(a b) is evaluated to false.
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Conditions on c1 and c2 for which

(s1 + c1 )R1 0 implies (s2 + c2 )R2 0
R2 !
= 6=
= c1 = c2 c2 c1 c1 6= c2 c2 c1
R1 c2 c1 c2 > c1
# 6= c1 = c2
c2 < c1 c2 c1
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Some more transformations for normalisation
It can be easily seen that some of the properties of ; ; = and

6= are accommodated in course of normalization and simplification
of formulas.
The symmetry property of f=; 6=g is taken care of by choosing the
normal form of relational literals as sfR g0 and by imposing
ordering on the constituent sub-expressions at all levels.
Example
Both x = y and y = x will be expressed either as x y = 0 or
y x = 0, consistently.
Similar is case for 6=.

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Some more transformations for normalisation

(contd.)
The reflexivity of f; =; g and the irreflexivity of f6=g are

accommodated by collecting the common sub-expressions in a
sum.
Example
x x changes to x x 0, whereupon the left-hand side reduces to
0 by collecting the common subexpressions x; accordingly, x x
reduces to true by normalization.
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Part IV
Basic concepts in logic synthesis
20 Boolean Functions
21 Methods for 2-L logic minimisation
22 Working with cube covers
23 Working with cofactors
24 Containment checking
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25 Incompletely specified functions

Logic Synthesis Flow (for 2-L)
FSM
FSM Synthesis
Logic
SOP logic minimisation
PLA AND-OR or NOR-NOR (2-level)
Physical design
Layout
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Boolean Functions
Section outline
20 Boolean Functions
Laws of BA and functions
Literals, formulae, cubes
SOP expressions
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Boolean Functions Laws of BA and functions
Laws of Boolean Algebra
The structure: h0; 1; +; i, where + OR, AND and subject to the
following:
Commutative, distributive in both operations
Identity elements: 0 for +, 1 for
= 1, a a = 0
Complement: a + a
Associativity: a + (b + c ) = (a + b) + c a(bc ) = (ab)c
Idempotence: a + a = a, a a = a
Absorption: a + ab = a, a (a + b) = a
b,
De Morgan: a + b = a a b = a + b
Involution: a = a
The operator is usually implicit
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Boolean Functions Laws of BA and functions
Boolean functions
f (x ) : B n ! B, where
B = f0; 1g ; x = (x1 ; x2 ; : : : ; xn )
x1 ; x2 ; : : : are variables
x1 ; x1 ; x2 ; x2 ; : : : are literals
each vertex of B n is mapped to 0 or 1
the ON-set of f is fx jf (x ) = 1g = f 1 = f 1 (1)
the OFF-set of f is fx jf (x ) = 0g = f 0 = f 1 (0)
if f 1 = B n , then f is a tautology, i.e. f 1

if =
f0 Bn, then f is not satisfiably, i.e. f 0
if f (x ) = g (x ), for all x 2 B n , then f and g are equivalent
f 1 is written as f
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Boolean Functions Literals, formulae, cubes
Literals
A literal is a variable or its negation: x or x

It is a logic function
Literal x1 represents the logic function f , where f = fx jx1 = 1g
Example
f (x ) = x1
The literal f (x ) = x1 in B 2 x2
x1
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Literals
A literal is a variable or its negation: x or x

It is a logic function
Literal x1 represents the logic function f , where f = fx jx1 = 1g
Example
f (x ) = x2
The literal f (x ) = x2 in B 2 x2
x1
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Boolean formulae
Boolean functions can be written as Boolean formulae using:

literals, operators + (OR), (AND) and (NOT), grouping using (
and )
Operators obey laws of Boolean algebra
Secondary operators, such as (XOR) can be defined in terms of
+, and
Sum of products: x1 :x2 + x1 :x2
Product of sums: (x1 + x2 ):(x1 + x2 )
Formulae interpretted by assigning values to variables
Several (countably infinite) formulae for same Boolean function
(how?)
n
22 distinct Boolean functions possible for n Boolean variables
(how?)
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Cubes
Cubes are conjunction of literals
Example
x2
The cube C = x2 in B3
x2 = 0, independent of: x1 ; x3
x3
x1
Let C be a cube
If C f , then C is an implicant of f
If C B n and C has k literals, then jC j has 2n k vertices
If k = n, then the cube is a minterm
Canonical SOP: each product term / cube is a minterm;
TECHNO
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Cubes
Example
x2
The cube C = x2 x3 in B3
x2 = 0; x3 = 1, independent of: x1
x3
x1
Let C be a cube
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Cubes
Example
x2
The cube C = x1 x2 x3 in B3
x1 = 0; x2 = 0; x3 = 1
x3
x1
Let C be a cube
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Cubes
Example
x2
The cube C = x1 x2 x3 in B3
x1 = 0; x2 = 0; x3 = 1
x3
x1
Let C be a cube
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Cubes
Example
x2
x3
x1
Let C be a cube
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Cubes
Example
x2
x3
x1
Let C be a cube
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Boolean Functions SOP expressions
SOPs as cube covers
SOPs can efficiently represent many logic functions

SOP for a given Boolean function may be redundant and
non-unique
Cube covers are equivalent to SOPs
Two-level minimization seeks the minimum size SOP (cover with
mininum number of cubes)
Example
x2
x1 x3
f (x ) = x1 x2 x3 + x1 x2 x3 + x1 x2 x3 + x1 x2 x3 x1 x2
= x2 x3 + x1 x2 + x1 x3 x2 x3 x1
x3
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Boolean Functions SOP expressions
Cover matrix representation of cubes
Example
F = x2 x3 + x1 x2 + x1 x3

is a cover of
f (x ) = x1 x2 x3 + x1 x2 x3 + x1 x2 x3 + x1 x2 x3

and may be represented as
x1 x2 x3 x1 x2 x3
x2 x3 0 0 x2 x3 2 0 0
or
x1 x2 1 0 x1 x2 1 0 2
x1 x3 1 1 x1 x3 1 2 1
Note: A row of dont cares (- or 2) makes the cover a tautology TE

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(always true)

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Methods for 2-L logic minimisation
Section outline
21 Methods for 2-L logic minimisation

Quine-McCluskeys technique
Boolean matrix for covering
Solving the cyclic core by Petricks method
Solving the cyclic core exactly
Solving the cyclic core heuristically
Performance of the heuristic (Optional)
Logic minimisation using cube covers
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Methods for 2-L logic minimisation Quine-McCluskeys technique
Quine-McCluskey exact method

Theorem (Quines Theorem1952)
A minimal SOP must always consist of a sum of prime implicants (PIs).
QM algorithm
Problem: Given a Boolean function f (may be incomplete), find a
minimum cost (number of literals) SOP formula.
Q-M Procedure:
1 Read in the minterms of f , fmi g or the given SOP
representation of f
2 Generate all the PIs of f , Pj
3 Build the Boolean matrix or Boolean constraint matrix
(BCM) B for covering, where Bij is 1 if mi 2 Pj and is 0
otherwise
4 Solve the minimum column covering problem for B find a TECHNO
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minimum set of prime implicants that cover all the
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minterms (unate covering problem)

Computing all PIs
Quines tabular method (traditional method)

Iterated consensus method
Recursive method
To be seen later
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Pitfalls of Quine-McCluskey Method
A function might have too many ( 2n ) minterms (although the

cover might be relatively smaller)
3n
The total number of prime implicants might be large ( )
n
The covering problem is known to be NP-hard
Size of the covering problem is also exponentially large
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Methods for 2-L logic minimisation Boolean matrix for covering
Covering by Boolean matrix for covering (BMC)

Example
f (w ; x ; y ; z ) = x 0 y 0 + wxy + x 0 yz 0 + wy 0 z
wxy wxz wyz 0 wy 0 z x 0 y 0 x 0z 0
wxyz X X
wxyz X
wxyz X X
wxyz X X
wxyz X X
wxyz X X
wxyz X
wxyz X X
wxyz X X
Essential column
Only column covering a minterm essential columns must be present in the TE
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Row dominance
Row ri (for minterm mi ) dominates row rj (for minterm mj ) if all the prime
that cover mi also cover mj (i.e. rj has all the 1-entries present in ri ).
Whenever a prime implicant Pi is chosen to cover the minterm mi ; the
minterm of rj is also covered.
Dominated rows can be dropped from the table.
Example
(2,6,10,14) (6,7,14,15) (8,10,12,14) (12,13,14,15)
2 X
6 X X
8 X
10 X X
12 X X
13 X
14 X X X X TE
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Column dominance
Column Pi dominates Pj if Pi has all the 1-entries present in Pj

(and possibly more)
Dominating columns cover all 1-entries (at no more cost) of the
columns then the dominated row
Dominated columns can be removed
Example
(2,6,10,14) (6,7,14,15) (8,10,12,14) (12,13,14,15)
2 X
8 X
13 X
15 X X
Column (12,13,14,15) dominates column (6,7,14,15)

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Cyclic core
Example
P1 P2 P3 P4 P5 P6
3 X X
5 X X
7 X X
9 X X
11 X X
13 X X
No scope for further reduction by dropping a essential column,
dominated row or dominated column.
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Methods for 2-L logic minimisation Solving the cyclic core by Petricks method
Petricks method
This is same as the well known NP-complete set cover problem

A (unate) Boolean expression p is formed which describes all
possible solutions of the table
For each prime implicant Pi , a Boolean variable pi is used which is
true whenever prime implicant pi is included in the solution
pi = 1(0) means Pi is (not) present in the cover
Example
For the cyclic core shown earlier, the required Boolean equation is:
p = (p1 + p2 )(p3 + p4 )(p1 + p3 )(p5 + p6 )(p2 + p5 )(p4 + p6 )

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Petricks method (contd.)
Expand the product of sum Boolean expression to a SOP

expression
Simplify using BA rules: X + X = X , X X = X , X + XY = X
Each product is a solution! expansion is exponentially expensive
Number of terms in each product indicates the number of prime
implicants that will be required total number of literals also
important
Each product is assigned a cost, select minimum cost product and
corresponding prime implicants
Example
The two products, p1 p4 p5 and p2 p3 p6 , describe two minimal solutions
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Petricks method (contd.)
Expand the product of sum Boolean expression to a SOP

expression
Simplify using BA rules: X + X = X , X X = X , X + XY = X
Each product is a solution! expansion is exponentially expensive
Number of terms in each product indicates the number of prime
implicants that will be required total number of literals also
important
Each product is assigned a cost, select minimum cost product and
corresponding prime implicants
Example
The two products, p1 p4 p5 and p2 p3 p6 , describe two minimal solutions
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Lower bound cost of covering a BMC
Independent rows
Two rows in a BMC are independent if the sets of columns (prime
implicants) covering them are disjoint.
Example
A BMC whose columns are rearranged with independent rows first.
1111
111111 0
1111
A C
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Lower bound cost of covering a BMC (contd.)
Theorem
The number of prime implicants in the cover of the BMC is at least as
large the number of independent rows in it.
Proof.
Let I = fI1 ; I2 ; : : : ; Ik g be the independent set of rows in B
Let Ci be the set of columns covering the row corresponding to Ii
Ci \ Cj = , if i 6= j
Hence, each of these rows must be covered by a distinct column,
leading to a minimum of jI j cubes for the cover
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Methods for 2-L logic minimisation Solving the cyclic core exactly
Solving the cyclic exactly by BB
hbound, coveri exactUC(B, X, b, Y) {

// B: Boolean matrix
// X: partial solution
// b,Y: best (trivial) UB cost, best soln so far
// first call: exactUC(B, X[00...0], |X|+1, -);
X X; lb reduceB(B, X); // lb: LB cost of B
// Reduce matrix B, derive lb and correspondingly update X
if (lb b) return hb, Xi; // bounding step
if (B has no rows) // termination, lb is a better UB
return hlb, Xi; // better soln found
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Methods for 2-L logic minimisation Solving the cyclic core exactly
Solving the cyclic exactly by BB (contd.)
c chooseCol(B); // Select a column c

B1 B; X1 X; X1[c] 1; // branch for keeping c
B1 delB1(B1, X1, c);
// deleting c and covered rows
hb1,X1i exactUC(B1, X1, b, Y);
if (b1 < b) // better soln found
b b1; Y X1;
B0 B; X0 X; X0[c] 0; // branch for dropping c
B0 delB0(B0, X0, c);
// deleting c only - not covered rows
hb0,X0i exactUC(B0, X0, b, Y);
if (b0 < b) // better soln found
b b0; Y X0;
return hb, Yi;
} TE
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Methods for 2-L logic minimisation Solving the cyclic core heuristically
Solving the cyclic core heuristically

// Let I = fI1 ; I2 ; : : : ; Ik g be the independent set of rows in B
heuristicBMC(B) {
I a new independent set of B // jI j may be 1
J
while (B is not empty) {
do {
choose S 2 colSet(Ii ) covering max rows of A
J J [ fS g
Drop all rows covered by column S
I = I n f Ii g
} while (jI j > 0)
if (B is empty) break // optimal solution has been found
I a new independent set of B // jI j may be 1
}
}
The cyclic core is same as the well known NP-complete set cover TE
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Methods for 2-L logic minimisation Performance of the heuristic (Optional)
Analysis of the approximate algorithm
Result
Given sets S1 ; S2 ; : : : ; Sn to cover the elements in X = [ni=1 Si = fx1 ; : : : ; xm g,
X
l
jJgreedy j H (r ) jJopt j; where H (l ) = 1=i and H (r ) = H ( max jSj j)
j =1;:::;n
i =1
Fact
ln(d + 1) H (d ) 1 + ln(d )
Reference
Chapter 2: The set covering problem in Lecture Notes on Approximation
Algorithms for Network Problems, J Cheriyan and R Ravi at
http://www.math.uwaterloo.ca/jcheriya/lecnotes.html TE
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Analysis of the approximate algorithm (contd.)
Let Ui be the set of uncovered rows (minterms) in iteration i of the

algorithm.
Let Si be the column (PI) chosen in iteration i of the algorithm.
For each x2 Si \ Ui (covered for the first time), let wgt(x ) = S \1U i i
Consider an arbitrary row S hx1 ; : : : ; xq i ; the elements

(minterms) ordered in the reverse order in which they are covered
(xq first and x1 last).
Therefore, wgt(xq ) wgt(xq : : : wgt(x1)
1)
Further, wgt(xl ) 1=l ; l 2 f1; 2; : : : ; q g ; since the number of newly
covered points when xl is covered is at least l, as the elements
fx1; : : : ; xl g in S are uncovered
P when xl is covered the first time.
For S = fx1 ; : : : ; xq g ; x 2S wgt(x ) = wgt(x1 ) + : : : + wgt(xq )
1 + 12 + : : : + q1 = H (q ) H (r ) TE
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Analysis of the approximate algorithm (contd.)
P
2 = jJgreedy j; noting that when Si is chosen in iteration i,
x X
8x 2 Si \ Ui ; wgt(x ) = jSi \1Ui j
Pn
Now consider the LP relaxation of the ILP: minimise j =1 sj , st
As 1m and sj 0; 8j 2 f1; : : : ; ng
Pm
j =1 yj , st yA 1
Also, consider the dual problem: maximise n
and yj 0; 8j 2 f1; : : : ; mg
wgt(xi )
yi = H (r ) is a feasible solution to the dual problem, as
P 1 P
2 yi = H (r ) xi 2S wgt(xi ) H (r ) H (r ) = 1
1
xi S
Pm 1 Pm jJgreedy j
j = 1 yj = H (r ) j =1 wgt(xj ) = H (r ) Jopt; as fy1; : : : ; ym g is
solution to the dual problem of the LP relaxation of the original IP
Thus, jJgreedy j H (r )Jopt TE
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Methods for 2-L logic minimisation Logic minimisation using cube covers
Outline of basic steps
Need to avoid minterm based canonical representation of f

Start with a cube cover representation of f
Work to obtain a minimum cover cover of minimum cardinality
Try to cover the minterms with bigger cubes
A cube can be expanded by dropping a literal
Should not cover a vertex in the OFF-set in the process
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Outline of basic steps
Need to avoid minterm based canonical representation of f

Start with a cube cover representation of f
Work to obtain a minimum cover cover of minimum cardinality
Try to cover the minterms with bigger cubes
A cube can be expanded by dropping a literal
Should not cover a vertex in the OFF-set in the process
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Example of heuristic minimisation using cube

covers
Example
Consider F (a; b; c ) = (f ; d ; r ); where
F1 (x ) = f (x ) = x1 x2 x3 + x1 x2 x3 + x1 x2 x3 + x1 x2 x3

d (x ) = x1 x2 x3 + x1 x2 x3
Cube x1 x2 x3 is not prime, so expand to x1 x2

F2 (x ) = x1 x2 x3 + x1 x2 x3 + x1 + x1 x2 x3
Make the cover irredundant dropping
x1 x2 x3 and x1 x2 x3 (in any order) x3
x1
F3 (x ) = x1 x2 x3 + x1
Cube x1 x2 x3 is not prime, expand to x2 x3
F4 (x ) = x2 x3 + x1
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covers
Example

d (x ) = x1 x2 x3 + x1 x2 x3

F2 (x ) = x1 x2 x3 + x1 x2 x3 + x1 + x1 x2 x3
x1
F3 (x ) = x1 x2 x3 + x1
F4 (x ) = x2 x3 + x1
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covers
Example

d (x ) = x1 x2 x3 + x1 x2 x3

F2 (x ) = x1 x2 x3 + x1 x2 x3 + x1 + x1 x2 x3
x1
F3 (x ) = x1 x2 x3 + x1
F4 (x ) = x2 x3 + x1
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covers
Example

d (x ) = x1 x2 x3 + x1 x2 x3

F2 (x ) = x1 x2 x3 + x1 x2 x3 + x1 + x1 x2 x3
x1
F3 (x ) = x1 x2 x3 + x1
F4 (x ) = x2 x3 + x1
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Working with cube covers
Section outline
22 Working with cube covers

Prime and irredundant cubes
Operations on cube covers
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Working with cube covers Prime and irredundant cubes
Prime and irredundant cubes, covers
Let F be a set of cubes covering f

A literal j of cube ci 2 F ( f ) is prime if

(F n fci g) [ ci0 6 f ;
where ci0 is the cube obtained by dropping literal j from ci a

prime literal cannot be dropped from the cube
A cube of F is prime cube if all its literals are prime
Pk
Let F = fc1 ; c2 ; : : : ck g be a cover for f : f = i = 1 ci
A cube ci 2 F is irredundant if F n fci g 6 f
A prime (cube) of f is essential (essential prime cube or essential
prime implicant) if there is a minterm in that prime cube or prime
implicant but in no other
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Working with cube covers Operations on cube covers
Operations on cube covers
Product (or intersection or logical AND) of cube covers

h = f g, h = fx jf (x ) = 1 ^ g (x ) = 1g
H = F G or H = F \ G
Sum (or union or logical OR) of cube covers
h = f + g, h = fx jf (x ) = 1 _ g (x ) = 1g
H = F + G or H = F [ G
Complementation of a cube cover
h = f , h = fx jf (x ) = 0g
H = F
interchange points which are present with those that are
absent
Difference of cube covers
H = F G or H = F \ G TE
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We need to obtain a suitable cube cover H, prefereably a compact one

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ORing of cube covers
// C, P, Q are lists of cubes

// compute pairwise AND between individual cubes
// add result to new list
OR(Q, P) {
C = ;
foreach q 2 Q { C = C [ q }
foreach q 2 P { C = C [ q }
return C;
}
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ANDing of cubes c and d as c \ d
q = c \ d is determined in the following steps

1 qi = ci , if di = ci or di is a dont care, otherwise
2 qi = di , if ci is a dont care, otherwise
3 6 di and neither is a dont care
q = , as in this case ci =
Operation is done in linear time in the number of input variables
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ANDing of cube covers
// C, P, Q are lists of cubes

// compute pairwise AND between individual cubes
// add result to new list
AND(Q, P) {
C = ;
foreach q 2 Q {
foreach p 2 P {
C = C [ (q \ p);
}
}
return C;
}
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Subtracting cube d from cube c: c d
// Assume that there are N variables

cubeDiff(c, d) { // result is a list of cubes in Q
if (c \ d = ) return Q fc g ;
Q ; q c;
for (i 0; i N; i++) {
if (qi = di or di = ) continue;
if (qi = ) {
pi di , pj qj if i 6= j
//
Q Q [ p // add p to Q
}
qi di
//
//
}
return Q; // c d TE
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}

Q ; q c;
for (i 0; i N; i++) {
if (qi = ) {
// note that p \ d =
}
qi di
//
//
}
return Q; // c d TE
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}

Q ; q c;
for (i 0; i N; i++) {
if (qi = ) {
// note that p \ d =
}
qi di
// ensures that all the cubes in Q are disjoint
// future cubes in Q will be from the other half
}
return Q; // c d TE
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}
Subtracting cube d from cube c: c d (contd.)
Example
Computing c d, where c = h i and d = h 11i
1 clearly, c \ d =
6
2 Q and q c (= h i)
3 nothing to do for the first two variables
4 p h 0 i, Q Q [ p, q3 1, q h 1 i
5 p h 10i, Q Q [ p, q4 1, q h 11i
6 Q = fh 0 i;h 10ig
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Example
1 clearly, c \ d =
6
2 Q and q c (= h i)
4 p h 0 i, Q Q [ p, q3 1, q h 1 i
5 p h 10i, Q Q [ p, q4 1, q h 11i
6 Q = fh 0 i;h 10ig
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Example
1 clearly, c \ d =
6
2 Q and q c (= h i)
4 p h 0 i, Q Q [ p, q3 1, q h 1 i
5 p h 10i, Q Q [ p, q4 1, q h 11i
6 Q = fh 0 i;h 10ig
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Disjoint SHARP of two cube covers
Given two cube covers C and D, C D = C \ D

SHARP(C, D) { // disjoint SHARP of SOP covers C and D

S C
foreach (d 2 D) {
R
foreach (c 2 S)
R R[c d
S R
}
return S // S is highly fragmented
}
Exercise
Compute fh 0 i;h 10ig fh 001ig
Answer: fh 10 i ; h 000i ; h 10ig TE
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S C
foreach (d 2 D) {
R
foreach (c 2 S)
R R[c d
S R
}
}
Exercise
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S C
foreach (d 2 D) {
R
foreach (c 2 S)
R R[c d
S R
}
}
Exercise
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Single cube containment (SCC)
SCC is used to do a cleanup after after performing logic

operations on covers
Cube c1 contains cube c2 if all literals of c1 are in c2
Just drop c2
Sort cubes in ascending order of the number of literals they have
so that bigger cubes preceed smaller cubes
While deciding whether to retain c2 in the cover, do a containment
check with cubes having lesser number of literals that are already
in the cover
Relatively easy to compute complexity ?
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Just drop c2
in the cover
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Just drop c2
in the cover
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Just drop c2
in the cover
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Single cube containment (SCC) (contd.)
Example
C = fx1 x2 x3 ; x1 x2 ; x2 x3 x4 ; x1 x2 x4 ; x1 x4 ; x1 x2 x3 x4 g

SCC(C ) = fx1 x2 x3 ; x1 x2 ; x2 x3 x4 ; x1 x4 g
A cover that is minimal wrt SCC is called an algebraic expression,

otherwise it is called a Boolean expression
The support of F , denoted as supp(F ) is the set of variables (not
literals) used in F
Two expressions F and G are called orthogonal if they have
disjoint supports (denoted as F ? G)
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Single cube containment (SCC) (contd.)
Example

SCC(C ) = fx1 x2 x3 ; x1 x2 ; x2 x3 x4 ; x1 x4 g
A cover that is minimal wrt SCC is called an algebraic expression,

otherwise it is called a Boolean expression
The support of F , denoted as supp(F ) is the set of variables (not
literals) used in F
Two expressions F and G are called orthogonal if they have
disjoint supports (denoted as F ? G)
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Working with cofactors
Section outline
23 Working with cofactors

Definition of cofactors
Shannon expansion
Cofactor of a cube
Cofactor wrt a cube
Cofactor of a cover
Cofactor from a cover matrix
Property of cofactors: xf = xfx
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Working with cofactors Definition of cofactors
Shannon (Boole) cofactors
fxi (x1 ; x2 ; : : : ; xn ) = f (x1 ; : : : ; xi 1 ; 1; xi +1 ; : : : ; xn )

The cofactor fl of f by a literal l is just f with a l = 1
If l xi , then l = 1 xi = 1
If l xi , then l = 1 xi = 1 xi = 0
The cofactor fl is, therefore, a conditional expansion of minterms
of f containing l, making fl independent of the variable
corresponding to l
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corresponding to l
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corresponding to l
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Why cofactors?
Cofactors play a central role in logic synthesis

Basis for a divide and conquer approach for handling problems in
logic synthesis
Recursive tautology checking
Recursive complementation
Used by way of tautology checking to determine
Irredundant cover
Prime literal
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Working with cofactors Shannon expansion
Shannon expansion
Shannon expansion of f around splitting variable x
f = xfx + x fx
Proof.
Consider a minterm m in the canonical SOP of f . It will have either
x or x in it as a literal
Partition the minterms of f into two sets (functions): f1 with all
minterms having x and f0 with all minterms having x , so that
f = f1 + f0
If m has x, then xm = m, x m 0, mx 0
If m has x , then x m = m, xm 0, mx 0
So xf0 0; x f1 0; f1 = xf1 = xf = xfx ; f0 = x f0 = x f = x fx
Hence, f = f1 + f0 = xfx + x fx TE
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Shannon expansion
f = xfx + x fx
Proof.
f = f1 + f0
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Shannon expansion
f = xfx + x fx
Proof.
f = f1 + f0
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Shannon expansion
f = xfx + x fx
Proof.
f = f1 + f0
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Shannon expansion
f = xfx + x fx
Proof.
f = f1 + f0
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Shannon expansion
f = xfx + x fx
Proof.
f = f1 + f0
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Shannon expansion of a cover

If F is a cover of f , then
F 0 = xj Fxj + xj Fxj
F 0 is a new cover of F obtained as F is expanded about xi , xi is called

the splitting variable
Example
Let F = x2 x3 + x1 x2 + x1 x3
F 0 = x2 Fx2 + x2 Fx2

= x2 (x1 x3 ) + x2 (x3 + x1 + x1 x3 )
= x1 x2 x3 + x2 x3 + x1 x2 + x1 x2 x3
Cube x1 x3 is split into x1 x2 x3 and x1 x2 x3 by x2 TE

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Working with cofactors Cofactor of a cube
Cofactor of a cube
The cofactor Cxj of a cube C with respect to a literal xj is Cxj =1 and is
obtained as:
C if xj and xj do not appear in C

C n xj if xj appears positively in C, i.e. as xj 2C
if xj appears negatively in C, i.e. xj 2C
Example
Let C = x2 x3
x2
Cx1 = C (x1 and x1 do not appear in C)
Cx2 = (x2 appears as x2 in C)
x3
Cx3 = x2 (x3 appears positively in C) x1
The cofactor of a cube with respect to a literal l has the effect of TE

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relaxing the cube with respect to l, if it was earlier restricted by l
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Cofactor of a cube
obtained as:

Example
Let C = x2 x3
x2
x3

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Cofactor of a cube
obtained as:

Example
Let C = x2 x3
x2
x3

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Working with cofactors Cofactor wrt a cube
Cofactor wrt a cube
Let c = xi1 xi2 : : : xix

The cofactor Cc of a cube C with respect to c is obtained as:
(Cx1 )(c nx1 )
Note that (Cx1 )(c nx1 ) = (C(c nx1 ) )x1
Example
Let C = x2 x3 and c = x1 x2
C1 = Cx1 = x2 x3
C2 = C1 x2 = x3
Cc = C2 = x3
TECHNO
OF LO
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Working with cofactors Cofactor of a cover
Cofactor of a cover
Cofactor of a cover F is the sum of cofactors of each cube of F

Cofactor wrt literal l of a cube c covering a minterm m
All literals in c will be present in m. The following two cases may occur
during the construction of the cofactors cl and ml , where l is any literal
Literal l is present in both c and m, then l will be absent in both cl
and ml and cl will cover ml
Literal l is absent in c, but present in m, in which case also l will
be absent in both cl and ml and cl will cover ml
Thus, if c covers m then cl covers ml
TECHNO
OF LO
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Working with cofactors Cofactor of a cover
Cofactor of a cover (contd.)
Example
+ cd Fb = ac + cd
F = abc + bd
Cubes which have b are dropped, b is dropped from cubes which have
b and other cubes are brought in unaltered
Fxj and fxj

If F =fc1 ; c2 ; : : : ; ck g is a cover of f , then
Fxj = (c1 )xj ; (c2 )xj ; : : : ; (ck )xj is a cover of fxj
Fc and fc
If F = fc1 ; c2 ; : : : ; ck g is a cover of f , then Fc = f(c1 )c ; (c2 )c ; : : : ; (ck )c g
is a cover of fc TE
OF
TECHNO
LO
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Working with cofactors Cofactor from a cover matrix
Cofactor determination from a cover matrix
While computing the cofactor wrt literal l corresponding to variable x,

each row according the the entry for x as follows:
Dont care (- for 2) then the row remains unchanged
0 indicating that x is present in the product, then change to
dont care (- for 2) if l = x , otherwise drop the row
1 indicating that x is present in the product, then change to
dont care (- for 2) if l = x, otherwise drop the row
TECHNO
OF LO
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Cofactor using a cover matrix (contd.)
Example
Let cube c = x1 x4 and let a Boolean function f (x1 ; x2 ; x3 ; x4 ) have a
cover F = x1 x2 x3 + x2 x4 + x1 x3 x4
x1 x2 x3 x4 x1 x2 x3 x4
x1 x2 x3
F = x2 x4
0

0
1
0

1
Fx1 = xx2 xx3

0
1
0

1
2 4
x3 x4 1 1 x3 x4 1 1
x1 x2 x3 x4
x2 x3
Fc = Fx x =
1 4
x2

0
1
0

x3 1
TECHNO
OF LO
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Example
cover F = x1 x2 x3 + x2 x4 + x1 x3 x4
x1 x2 x3 x4 x1 x2 x3 x4
x1 x2 x3
F = x2 x4
0

0
1
0

1
Fx1 = xx2 xx3

0
1
0

1
2 4
x3 x4 1 1 x3 x4 1 1
x1 x2 x3 x4
x2 x3
Fc = Fx x =
1 4
x2

0
1
0

x3 1
TECHNO
OF LO
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IND

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Example
cover F = x1 x2 x3 + x2 x4 + x1 x3 x4
x1 x2 x3 x4 x1 x2 x3 x4
x1 x2 x3
F = x2 x4
0

0
1
0

1
Fx1 = xx2 xx3

0
1
0

1
2 4
x3 x4 1 1 x3 x4 1 1
x1 x2 x3 x4
x2 x3
Fc = Fx x =
1 4
x2

0
1
0

x3 1
TECHNO
OF LO
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IND

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Working with cofactors Property of cofactors: xf = xfx
An important property of cofactors
Theorem
xf = xfx
Proof.
Consider any product p of the SOP f and the following cases
x occurs in p p occurs in xf ; pn fx g occurs in fx ; p occurs in xfx
x occurs in p xp = 0, so p does not occur in xf ; also p gets dropped
in fx and so does not influence xfx
Neither occurs in p xp occurs in xf ; p occurs in fx and so xp occurs
in xfx
TECHNO
OF LO
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Working with cofactors Property of cofactors: xf = xfx
Extending property for xfx = xf to CfC = Cf
xf x = xf
Let C = li1 li2 : : : lin 1 lin
CfC = li1 li2 : : : lin 1 lin fli l :::lin l

1 i2 1 in
= li1 li2 : : : lin 1 lin (fli1 li2 :::lin 1 )lin

= li1 li2 : : : lin 1 lin fli1 li2 :::lin 1
= lin li1 li2 : : : lin 1 fli1 li2 :::lin 1
= lin 1 lin li1 li2 : : : lin 2 fli1 li2 :::lin 2
:::
= li1 li2 : : : lin 1 lin f
= Cf TE
OF
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Containment checking
Section outline
24 Containment checking
Motivating example
Contaiment check via tautology checking
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Containment checking Motivating example
Cofactor of f wrt to a cube C
The cofactor fC of f by a cube C is f with variables indicated by the

literals of C, assigned values so that C = 1.
Example
If C = xi xj , then xi = 1, and xj = 0
Example
If C = x1 x4 x6 , fC is obtained by restricting f to the subspace where
x1 = x6 = 1 and x4 = 0
TECHNO
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Example
Example
x1 = x6 = 1 and x4 = 0
TECHNO
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Example
Example
x1 = x6 = 1 and x4 = 0
TECHNO
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Cofactor of F wrt to a member cube C

Example
F = x2 x3 + x1 x2 in B 3

C = x2 x3 , C 2F
The cube C = x2 x3 in B 3
Note that Fx2 ;x3 formed by dropping
literals of C, one by one, from cubes x2
of F
After dropping x2 from the cube x2 x3 x3
(C) of F : x3 x1
After dropping x3 from the cube x3
(C n fx2 g) of F : 1
Thus, Fx2 ;x3 1 (the cofactor FC ,
C 2 F is again a tautology in B 3 )
TECHNO
OF LO
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Example
F = x2 x3 + x1 x2 in B 3

C = x2 x3 , C 2F
of F
(C) of F : x3 x1
TECHNO
OF LO
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Example
F = x2 x3 + x1 x2 in B 3

C = x2 x3 , C 2F
of F
(C) of F : x3 x1
TECHNO
OF LO
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Example
F = x2 x3 + x1 x2 in B 3

C = x2 x3 , C 2F
of F
(C) of F : x3 x1
TECHNO
OF LO
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Example
F = x2 x3 + x1 x2 in B 3

C = x2 x3 , C 2F
of F
(C) of F : x3 x1
TECHNO
OF LO
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Example
F = x2 x3 + x1 x2 in B 3

C = x2 x3 , C 2F
of F
(C) of F : x3 x1
TECHNO
OF LO
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Cofactor of F wrt to a cube C F

Example
F = x1 x2 x3 + x1 x2 x3 + x1 x2 in B 3

C = x2 x3 , C F , but C is not a
member cube of F
Cubes x1 x2 x3 and x1 x2 x3 in B 3 x2
We shall track the development of
these two cubes during cofactoring
x3
After dropping x2 : x1 x3 and x1 x3 x1
After dropping x3 : x1 and x1
C 2 F is a tautology in B 3 )
TECHNO
OF LO
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Example
F = x1 x2 x3 + x1 x2 x3 + x1 x2 in B 3

member cube of F
x3
TECHNO
OF LO
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Example
F = x1 x2 x3 + x1 x2 x3 + x1 x2 in B 3

member cube of F
x3
TECHNO
OF LO
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Example
F = x1 x2 x3 + x1 x2 x3 + x1 x2 in B 3

member cube of F
x3
TECHNO
OF LO
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IND

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Example
F = x1 x2 x3 + x1 x2 x3 + x1 x2 in B 3

member cube of F
x3
TECHNO
OF LO
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IND

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Example
F = x1 x2 x3 + x1 x2 x3 + x1 x2 in B 3

member cube of F
x3
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OF LO
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Cofactor of F wrt to a C, C *F
Example
F = x2 x3 + x1 x2 in B 3 x2

C = x2 x3 , C *F
Fx2 = x3 + x1
x3
Fx2 x3 = x1 , not a tautology x1
Observation
Apparently, FC 1 if and only if C F
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Example
F = x2 x3 + x1 x2 in B 3 x2

C = x2 x3 , C *F
Fx2 = x3 + x1
x3
Observation
TECHNO
OF LO
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Example
F = x2 x3 + x1 x2 in B 3 x2

C = x2 x3 , C *F
Fx2 = x3 + x1
x3
Observation
TECHNO
OF LO
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Example
F = x2 x3 + x1 x2 in B 3 x2

C = x2 x3 , C *F
Fx2 = x3 + x1
x3
Observation
TECHNO
OF LO
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Containment checking Contaiment check via tautology checking
Valuation of fC at minterms in mC
Theorem
Let f be a Boolean function; C, a cube; m, a minterm and C 0 = mC
then (8 minterms m0 )(m0 2 C 0 ) fC (m0 ) = fC (m)).
Proof.
= C ; C 0 = and the claim is vacuously true
if m 2
n o
Let C = li1 li2 : : : lin 1 lin and let J = j : lij 2C
By definition, fC = f (li1 = 1; : : : ; lij = 1; : : : ; lijJ j = 1); lij 2J
Now, fC is independent of xij where xij = supp(lij ) j 2J
Now, m 2 C 0
8m0 2 C 0, mi = mi0, if mi 2= supp(C )
Hence, (8m0 )(m0 2 C 0 ) fC (m0 ) = fC (m))
TECHNO
OF LO
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Relationship between an implicant and the

cofactor wrt it
Theorem on cube as an implicant

Let C be a cube and f a Boolean function. Then
C f , fC 1
Observation
Note that xfx = xf and fx is independent of x
Proof. (If part)

Suppose fC 1, then Cf = CfC = C, thus C f
TECHNO
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cofactor wrt it

C f , fC 1
Observation
Proof. (If part)

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cofactor wrt it

C f , fC 1
Observation
Proof. (If part)

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Proof (contd.) (Only if part).

Next, assume C f , then C Cf = CfC [C is an implicant of CfC ]
Thus, C (x ) ) C (x )fC (x ) , C (x )fC (x ) = 0 ) C (x ) = 0
Let fC = 1, there must be a minterm m 2 B n , s.t. fC (m) = 0
Let C 0 = mC , thus m 2 C 0
Chose minterm m0 2 C 0 such that mi0 = mi , if xi 62 supp(C )
Therefore, m0 2 C, also m0 2 C , C (m0 ) = 1
Now fC (m0 ) = 0, as (8 minterms m0 )(m0 2 C 0 ) fC (m0 ) = fC (m)) and
fC (m) = 0
Hence C (m0 )fC (m0 ) = 0 although C (m0 ) = 1, thus contradicting C CfC
Hence the assumption that fC = 1 is not tenable and so fC 1
TECHNO
OF LO
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fC (m) = 0
TECHNO
OF LO
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fC (m) = 0
TECHNO
OF LO
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fC (m) = 0
TECHNO
OF LO
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fC (m) = 0
TECHNO
OF LO
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fC (m) = 0
TECHNO
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fC (m) = 0
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Importance of theorem
While expanding a cube to make it prime, it should not be

expanded into the OFF-set of the function
We now have a convenient way to check that a given cube is
indeed an implicant of the function represented by the cover the
expanded cube is contained within the original cover (alongwith
the DC-set)
We can also check whether a given cube of a cover is redundant
and can be dropped that cube is contained within the cube
removed from the original cover (alongwith the DC-set)
However, we need a way to perform tautology checking (after
computing the cofactor)
The containment checking method does not directly help us
determine the minimal irredundant cover TE
OF
TECHNO
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the DC-set)
OF
TECHNO
LO
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the DC-set)
OF
TECHNO
LO
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IND

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the DC-set)
OF
TECHNO
LO
GY
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IND

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the DC-set)
OF
TECHNO
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IND

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Incompletely specified functions
Section outline
25 Incompletely specified functions

Representation of ISF
Primes of ISF
Containment checking in ISF
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Incompletely specified functions Representation of ISF
Representation of incompletely specified

functions
) f0; 1; g where represents dont care

F = (f ; d ; r ) : B n
f : ON-set function - f (x ) = 1 $ F (x ) = 1
r : OFF-set function - r (x ) = 1 $ F (x ) = 0
d: DC-set function - d (x ) = 1 $ F (x ) = 0=1
Domains of (f ; d ; r ) form a partition of B n

D (f ) \ D (d ) = D (f ) \ D (r ) = D (d ) \ D (r ) =
A completely specified function g is a cover for F = (f ; d ; r ) if:
g is true whenever f is true, so f g
Whenever r is true g is false; r ) :g, so g ) :r , so g ) f + d, as
f ; d and r form a partition of B n , so g f + d
Thus, f g f + d, if g is a cover for F TE
OF
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functions

F = (f ; d ; r ) : B n

D (f ) \ D (d ) = D (f ) \ D (r ) = D (d ) \ D (r ) =
OF
TECHNO
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functions

F = (f ; d ; r ) : B n

D (f ) \ D (d ) = D (f ) \ D (r ) = D (d ) \ D (r ) =
OF
TECHNO
LO
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19 5 1
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functions

F = (f ; d ; r ) : B n

D (f ) \ D (d ) = D (f ) \ D (r ) = D (d ) \ D (r ) =
OF
TECHNO
LO
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functions

F = (f ; d ; r ) : B n

D (f ) \ D (d ) = D (f ) \ D (r ) = D (d ) \ D (r ) =
OF
TECHNO
LO
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IND

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functions

F = (f ; d ; r ) : B n

D (f ) \ D (d ) = D (f ) \ D (r ) = D (d ) \ D (r ) =
OF
TECHNO
LO
GY
ITU
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IND

19 5 1
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functions

F = (f ; d ; r ) : B n

D (f ) \ D (d ) = D (f ) \ D (r ) = D (d ) \ D (r ) =
OF
TECHNO
LO
GY
ITU
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IND

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functions

F = (f ; d ; r ) : B n

D (f ) \ D (d ) = D (f ) \ D (r ) = D (d ) \ D (r ) =
OF
TECHNO
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Incompletely specified functions Primes of ISF
Primes of incompletely specified functions
A cube C is prime of F = (f ; d ; r ) if it is a prime (implicant) of

f + d, so there is not other cube C 0 , such that C 0 ) f + d and
C C 0 (Note that C f + d $ Cr = )
Let G = fci g be a cover of F = (f ; d ; r ); let D be any cover for d;
let F f be any cover for f
A literal l2 ci is prime if (ci n fl g) = (ci )l is not an implicant of F
A cube ci is a prime of F iff all literals l 2 ci are prime
Literal l 2 ci is not prime , (ci )l f + d
(F f [ D )(c ) 1 (implies l not prime, by tautology check)
i l
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i l
TECHNO
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i l
TECHNO
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i l
TECHNO
OF LO
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i l
TECHNO
OF LO
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i l
TECHNO
OF LO
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i l
TECHNO
OF LO
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i l
TECHNO
OF LO
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i l
TECHNO
OF LO
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i l
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Incompletely specified functions Containment checking in ISF
Checking irredundant cube of a cover
Let G = fci g be a cover of F = (f ; d ; r ), let D be any cover for d

Let G0 = Gn cj , cube cj of cover G is redundant iff f G0 ;
otherwise, it is irredundant

Let Gj = Gn cj [ D = G0 [ D and suppose that f G0
Let m 2 cj , then m 2 f or m 2 d
if m 2 f , then m 2 G0 , as f G0 and so fmg Gj , as G0 Gj
If m 2 d then fmg D and so fmg Gj
Hence, cj Gj , as all its minterms are present in Gj
Thus, cj G is redundant iff cj Gj
(Gj )c 1 (implies cj is redundant by tautology check)
j
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j
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j
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j
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j
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j
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j
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Complexity of tautology checking
Section outline
26 Complexity of tautology checking

Complement of a decision problem
Counterexamples
co-NP problems
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Complexity of tautology checking Complement of a decision problem
co-NP problems
Tautology checking is a frequently occurring problem.

We consider its computation hardness.
Complement problem
The complement of a decision problem X is the decision problem X 0 if
for every problem instance p, answer for X (p) is yes if and only if
answer for X 0 (p) is no.
Example
Primality Is a given integer prime?
Compositeness Is a given integer compsite?
A given integer is prime if and only if it is not composite
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co-NP problems
Tautology checking is a frequently occurring problem.

We consider its computation hardness.
Complement problem
The complement of a decision problem X is the decision problem X 0 if
for every problem instance p, answer for X (p) is yes if and only if
answer for X 0 (p) is no.
Example
Primality Is a given integer prime?
Compositeness Is a given integer compsite?
A given integer is prime if and only if it is not composite
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Complementary problem of Tautology checking

Example
Tautology Is f (in DNF) true for all combinations of inputs?
Complementary problem Is f (in DNF) false for any combinations of
inputs?
Answer to original question is true if and only if answer to
complementary question is false.
CNF Is f (in CNF) true for any combination of inputs?
equivalent to the complementary problem
f (in DNF) is a tautology if and only if f (in CNF) is not
satisfiable
+ bc d
Tautology ? f = abc + abd
by DeMorgan f = abc abd
bc d
CNF ? f 0 = f = (a
+ b c)(a + b + d )(b + c + d )
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Complexity of tautology checking Counterexamples
Complementary problems and conterexamples
Example (Tautology)
A tautology is a propositional formula that is true under any
possible valuation of its propositional variables
Checking if f is true for all combinations of inputs is difficult
Counterexample, will indicate that f is not true for a combination of
inputs
Easy to verify counter example answer to CNF
Example (Primality)
Checking if p has a factor is difficult
Counterexample, will indicate that p has a factor
Easy to verify counter example answer to compositeness TE
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Complexity of tautology checking co-NP problems
co-NP problems
co-NP problem
A problem X is a member of co-NP if and only if its complement X is in
complexity class NP.
NP problem
A problem X is a member of NP if a solution to an instance of that
problem can be easily (in polytime) checked.
Such a positive solution is called a certificate for the problem instance.
Note that a certificate for the complementary problem instance is a

counterexample for the original problem instance.
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co-NP problems (contd.)
A Co-NP-complete problem is the complement of an NP-complete

problem
CNF satisfiability is NP-complete
Tautology checking is co-NP-complete
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Tautology checking of propositional formulae
Let F be a cover of f (x1 : : : xn )

How to check that F is a tautology?
A divide and conquer approach may be adopted
Theorem
F 1 , (Fx 1) ^ (Fx 1)
j j
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Tautology checking of propositional formulae
Let F be a cover of f (x1 : : : xn )

How to check that F is a tautology?
A divide and conquer approach may be adopted
Theorem
F 1 , (Fx 1) ^ (Fx 1)
j j
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Recursive divide and conquer approach
Section outline
27 Recursive divide and conquer approach

Binary recursion tree
Early termination
Implicit enumeration
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Recursive divide and conquer approach Binary recursion tree

x1
0
1
x2
0
1
x3
0
1
v
The recursive Shannon expansion gives rise to a binary recursion

tree, as illustrated above (only partially)
Vertex label: splitting variable, edge label: its valuation
Path (v ) from the root to v corresponds to cube c (v )
In the diagram above: c (v ) = x1 x2 x3
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x1
0
1
x2
0
1
x3 (v )
0
1
v
The recursive Shannon expansion gives rise to a binary recursion

tree, as illustrated above (only partially)
Vertex label: splitting variable, edge label: its valuation
Path (v ) from the root to v corresponds to cube c (v )
In the diagram above: c (v ) = x1 x2 x3
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Binary recursion tree (contd.)
x1
0
1
x2
0
1
x3 (v )
0
1
v
The entire tree represents the original function f

Each node v in the tree corresponds to fc (v )
Any node where fc (v ) = 1 or 0 can be treated as a leaf node, as
no further expansion is needed TE
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x1
0
1
x2
0
1
x3 (v )
0
1
v

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x1
0
1
x2
0
1
x3 (v )
0
1
v

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Development of binary recursion tree
Example
f (x1 ; x2 ; x3 ) = x1 fx1 + x1 fx1
x1
0
1
(fx1 = 1) 1 fx1
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Example
f (x1 ; x2 ; x3 ) = x1 1 + x1 (x2 fx1 x2 + x2 fx1 x2 )
x1
0
1
(fx1 = 1) 1 x2
0
1
fx1 x2 1 (fx1 x2 = 1)
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Example
f (x1 ; x2 ; x3 ) = x1 1 + x1 (x2 (x3 fx1 x2 x3 + x3 fx1 x2 x3 ) + x2 1)
x1
0
1
(fx1 = 1) 1 x2
0
1
x3 1 (fx1 x2 = 1)
0
1
(fx1 x2 x3 = 1) 1 0 (fx1 x2 x3 = 0)
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Example
f (x1 ; x2 ; x3 ) = x1 1 + x1 (x2 (x3 1 + x3 0) + x2 1)
x1
0
1
(fx1 = 1) 1 x2
0
1
x3 1 (fx1 x2 = 1)
0
1
(fx1 x2 x3 = 1) 1 0 (fx1 x2 x3 = 0)
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Example
f (x1 ; x2 ; x3 ) = x1 + x1 x2 x3 + x1 x2
x1
0
1
(fx1 = 1) 1 x2
0
1
x3 1 (fx1 x2 = 1)
0
1
(fx1 x2 x3 = 1) 1 0 (fx1 x2 x3 = 0)
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Recursive divide and conquer approach Early termination
Special case where all leaf nodes 1
Example
x1
0
1
1 x2
0
1
x3 1
0
1
1 1
Any Binary Recursion Tree (by Shannon expansion) where all the leaf
nodes are 1 represents a tautology
Expansion for tautology checking can stop when any cofactor 0
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Example
x1
0
1
1 x2
0
1
x3 1
0
1
1 1
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Example
x1
0
1
1 x2
0
1
x3 1
0
1
1 1
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Choice of splitting variable

Choices of splitting variables are the decisions to be made while
exapanding the tree.
Example
Consider f = ab + a c and one of its binary recursion trees, where the
splitting variable is a at the topmost level and b in the next level
a
0
1
b b
0 0
1 1
1 0 c c
0 0
1 1
1 0 1 0 TE
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Choice of splitting variable (contd.)
Example
Now consider construction of the binary recursion tree, where the
splitting variable is a at the topmost level and b for fa and c for fa
a
0
1
b c
0 0
1 1
1 0 1 0
Observation: Choice of splitting variable is important as that has a

significant effect on the size of the binary recursion tree TE
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Choice of splitting variable (contd.)
Example
Now consider construction of the binary recursion tree, where the
splitting variable is a at the topmost level and b for fa and c for fa
a
0
1
b c
0 0
1 1
1 0 1 0
Observation: Choice of splitting variable is important as that has a

significant effect on the size of the binary recursion tree TE
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Predicting value of cofactor
Important, as it can help in achieving early bounding

Tautology, if any row in the matrix representation has only dont
care entries
Unsatisfiable, if given SOP is empty
These are special cases
Cofactor is just another Boolean function so hard to solve, in
general
Prediction may be easier when the function has special
properties, e.g. unate functions
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care entries
general
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care entries
general
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Recursive divide and conquer approach Implicit enumeration
Branch and bound
General algorithm for finding optimal solutions of various

optimization problems, especially in discrete and combinatorial
optimization requires two tools
The first one is a splitting procedure that, given a set S of
candidates, returns two or more smaller sets S1 ; S2 ; : : : whose
union covers S
Called branching, since its recursive application defines a tree
structure (the search tree) whose nodes are the subsets of S
Shannon decomposition
Second one is a procedure that computes upper and lower bounds
for the minimum value of f (x ) within a given subset S bounding
Trivial bound for valuation of cofactor [0; 1] (either 0 or 1)
Bounds become equal (0 or 1) at minterm nodes or when value of TE
OF
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cofactor can be predicted, non-trivially
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Branch and bound

union covers S
OF
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Branch and bound

union covers S
OF
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Branch and bound

union covers S
OF
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Branch and bound

union covers S
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Branch and bound

union covers S
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Branch and bound

union covers S
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Branch and bound (contd.)
Strength of the branch and bound approach comes when bounds

on a large subregion show that it contains only inferior solutions,
and so the entire subregion can be discarded without further
examination pruning e.g. when value of cofactor can be
predicted, non-trivially
Pruning may propagate upwards towards the root for tautology
checking, when valuation of any node is 0, the function is not a
tautology
On termination, the 2n min-terms of f have been implicitly
enumerated especially when valuation of non-trivial cofactors
has been done analytically
Polynomial time execution is not guaranteed, but fast (polynomial
time) execution has been observed in practice only when
TECHNO
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sophisticated optimisations are employed in the BB scheme

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tautology
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tautology
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tautology
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tautology
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tautology
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tautology
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Part V
Use of unateness in logic synthesis
28 Unate functions
29 Tautology checking assisted by unateness
30 Complemenation
31 Generation of prime implicants

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Unate functions
Section outline
28 Unate functions
Monotone functions
Containment property for monotonicity
Positive/negative unate functions
Test for unateness
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Unate functions Monotone functions
Monotone functions
Monotonicity
A logic function f is monotone increasing (decreasing) in a variable xj if
a 0 ! 1 change in xj causes f to either remain constant or make a
0 ! 1 (1 ! 0) change.
Let mi be a minterm of the form mi = l1 : : : xi : : : ln

Similarly, let mi+ = l1 : : : xi : : : ln
Monotonic increasing
f (mi ) f (mi+ ) (for all pairs of mi and mi+ )
Monotonic decreasing
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Monotone functions
Monotonicity
0 ! 1 (1 ! 0) change.

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Monotone functions
Monotonicity
0 ! 1 (1 ! 0) change.

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Cofactors when valuation is known
(mi )xi = (mi+ )xi = l1 : : : li 1 li +1 : : : ln

f (mi ) 2 f (mi )xi = (mi+ )xi fx i
If f has mi , then fxi covers both mi and mi+

Thus, if f (mi ) = 1 mi 2 f then
fxi (mi ) = fxi (mi+ ) = 1 (mi )xi = (mi+ )xi fx i
Also, if f (mi ) = 0 mi 2 = f then

fxi (mi ) = fxi (mi+ ) = 0 (mi )xi = (mi+ )xi * fx i
f (mi ) 2 f f (mi ) = 1 (mi )xi = (mi+ )xi fx i
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Cofactors when valuation is known (contd.)
Simlarly, if f (mi+ ) = 1 mi+ 2 f then

Also, if f (mi+ ) = 0 mi+ 2= f then

+
fxi (mi ) = fxi (mi ) = 0 (mi )xi = (mi+ )xi * fxi
f (mi+ ) 2 f f (mi+ ) = 1 (mi )xi = (mi+ )xi fxi
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Unate functions Containment property for monotonicity
Theorem on monotonicity
Theorem
f is monotonic increasing in xi iff fxi fx i
Proof (Necessity).
Consider any pair of hmi ; mi+ i
if f (mi+ ) = 0 then f (mi ) = 0 [monotonicity]
Thus, fxi (mi ) = fxi (mi+ ) = 0
if f (mi ) = 1 then f (mi+ ) = 1 [monotonicity]
Thus, fxi fx i
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Theorem
Proof (Necessity).
Thus, fxi fx i
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Theorem
Proof (Necessity).
Thus, fxi fx i
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Theorem
Proof (Necessity).
Thus, fxi fx i
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Theorem on monotonicity (contd.)
Proof (Sufficiency) (contd.)

fxi fxi
Note that (mi )xi = (mi+ )xi

Also, (mi )xi fxi f (mi ) = 1 and (mi+ )xi fxi f (mi+ ) = 1
Thus, (mi )xi fxi ) (mi+ )xi fxi f (mi ) = 1 ) f (mi+ ) = 1
Similarly, (mi+ )xi * fx ) (mi
i
)xi * fx f (mi
i
) = 0 ) f (mi+ ) = 0
Hence, if fxi fx , then f (mi ) f (mi+), for all pairs of mi
i
and mi+
Monotonic decreasing in terms of cofactors

f is monotonic decreasing in xi iff fxi fx i
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Theorem on monotonicity (contd.)
Proof (Sufficiency) (contd.)

fxi fxi
Note that (mi )xi = (mi+ )xi

Also, (mi )xi fxi f (mi ) = 1 and (mi+ )xi fxi f (mi+ ) = 1
Thus, (mi )xi fxi ) (mi+ )xi fxi f (mi ) = 1 ) f (mi+ ) = 1
Similarly, (mi+ )xi * fx ) (mi
i
)xi * fx f (mi
i
) = 0 ) f (mi+ ) = 0
Hence, if fxi fx , then f (mi ) f (mi+), for all pairs of mi
i
and mi+
Monotonic decreasing in terms of cofactors

f is monotonic decreasing in xi iff fxi fx i
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Unate functions Positive/negative unate functions
Unate functions
Positive (Negative) Unate in xj

A function is positive (negative) unate in xj if it is monotone increasing
(decreasing) in xj
Unate in xj
A function is unate in xj if it is either monotone increasing (positive
unate) or it is monotone decreasing (negative unate) in xj
Unate function
A function is unate if it is unate in all its variables
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Unate functions (contd.)
Example
Let mi = 1001; mi+ = 1011 (for i=3)
For a positive unate function f , valid valuations are:
f (mi ) = 0; f (mi+ ) = 0
f (mi ) = 0; f (mi+ ) = 1
f (mi ) = 1; f (mi+ ) = 1
For a negative unate function f , valid valuations are:
f (mi ) = 0; f (mi+ ) = 0
f (mi ) = 1; f (mi+ ) = 0
f (mi ) = 1; f (mi+ ) = 1
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Example
Let mi = 1001; mi+ = 1011 (for i=3)
f (mi ) = 0; f (mi+ ) = 0
f (mi ) = 0; f (mi+ ) = 1
f (mi ) = 1; f (mi+ ) = 1
f (mi ) = 0; f (mi+ ) = 0
f (mi ) = 1; f (mi+ ) = 0
f (mi ) = 1; f (mi+ ) = 1
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Example
Let mi = 1001; mi+ = 1011 (for i=3)
f (mi ) = 0; f (mi+ ) = 0
f (mi ) = 0; f (mi+ ) = 1
f (mi ) = 1; f (mi+ ) = 1
f (mi ) = 0; f (mi+ ) = 0
f (mi ) = 1; f (mi+ ) = 0
f (mi ) = 1; f (mi+ ) = 1
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Unate functions Test for unateness
Sufficiency test for unate functions
Example
f = x1 x2 + x2 x3
x2
Positive unate in x1
x2 x3
Negative unate in x2 x1 x2
Positive unate in x1 x3
x1
Thus f is a unate function
Unateness from inspection of cover

Given a cover for a function, if xj is either dont care or 1 (dont care or
0) in any cube of the cover, then the function is positive (negative)
unate in xj
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Sufficiency test for unate functions
Example
f = x1 x2 + x2 x3
x2
Positive unate in x1
x2 x3
Negative unate in x2 x1 x2
Positive unate in x1 x3
x1
Thus f is a unate function
Unateness from inspection of cover

Given a cover for a function, if xj is either dont care or 1 (dont care or
0) in any cube of the cover, then the function is positive (negative)
unate in xj
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Counterexample for necessary condition
Example
Consider a cover F = x1 x2 x3 + x2 , x2

evidently unate (from the adjoining
diagram)
Does not pass sufficiency test for x3
x1
unateness
x2 is a binate variable in the cover
F1 = x1 x3 + x2 is a unate function x1 x2 x3
covering f x1 x3 1 0
x2 0
Cover matrix of F1
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Example

evidently unate (from the adjoining x1 x3
diagram)
x2
x1
unateness
x2 0
Cover matrix of F1
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Example

evidently unate (from the adjoining x1 x3
diagram)
x2
x1
unateness
x2 0
Cover matrix of F1
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Example of unate cofactor
Example
We now perform a Shannon decomposition of F = x1 x2 x3 + x2
around x2
F2 = x2 Fx2 + x2 Fx2

= x2 (x1 x3 ) + x2
Shannon decomposition of F1 around the splitting variable x2

produces a unate cofactor x1 x3
However, note that Fx2 Fx 2
and that indicates that F is negative
unate in x2
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Example of unate cofactor
Example
We now perform a Shannon decomposition of F = x1 x2 x3 + x2
around x2
F2 = x2 Fx2 + x2 Fx2

= x2 (x1 x3 ) + x2
Shannon decomposition of F1 around the splitting variable x2

produces a unate cofactor x1 x3
However, note that Fx2 Fx 2
and that indicates that F is negative
unate in x2
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Tautology checking assisted by unateness
Section outline
29 Tautology checking assisted by unateness

Tautology check for unate covers
Unate reduction
Special cases for tautology checking
Algorithm for tautology checking
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Tautology checking assisted by unateness Tautology check for unate covers
Tautology checking for unate covers

Definition
A cover F is positive unate in xi iff (8Cj2 F ) xi 2= Cj
A cover F is negative unate in xi iff (8Cj 2 F ) xi 2 = Cj
Theorem on tautology of unate covers
A unate cover is a tautology if and only if the cover contains a row of all
dont care entries ( or 2 entries)
Proof.
Necessity: Without loss of generality, let F be positive unate in
x1 ; : : : ; xj (with entries 1 or ) and negative unate in xj +1 ; : : : ; xk (with
entries 0 or ).
Cube x1 : : : xj xj +1 : : : xk must be covered for F to be a tautology. That
is possible only with the row of all dont care entries. TE
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Sufficiency: Trivial

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Tautology checking assisted by unateness Tautology check for unate covers
Tautology checking for unate covers

Definition
A cover F is positive unate in xi iff (8Cj2 F ) xi 2= Cj
A cover F is negative unate in xi iff (8Cj 2 F ) xi 2 = Cj
Theorem on tautology of unate covers
A unate cover is a tautology if and only if the cover contains a row of all
dont care entries ( or 2 entries)
Proof.
Necessity: Without loss of generality, let F be positive unate in
x1 ; : : : ; xj (with entries 1 or ) and negative unate in xj +1 ; : : : ; xk (with
entries 0 or ).
Cube x1 : : : xj xj +1 : : : xk must be covered for F to be a tautology. That
is possible only with the row of all dont care entries. TE
OF
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Sufficiency: Trivial

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Tautology checking assisted by unateness Unate reduction
Theorem for tautology when cover is unate is

some variables
Theorem on tautology on reduced unate cover matrix

Let U be the set of unate variables in a cover F : Rearrange the
columns so that they are all placed first so that the cover has the form
F = (UB ) ; where B represent columns for the binate variables.
If U has no rows of dont cares ( or 2), then f
=1
Proof.
For the function f (U ) restricted to the unate variables, f (U ) 1 if and
only if there is a row of all dont cares ( or 2) in U. If f (U )
= 1; then
f
= 1:
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Tautology checking on reduced cover matrix
Theorem on tautology on reduced cover matrix

Let F be a cover (matrix) for f obtained by rearranging
its rows and
A X
columns so that it is for the form F =
T C
; where T represents
a block of dont cares ( or 2), then
A
= 1 ) (F 1 , C 1)
How to check that A = 1?

A
Easiest when is a unate cover all DC rows have already
T
been grouped into T , so A =1
Otherwise, necessary to do a tautology check on A TE
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its rows and
A X
T C
A
= 1 ) (F 1 , C 1)

A
T
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its rows and
A X
T C
A
= 1 ) (F 1 , C 1)

A
T
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(contd.)
Proof.
Necessity: A = 1 ) (F 1 ) C 1)
Assume C = 1. Then there is a minterm m2 such that C (m2 ) = 0, i.e.
m2 is not a cube of C.
Similarly, m1 exists where A(m1 ) = 0, i.e. m1 is not a cube of A.
Now the minterm hm1 ; m2 i in the full space satisfies F (m1 ; m2 ) = 0
since m1 m2 62 AX and m1 m2 62 TC. So hm1 ; m2 i is not in any cube of
F.
Sufficiency: A = 1 ) (C 1 ) F 1)
Trivial
8m1; m2; T (m1) = 1 ^ C (m2) = 1 ) F (hm1; m2i) = 1
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(contd.)
F
A X
T C
C 000 = xj + xj 1, hence F 1 TE

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(contd.)
F
A X
A0 X0
T
T0 C0

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(contd.)
F xj
A X
A0 X0
T
T0 C0 C000
0
1

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(contd.)
F xj
A X
A0 X0
T
T0 C0 C000
0
1

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Tautology checking assisted by unateness Special cases for tautology checking
Special cases for tautology checking for a cover F
If F is empty, then F 0
If there a row of all dont cares ( or 2), then F 1
If there is a column (for xj ) of all 1s (0s), then F
= 1 because
no minterm containing xj (xj ) will be covered
Each row corresponds to a cube. If there are k dont cares in that
row then the cube has 2k minterms. If the sum of minterms over
all the rows is less than 2m where m is the number of inputs to
F(v ) , then F
= 1, F (v ) is the cofactor (sub-space of F ) under
consideration
If a list of minterms are provided, then the function is a tautology if
and only if the number is exactly 2n
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Tautology checking assisted by unateness Special cases for tautology checking
Special cases for tautology checking for a cover F
If F is empty, then F 0
If there a row of all dont cares ( or 2), then F 1
If there is a column (for xj ) of all 1s (0s), then F
= 1 because
no minterm containing xj (xj ) will be covered
Each row corresponds to a cube. If there are k dont cares in that
row then the cube has 2k minterms. If the sum of minterms over
all the rows is less than 2m where m is the number of inputs to
F(v ) , then F
= 1, F (v ) is the cofactor (sub-space of F ) under
consideration
If a list of minterms are provided, then the function is a tautology if
and only if the number is exactly 2n
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Tautology checking assisted by unateness Algorithm for tautology checking
Algorithm for tautology checking

(T, X) checkTautology(F, X) {
// called as checkTautology(UNKOWN, )
// return value: (TRUE, -) or (FALSE, X), X where F(X)=0
(T,X) = checkSpecialCases(F); // FX 0 = 1 if F = 1
if (T != UNKNOWN) return (T, X X);
(T, X, C) = unateReduction(F); // FX 0 = 1 or F (C ) 1?
if (T != UNKNOWN) return (T, X X);
Xi = binateSelect(C);
F0 = cofactor(C, X i );
if((T, X)=checkTautology(F0, X X
i ) && T == FALSE) {
return (FALSE, X);
}
F1 = cofactor(C, Xi );
if((T, X)=checkTautology(F1, X Xi ) && T == FALSE) {
return (FALSE, X);
} TE
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return (TRUE, X);
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}
Complemenation
Section outline
30 Complemenation
Rules for complementation of special covers
Recursive complementation based on cofactors
Complement of unate cover
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Complemenation
Applications of complementation
Example (Static verfication of a synthesised Boolean function)
Suppose F 0 is and implementation of a given cover F of a completely
specified function; how do we know that F 0 is a proper implemenation?
Compute Y = F F 0 (ex-nor of F and F 0 )
Y 1 iff F and F 0 are equivalent how to proceed?
1 Compute Y = FF 0 + F F0 (note the use of complementation)
2 Perform a tautology check on Y
Product and sum of covers can be done in polynomial time
What if F and F 0 are covers of some incompletely specified function?
Example (Computation of OFF-set)

A Boolean function g = hf ; d ; r i is often specified by covers F of f and D of d.
[ D as in Espresso
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A cover R of r may be computed as F
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Complemenation

[ D as in Espresso
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Complemenation

[ D as in Espresso
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Complemenation

[ D as in Espresso
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Complemenation
Need for an efficient complemenation procedure
Consider F = C1 + : : : + Cn
F = C1 Cn [by De Morgans law]
Cj = li1 li2 : : : lij
Cj = li1 + li2 + : : : + lij [by De Morgans law]
Not feasible to compute the product directly as, C1 Cn will have
too many cubes
A more efficient method would be desirable
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Complemenation
too many cubes
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Complemenation
too many cubes
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Complemenation
too many cubes
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Complemenation
too many cubes
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Complemenation Rules for complementation of special covers
Basic rules for complementation of cover F

Cover F is Empty Complement is the tautology, return cube of all
dont cares ( or 2)
Cover F includes the Universal Cube Complement is the empty
cover (containing no cubes)
Cover F contains a Single Cube
c = li1 li2 : : : lik
c = li1 li2 : : : lik = li1 + li2 + : : : + lik
If the cube has k literals, then k cubes, each corresponding to the
complement of the literal, is returned
Single-Input Dependence If the function depends on only one input
xi (i.e., all other input columns contain only dont care entries) and
the x column contains both 1s and 0s, then the function is a
tautology and its complement is the empty cover, which is TE
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returned.
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Complemenation Recursive complementation based on cofactors
Recursive complementation
Principle of recursive complementation
F = xi Fxi + xi Fxi
Proof.
F = xi Fxi + xi Fxi

G = xi Fxi + xi Fxi
FG = 0
F +G =1
FG = 0 ^ F + G = 1 ) F = G

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Decomposition for complementation around a

variable in which f is unate
Suppose f is positive unate in x ; then fx fx , and so xfx xfx

f = xfx + x fx = xfx + xfx + x fx
= xfx + (x + x )fx = xfx + fx
f = (x + fx )fx = xfx + fx fx
= xfx + fx [fx fx ) fx fx ) fx fx = fx ]
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Decomposition for complementation around a

variable in which f is unate (contd.)
Complement of unate cover
F is a positive unate (monotonically increasing) cover in x ;:
F = Fx + x Fx
F is a negative unate (monotonically decreasing) cover in x ;:
F = x Fx + Fx
In the recursive divide and conquer scheme only need to compute
x Fx + Fx or Fx + x Fx , avoiding a round of ANDing in each step
Technique is sound but not optimal
The cubes generated may not be prime
The cover generated may not be irredundant TE
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Decomposition around a binate variable is more interesting

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Complementation procedure by divide and

conquer
complement(F) {
(flag, F) = tryComplementBasic(F)
if(flag) {
return F
} else {
xi = binateSelect(F)
F0 = complement(cofactor(F,xi )) ^ x i
F1 = complement(cofactor(F,xi )) ^ xi
return (F0 _ F1)
}
}
We shall see next that if F is a unate cover, its complement can be
computed directly, without resorting to further decompositions TE
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Complemenation Complement of unate cover
Boolean matrix from unate cover matrix

Obtained by replacing each entry of 0 or 1 with 1 and each entry
of dont care ( / 2) with 0
Since cover is unate, column for xj can be labeled by xj if cover is
positive unate in xj or xj otherwise (negative unate in xj )
Example
F = x2 x4 + x3 x4 x5 + x1 x2 x5 + x1 x3 x5
Unate cube cover F Boolean matrix

x1 x2 x3 x4 x5 x1 x2 x3 x4 x5
2 1 2 0 2
2 2 0 0 1
) 0
0
1 0 1 0
0 1 1 1
1 1 2 2 1 1 1 0 0 1 OF
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1 2 0 2 1 1 0 1 0 1
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Column cover of a Boolean matrix

A column cover is a set of literals li1 ; li2 ; : : : ; lik with the property
that for each cube in the cover, at least one of its literals is
included in the column cover
Determine all minimal column covers (MCC) of the Boolean matrix
A depth first search procedure can be used
Example
Boolean matrix
x1 x2 x3 x4 x5
All MCCs of the adjoining
Boolean matrix are: fx1 ; x4 g,
0 1 0 1 0
fx2; x3g, fx2; x5g and fx4; x5g 0
1
0 1 1 1
1 0 0 1
1 0 1 0 1 TE
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Complement using Boolean matrix of a unate

cover F

Corresponding to each minimal cover li1 ; li2 ; : : : ; lik of the Boolean
matrix of F ; generate the cube li1 li2 lik
Example
All MCCs of the Boolean matrix: (Unate) Cube cover F
fx1; x4g, fx2; x3g ; fx2; x5g and x1 x2 x3 x4 x5
fx4; x5g 2 1 2 0 2
The unate complement of F 2 2 0 0 1
derived from the MCCs: x1 x4 + 1 1 2 2 1
x2 x3 + x2 x5 + x4 x5 1 2 0 2 1
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cover F (contd.)
For the procedure outline to obtain the complement of a given cover,

we shall establish the following to prove the theorem stated next.
Soundness Any cube generated by the procedure belongs to the F
Completeness Any cube belonging to a cover of F is covered by the
generated set of cubes we actually prove a stronger
result, that a cube belonging to any cover of F is
contained within one of the cubes of the generated cover
Theorem on complement of a unate cover

Let M be a unate cover matrix of f . The set of cubes associated with
the minimal column covers of the Boolean matrix (BM ) is a cube cover
of f . TE
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cover F (contd.)
For the procedure outline to obtain the complement of a given cover,

we shall establish the following to prove the theorem stated next.
Soundness Any cube generated by the procedure belongs to the F
Completeness Any cube belonging to a cover of F is covered by the
generated set of cubes we actually prove a stronger
result, that a cube belonging to any cover of F is
contained within one of the cubes of the generated cover
Theorem on complement of a unate cover

Let M be a unate cover matrix of f . The set of cubes associated with
the minimal column covers of the Boolean matrix (BM ) is a cube cover
of f . TE
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Soundness of complementation procedure
Proof.
Let the literals in the column cover be li1 li2 : : : lik
Then, F = li1 (ri1 ;1 + ri1 ;2 + : : :)+ li2 (ri2 ;1 + ri2 ;2 + : : :) + : : : +
lik (rik ;1 + rik ;2 + : : :); where rij ;1 is the cube corresponding to a row
covered by lij as the literals lij form a column cover
Now,
F = li1 (ri1 ;1 + ri1 ;2 + : : :) li2 (ri2 ;1 + ri2 ;2 + : : :) : : :

= (li1 + (ri1 ;1 + ri1 ;2 + : : :)) (li2 + (ri2 ;1 + ri2 ;2 + : : :)) : : :
= li1 li2 : : : lik + : : :
Hence, li1 li2 : : : lik 2 F

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Proof.
Now,
F = li1 (ri1 ;1 + ri1 ;2 + : : :) li2 (ri2 ;1 + ri2 ;2 + : : :) : : :

= (li1 + (ri1 ;1 + ri1 ;2 + : : :)) (li2 + (ri2 ;1 + ri2 ;2 + : : :)) : : :
= li1 li2 : : : lik + : : :

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Proof.
Now,
F = li1 (ri1 ;1 + ri1 ;2 + : : :) li2 (ri2 ;1 + ri2 ;2 + : : :) : : :

= (li1 + (ri1 ;1 + ri1 ;2 + : : :)) (li2 + (ri2 ;1 + ri2 ;2 + : : :)) : : :
= li1 li2 : : : lik + : : :

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Proof.
Now,
F = li1 (ri1 ;1 + ri1 ;2 + : : :) li2 (ri2 ;1 + ri2 ;2 + : : :) : : :

= (li1 + (ri1 ;1 + ri1 ;2 + : : :)) (li2 + (ri2 ;1 + ri2 ;2 + : : :)) : : :
= li1 li2 : : : lik + : : :

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Proof.
Now,
F = li1 (ri1 ;1 + ri1 ;2 + : : :) li2 (ri2 ;1 + ri2 ;2 + : : :) : : :

= (li1 + (ri1 ;1 + ri1 ;2 + : : :)) (li2 + (ri2 ;1 + ri2 ;2 + : : :)) : : :
= li1 li2 : : : lik + : : :

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Completeness of complementation procedure
Proof.
Let c = li1 li2 : : : lik be a cube in any cover (G) of f
Therefore, c must confict with each row or cube of F (otherwise, F
must have a row of all dont cares and F 1 and F = )

Let C 0 = lj1 ; lj2 ; : : : ; ljp be the literals of c that conflict with at least
one literal of each row (cube) of F ; let c 0 = lj1 lj2 : : : ljp and

C = lj1 ; lj2 ; : : : ; ljp
c c 0 and C is a column cover of the Boolean matrix B of F
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Completeness of complementation procedure

(contd.)
Proof. (contd.)
There must be column cover b00 (corresponding cube being c 00 )
among all the minimal column covers of B ; st b00 C
By construction of c 00 from b00 (by complementation of literals in
b00 ), c 00 conflicts with each of the rows (cubes) of F
But c c 0 c 00 , hence for any c 2 G
(G
being any cover of f ),
there is always in cube derived from an MCC of B containing c
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Generation of prime implicants
Section outline
31 Generation of prime implicants

Distance between cubes
Cube consensus
Generation of primes
Recursive scheme for generating primes
Unate Prime Theorem
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Generation of prime implicants Distance between cubes
Distance and intersection between cubes
Given two cubes c1 and c2 , they differ in x if c1 has literal x and c2

has literal x (or vice-versa)
If both cubes have literal x, or both have literal x , or if variable x
does not appear in at least one of the cubes, then they do not
differ in variable x
The distance between two cubes is the number of inputs where
they differ
If two cubes have distance 1 or greater, they do not intersect
If two cubes have distance 0, they intersect
The intersection cube has literals as the union of literals of the two
cubes just ANDing
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Distance and intersection between cubes (contd.)
Example
Let c1 = x1 x2 x3 , c2 = x1 x3 x4 ; c3 = x1 x2 x3 x4 and c4 = x2 x4
Cubes c1 and c2 differ in x3
They do not differ in x1 , x2 and x4
Distance between c1 and c2 is 1
c1 and c3 differ in x1 and x2 ; their distance is 2
Distance between c1 and c4 is 0, then intersect
Their intersection is the cube x1 x2 x3 x4
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Example
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Example
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Example
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Example
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Example
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Generation of prime implicants Cube consensus
Consensus between cubes
Definition
The consensus of two cubes terms will be defined if they do not
intersect.
Two cubes having distance 2 or greater have empty consensus
Let c1 and c2 have distance 1, and differ in variable x
Let x occur as literal xc1 in c1 and as xc2 in c2
Cubes c1 and c2 do not intersect and are contained in the cubes
xc1 and xc2 , respectively
Their consensus is (c1 nxc1 ) \ (c2 nxc2 )
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Generation of prime implicants Cube consensus
Consensus between cubes (contd.)
Example
Let c1 = x1 x2 x3 and c2 = x1 x3 x4
Consensus between c1 and c2 is c3 = x1 x2 x4
NB: c3 * c1, c3 * c2
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Generation of prime implicants Generation of primes
Generation of primes
Given a function f and a splitting variable x, each prime implicant of f

falls into one of 3 categories: either
1 it contains literal x present in the part of the hypercube where
x =1
2 it contains literal x present in the part of the hypercube where
x =0
3 it contains neither x nor x spans both halves
Example
f with cover F = xy z + x y + y z, then wrt x, the three cubes are in
categories (i), (ii) and (iii), respectively
How to find the prime implicants in each of the categories? TE

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Generation of primes (contd.)
Prime Consensus Theorem

Let f be a Boolean function, with cover F (which covers the entire
ON-set and DC-set). Also, let x be any input variable. Then the prime
implicants of f can be partitioned into 3 sets:
P1, which contains primes having literal x;
P0, which contains primes having literal x ;
P , which contains primes independent of x (dont care in x)
Each prime implicant p in P is the consensus of two other primes,
p1 and p0 , where p1 is from P1 and p0 is from P0
Thus, p = consensus(p1 ; p0 ), for some primes p1 2 P1 and p0 2 P0
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Let cover F of f be decomposed around x to obtain P1 and P0

Primes in P may be generated as follows:
For each pair of primes, (p1 ; p0 ), p1 2 P1 and p0 2 P0, generate
the consensus cube p1=0 = consensus(p1 ; p0 )
Resulting set P1=0 = consensus(P1; P0) of all such consensus
cubes contains all the primes of P
Non-prime cubes of P1=0, if any, must be deleted use SCC
Some cubes of P0 and P1 may be contained within cubes of P1=0
Example
c1 = x1 x3 ; c2 = x1 x3 , c3 = x1 x2
p1 = consensus(c1 ; c2 ) = x3 ; c1 p1, c2 p1
p2 = consensus(c1 ; c3 ) = x2 x3 ; p2 p1
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Let cover F of f be decomposed around x to obtain P1 and P0

Primes in P may be generated as follows:
For each pair of primes, (p1 ; p0 ), p1 2 P1 and p0 2 P0, generate
the consensus cube p1=0 = consensus(p1 ; p0 )
Resulting set P1=0 = consensus(P1; P0) of all such consensus
cubes contains all the primes of P
Non-prime cubes of P1=0, if any, must be deleted use SCC
Some cubes of P0 and P1 may be contained within cubes of P1=0
Example
c1 = x1 x3 ; c2 = x1 x3 , c3 = x1 x2
p1 = consensus(c1 ; c2 ) = x3 ; c1 p1, c2 p1
p2 = consensus(c1 ; c3 ) = x2 x3 ; p2 p1
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Generation of prime implicants Recursive scheme for generating primes
Recursive prime generation

ON-set and DC-set)
Let x be any input variable
The prime implicants of f can be generated as follows:
primes(f ) = SCC(P1 [ P0 [ consensus(P1 ; P0 ))
P1 = x (primes(Fx )) and P0 = x (primes(Fx 0 ))

The same strategy used for tautology checking can be used for
choosing the splitting variable
Used in espresso-exact
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Recursive prime generation
Example
Consider the cover
F = x2 x3 x4 + x2 x3 x4 + x2 x3 x4 + x1 x3 x4 + x3 x4
We would like to find all its prime implicants by the recursive prime
generation scheme.
x1 x2 x3 x4
0 0 0
1 0 0
Cover matrix of F :
0 0 1
0 1 0
1 1 OF
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Recursive prime generation (contd.)

Example
x1 x2 x3 x4
x1 x2 x3 x4
x4 Fx :
0 0 0
x4 Fx4 : 0 0 1
4
1 0 0
1 1
0 1 0
x3 x4 Fx3 x4 :
x1 x2 x3 x4 x1 x2 x3 x4
x3 x4 Fx3 x4 :
0 0 1 1 1
x1 x2 x3 x4
0 0 1
primes(x4 Fx4 ): 1 1
0 1
x1 x2 x3 x4
SCC(primes(x4 Fx4 )): 1 1 OF
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Example
x1 x2 x3 x4
x1 x2 x3 x4
x4 Fx :
0 0 0
x4 Fx4 : 0 0 1
4
1 0 0
1 1
0 1 0
x3 x4 Fx3 x4 :
x1 x2 x3 x4 x1 x2 x3 x4
x3 x4 Fx3 x4 :
0 0 1 1 1
x1 x2 x3 x4
0 0 1
0 1
x1 x2 x3 x4
TECHNO
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Example
x1 x2 x3 x4
x1 x2 x3 x4
x4 Fx :
0 0 0
x4 Fx4 : 0 0 1
4
1 0 0
1 1
0 1 0
x3 x4 Fx3 x4 :
x1 x2 x3 x4 x1 x2 x3 x4
x3 x4 Fx3 x4 :
0 0 1 1 1
x1 x2 x3 x4
0 0 1
0 1
x1 x2 x3 x4
TECHNO
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Example
x1 x2 x3 x4
x1 x2 x3 x4
x4 Fx :
0 0 0
x4 Fx4 : 0 0 1
4
1 0 0
1 1
0 1 0
x3 x4 Fx3 x4 :
x1 x2 x3 x4 x1 x2 x3 x4
x3 x4 Fx3 x4 :
0 0 1 1 1
x1 x2 x3 x4
0 0 1
0 1
x1 x2 x3 x4
TECHNO
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Example
x1 x2 x3 x4
x1 x2 x3 x4
x4 Fx :
0 0 0
x4 Fx4 : 0 0 1
4
1 0 0
1 1
0 1 0
x3 x4 Fx3 x4 :
x1 x2 x3 x4 x1 x2 x3 x4
x3 x4 Fx3 x4 :
0 0 1 1 1
x1 x2 x3 x4
0 0 1
0 1
x1 x2 x3 x4
TECHNO
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0 1
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Example
x1 x2 x3 x4
x1 x2 x3 x4
x4 Fx :
0 0 0
x4 Fx4 : 0 0 1
4
1 0 0
1 1
0 1 0
x3 x4 Fx3 x4 :
x1 x2 x3 x4 x1 x2 x3 x4
x3 x4 Fx3 x4 :
0 0 1 1 1
x1 x2 x3 x4
0 0 1
0 1
x1 x2 x3 x4
TECHNO
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Example
x1 x2 x3 x4
x1 x2 x3 x4
x4 Fx :
0 0 0
x4 Fx4 : 0 0 1
4
1 0 0
1 1
0 1 0
x3 x4 Fx3 x4 :
x1 x2 x3 x4 x1 x2 x3 x4
x3 x4 Fx3 x4 :
0 0 1 1 1
x1 x2 x3 x4
0 0 1
0 1
x1 x2 x3 x4
TECHNO
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Example
x1 x2 x3 x4
x3 x4 Fx3 x4 : primes(x3 x4 Fx3 x4 ):
x1 x2 x3 x4
0 0 0
0 0
1 0 0
x3 x4 Fx3 x4 :

x1
0
x2 x3
1
x4
0
primes(x3 x4 Fx x )3 4
x1 x2 x3 x4
0 0
primes(x4 Fx4 ): 0 1 0
0 0
x1 x2 x3 x4
SCC(primes(x4 Fx4 )): 0 0
0 0 TE
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Example
x1 x2 x3 x4
x1 x2 x3 x4
0 0 0
0 0
1 0 0
x3 x4 Fx3 x4 :

x1
0
x2 x3
1
x4
0
x1 x2 x3 x4
0 0
0 0
x1 x2 x3 x4
0 0 TE
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Example
x1 x2 x3 x4
x1 x2 x3 x4
0 0 0
0 0
1 0 0
x3 x4 Fx3 x4 :

x1
0
x2 x3
1
x4
0
x1 x2 x3 x4
0 0
0 0
x1 x2 x3 x4
0 0 TE
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Example
x1 x2 x3 x4
x1 x2 x3 x4
0 0 0
0 0
1 0 0
x3 x4 Fx3 x4 :

x1
0
x2 x3
1
x4
0
x1 x2 x3 x4
0 0
0 0
x1 x2 x3 x4
0 0 TE
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Example
x1 x2 x3 x4
x1 x2 x3 x4
0 0 0
0 0
1 0 0
x3 x4 Fx3 x4 :

x1
0
x2 x3
1
x4
0
x1 x2 x3 x4
0 0
0 0
x1 x2 x3 x4
0 0 TE
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Example
x1 x2 x3 x4
x1 x2 x3 x4
0 0 0
0 0
1 0 0
x3 x4 Fx3 x4 :

x1
0
x2 x3
1
x4
0
x1 x2 x3 x4
0 0
0 0
x1 x2 x3 x4
0 0 TE
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Example
x1 x2 x3 x4 x1 x2 x3 x4
1 1 1 1
0 1 0 1
0 0
primes(F ): SCC(primes(F )):
0 0
0 0 0 0
0 1 0 1
0 0 0 0
0 0 0 0
The set of prime implicants are:
fx3 x4 + x2 x4 + x3 x4 + x1 x4 + x1 x3 + x2 x3 + x1 x2 g
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Example
x1 x2 x3 x4 x1 x2 x3 x4
1 1 1 1
0 1 0 1
0 0
0 0
0 0 0 0
0 1 0 1
0 0 0 0
0 0 0 0
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Example
x1 x2 x3 x4 x1 x2 x3 x4
1 1 1 1
0 1 0 1
0 0
0 0
0 0 0 0
0 1 0 1
0 0 0 0
0 0 0 0
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Base cases for prime generation
Cover F includes the Universal Cube Here, F is a tautology.

Return a cover containing the universal cube.
Single-Input Dependence If the function depends on only one input
x (i.e., all other input columns contain only -), and the x column
contains both 1s and 0s, then the function is a tautology. Return
a cover containing the universal cube.
Cover F is Empty A cover is empty if it contains no cube. In this
case, the function is all 0. Return the empty cover (contains no
cubes).
Cover F contains a Single Cube In this case, the cube itself must
be the only prime of the function. Return F (which contains the
single cube).
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Generation of prime implicants Unate Prime Theorem
Primes of a unate cover
Unate Prime Theorem

ON-set and DC-set). If F is a unate cover, then cover F contains all of
its prime implicants. In addition, F may contain some non-primes,
which can be deleted. That is:
primes(f ) = SCC(F )
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Primes of a unate cover (contd.)
Proof (by induction).

Induction base: Any function in a single variable is unate and a unate
cover of that function contains the prime cubes.
Consider all possible functions on a single variable x:
f (x ) = 0 The cover only has only the empty cube
f (x ) = x The cover only has the cube x
f (x ) = 1 The cover must contain the universal cube - , otherwise
the cover will not be unate
A cover of x and x is not a unate cover, although the
function represented is unate
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Proof (by induction, contd.).

Induction step:
By hypothesis, assuming that F is positive unate in x, both Fx and
Fx satisfy the statement of the theorem; also Fx Fx
Thus any prime cube p0 of x Fx has a corresponding prime cube
p1 in xFx such that the distance between p0 and p1 is 1
The cube consensus(p1 ; p0 ) is a prime cube of F
Non-prime cubes after computing the consensus are removed by
SCC
The remaining cubes are prime implicants of F
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Induction step:
SCC
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Induction step:
SCC
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Generation of prime implicants Iterated consensus method
Computing PIs: iterated consensus method
Start with: SOP standard form (as compared to the canonical form
in Tabular Method)
Goal: sum of all PIs (likely to be redundant!)
Basic idea: xy + x z = xy + x z + yz consensus law
Start with any cover
Need to compare every pair of terms check:
Do they have consensus?
Does one contain the other?
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Generation of prime implicants Iterated consensus method
Example
f (w ; x ; y ; z ) = wx + x y + xyz
= wx + x y + xyz + wy
= wx + x y + xyz + wy
= wx + x y + xyz + wy + yz
= wx + x y + wy + yz
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Part VI
The Espresso logic synthesis tool
32 Irredundant
33 Expand
34 Reduce
35 Lastgasp
36 BDDs TE
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About Espresso
Espresso was developed by Robert Brayton

Radically different approach the technique of Quine-McCluskey
Cube oriented rather than minterm oriented significantly more
efficient
Rudell later published the variant Espresso-MV in 1986 as
Multiple-Valued Logic Minimization for PLA Synthesis
Many other variants are available
Related software packages: Espresso from Berkley, Minilog, Logic
Friday
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Espresso minimisation loop
Espresso minimisation loop
Basic scheme may be as follows:

Start with an initial solution
Extend the solution to its neighboring solutions
Evaluate the solutions to find the best one
Repeat until a satisfactory solution is found or run out of time
Optimality is not guaranteed
Run times can be well controlled
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Outline of Espresso minimisation loop
Outline of Espresso minimisation loop
newCost = coverCost(F);
do {
F = reduce(F, D);
// trim each cube maximally
F = expand(F, D);
// grow each cube maximally
F = irredundant(F, D);
// drop redundant cubes
cost = newCost;
newCost = coverCost(F);
} while (newCost < cost);
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Irredundant
Section outline
32 Irredundant
Covering function g
Complement of covering function (g ) via MCCs of B of g
Computing g from F

Contribution of each cube of F to g
Leveraging unateness to generate cubes of g
Comparison with QM covering
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Irredundant Covering function g
Irredundant
Irredundant Cover
a cover F of cubes fci g, find a minimum subset of these as
Given
cik that is still a cover, i.e.
X
f cik f +d
k
From earlier result we know how to check whether any individual

cube of F is redundant
However, we need to identify a subset of cubes that can be
dropped from F to get the minimum subset of F covering f
Generating all possible subsets and testing those would be a poor
approach TE
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Irredundant
Irredundant Cover
a cover F of cubes fci g, find a minimum subset of these as
Given
cik that is still a cover, i.e.
X
f cik f +d
k
From earlier result we know how to check whether any individual

cube of F is redundant
However, we need to identify a subset of cubes that can be
dropped from F to get the minimum subset of F covering f
Generating all possible subsets and testing those would be a poor
approach TE
OF
TECHNO
LO
GY
ITU
IAN INST
KH
ARAGPUR
IND

19 5 1
yog, km s kOflm^
Irredundant (contd.)
Let F = fci g, i = 1; : : : ; m
Let fyi g, i = 1; : : : ; m be a set of decision variables indicating
whether ci should be present in the cover
We could think of constructing a function g (y1 ; y2 ; : : : ; ym ) so that
g (~y ) = 1 iff ~y represents a cover of F
g is positive unate
A prime of g (cube with minimal yj s) represents a solution, largest
prime is favoured
We shall not try to construct g directly
TECHNO
OF LO
TE
GY
ITU
IAN INST
KH
ARAGPUR
IND

19 5 1
yog, km s kOflm^
Let F = fci g, i = 1; : : : ; m
g is positive unate
prime is favoured
TECHNO
OF LO
TE
GY
ITU
IAN INST
KH
ARAGPUR
IND

19 5 1
yog, km s kOflm^
Let F = fci g, i = 1; : : : ; m
g is positive unate
prime is favoured
TECHNO
OF LO
TE
GY
ITU
IAN INST
KH
ARAGPUR
IND

19 5 1
yog, km s kOflm^
Let F = fci g, i = 1; : : : ; m
g is positive unate
prime is favoured
TECHNO
OF LO
TE
GY
ITU
IAN INST
KH
ARAGPUR
IND

19 5 1
yog, km s kOflm^
Irredundant ) via MCCs of B of g
Complement of covering function (g
Complement of covering function (g ) via MCCs of

B of g
X
(y1 ; y2 ; : : : ; ym ) = 1 ,
g cik is not a cover
k
(expressed in yj ) indicates sets of cubes which if dropped will

g
cause the remaining cubes not to be a cover
is unate and monotone decreasing
g

Consider the Boolean matrix B of g
A minimal column cover (MCC) of B is a prime of (g ) = g
We are interested in a prime of g, but not g itself!
TECHNO
OF LO
TE
GY
ITU
IAN INST
KH
ARAGPUR
IND

19 5 1
yog, km s kOflm^

B of g
X
(y1 ; y2 ; : : : ; ym ) = 1 ,
k

g
g

TECHNO
OF LO
TE
GY
ITU
IAN INST
KH
ARAGPUR
IND

19 5 1
yog, km s kOflm^

B of g
X
(y1 ; y2 ; : : : ; ym ) = 1 ,
k

g
g

TECHNO
OF LO
TE
GY
ITU
IAN INST
KH
ARAGPUR
IND

19 5 1
yog, km s kOflm^

B of g
X
(y1 ; y2 ; : : : ; ym ) = 1 ,
k

g
g

TECHNO
OF LO
TE
GY
ITU
IAN INST
KH
ARAGPUR
IND

19 5 1
yog, km s kOflm^
Illustrating g, g and B
Example
F = bc + ac + ab + bc

The four decision variables are y1 ; y2 ; y3 ; y4
From an inspection of the cubes of the given cover, g = y1 y4 (y2 + y3 )

g = y1 + y4 + y2 y3
y1 y2 y3 y4
: B
Boolean matrix of g = 1
0
0
0
0
0
0
1
0 1 1 0
We are after a MCC of B because that corrosponds to a prime of g,
which we need
fy1 ; y2 ; y4 g is a MCC and corresponds to the prime y1 y2 y4 of g
c + bc of F
corresponding to the irredundant cover bc + a
TE
OF
TECHNO
LO
GY
ITU
IAN INST
KH
ARAGPUR
IND

19 5 1
yog, km s kOflm^
Example


g = y1 + y4 + y2 y3
y1 y2 y3 y4
: B
0
0
0
0
0
0
1
0 1 1 0
which we need
c + bc of F
TE
OF
TECHNO
LO
GY
ITU
IAN INST
KH
ARAGPUR
IND

19 5 1
yog, km s kOflm^
Example


g = y1 + y4 + y2 y3
y1 y2 y3 y4
: B
0
0
0
0
0
0
1
0 1 1 0
which we need
c + bc of F
TE
OF
TECHNO
LO
GY
ITU
IAN INST
KH
ARAGPUR
IND

19 5 1
yog, km s kOflm^
Example


g = y1 + y4 + y2 y3
y1 y2 y3 y4
: B
0
0
0
0
0
0
1
0 1 1 0
which we need
c + bc of F
TE
OF
TECHNO
LO
GY
ITU
IAN INST
KH
ARAGPUR
IND

19 5 1
yog, km s kOflm^
Example


g = y1 + y4 + y2 y3
y1 y2 y3 y4
: B
0
0
0
0
0
0
1
0 1 1 0
which we need
c + bc of F
TE
OF
TECHNO
LO
GY
ITU
IAN INST
KH
ARAGPUR
IND

19 5 1
yog, km s kOflm^
Example


g = y1 + y4 + y2 y3
y1 y2 y3 y4
: B
0
0
0
0
0
0
1
0 1 1 0
which we need
c + bc of F
TE
OF
TECHNO
LO
GY
ITU
IAN INST
KH
ARAGPUR
IND

19 5 1
yog, km s kOflm^
Irredundant from F
Computing g
Computing g from F
While computing g we are essentially trying to identify cubes

which, if dropped, will disturb coverage
A scheme could be to look into the region of each cube in the
given cover
The region of each cube is covered by itself and possibly by a set
of other cubes too
If region is not covered by other cubes, this is a prime implicant of
the cover
Therefore, each such set of cubes if dropped will disturb the
coverage and thus represents a cube yi1 :yi2 : : : yik of g

Once we have g , we can then construct the MCC of its Boolean
matrix and get our irredundant cover TECHNO
OF LO
TE
GY
ITU
IAN INST
KH
ARAGPUR
IND

19 5 1
yog, km s kOflm^
Irredundant from F
Computing g
Computing g from F

given cover
of other cubes too
the cover

OF LO
TE
GY
ITU
IAN INST
KH
ARAGPUR
IND

19 5 1
yog, km s kOflm^
Irredundant from F
Computing g
Computing g from F

given cover
of other cubes too
the cover

OF LO
TE
GY
ITU
IAN INST
KH
ARAGPUR
IND

19 5 1
yog, km s kOflm^
Irredundant from F
Computing g
Computing g from F

given cover
of other cubes too
the cover

OF LO
TE
GY
ITU
IAN INST
KH
ARAGPUR
IND

19 5 1
yog, km s kOflm^
Irredundant
How to look into the region of each cube? Do so using Shannon

cofactors
How to look for sets of cubes to drop, to disturb coverage? Do so
using the tautology checking principle
Each cube ci being considered is from the cover, hence
Fci 1
While computing the cofactor, cubes of the cover having
empty intersetion with ci will be dropped
Only cubes with non-empty intersection remain to form
the tautology
We would like to identify the cubes that contribute to the

formation of the tautology to get a row of g TECHNO
OF LO
TE
GY
ITU
IAN INST
KH
ARAGPUR
IND

19 5 1
yog, km s kOflm^
Irredundant

cofactors
Fci 1
the tautology

OF LO
TE
GY
ITU
IAN INST
KH
ARAGPUR
IND

19 5 1
yog, km s kOflm^
Irredundant

cofactors
Fci 1
the tautology

OF LO
TE
GY
ITU
IAN INST
KH
ARAGPUR
IND

19 5 1
yog, km s kOflm^
Irredundant

cofactors
Fci 1
the tautology

OF LO
TE
GY
ITU
IAN INST
KH
ARAGPUR
IND

19 5 1
yog, km s kOflm^
Irredundant

cofactors
Fci 1
the tautology

OF LO
TE
GY
ITU
IAN INST
KH
ARAGPUR
IND

19 5 1
yog, km s kOflm^
Irredundant

cofactors
Fci 1
the tautology

OF LO
TE
GY
ITU
IAN INST
KH
ARAGPUR
IND

19 5 1
yog, km s kOflm^
Irredundant

Fci could be a unate cover, otherwise, do a binate decomposition
of Fci until all leaf nodes are unate
Since Fci 1, all the leaf nodes must be 1
Thus, the cover matrix of each unate leaf must have least one row
of dont cares
There are the only rows that interest us dropping all these rows
forces the leaf not to be a tautology
Each row comes from a cube of the cover so we know which yi s
to use
Now, some of these leaves could be entirely within the dont care
region (d, covered by D)
These are regions entirely within the DC region and do not affect
the ON-set TE
OF
TECHNO
LO
GY
ITU
IAN INST
KH
ARAGPUR
These leaves should be ignored, but how?
IND

19 5 1
yog, km s kOflm^
Irredundant

Fci could be a unate cover, otherwise, do a binate decomposition
of Fci until all leaf nodes are unate
Since Fci 1, all the leaf nodes must be 1
Thus, the cover matrix of each unate leaf must have least one row
of dont cares
There are the only rows that interest us dropping all these rows
forces the leaf not to be a tautology
Each row comes from a cube of the cover so we know which yi s
to use
Now, some of these leaves could be entirely within the dont care
region (d, covered by D)
These are regions entirely within the DC region and do not affect
the ON-set TE
OF
TECHNO
LO
GY
ITU
IAN INST
KH
ARAGPUR
These leaves should be ignored, but how?
IND

19 5 1
yog, km s kOflm^
Irredundant

(contd.)
h i
Let X = Fci , Y = Dci , do a tautology check on X
Y instead of just
Fci , keeping track of the rows coming D
h i
X
Ignore any leaf node in the recursive decomposition of Y having
has a row of all dont cares in the Y part
Otherwise, if rows corresponding to ci1 ; ci2 ; : : : ; ci1 are all dont
cares in a leaf node, then yi1 yi2 : : : yi1 is a row in g
and so the
appropriate row should be introduced into B
TECHNO
OF LO
TE
GY
ITU
IAN INST
KH
ARAGPUR
IND

19 5 1
yog, km s kOflm^
Irredundant
Illustrating construction of g
Example
c + ab + b c
Cover: F = bc + a
D=
a b c
bc (y1 ) 1 1
c (y2 )
Cover matrix of F : a 0 1
b (y3 )
a 0 0
c (y4 )
b 0 0
a b c
Fbc (unate): bc (y1 )
c (y2 )
a 0
y1 2 g (~y ) TE
OF
TECHNO
LO
GY
ITU
IAN INST
KH
ARAGPUR
IND

19 5 1
yog, km s kOflm^
Irredundant
Illustrating construction of g
Example
c + ab + b c
Cover: F = bc + a
D=
a b c
bc (y1 ) 1 1
c (y2 )
Cover matrix of F : a 0 1
b (y3 )
a 0 0
c (y4 )
b 0 0
a b c
Fbc (unate): bc (y1 )
c (y2 )
a 0
y1 2 g (~y ) TE
OF
TECHNO
LO
GY
ITU
IAN INST
KH
ARAGPUR
IND

19 5 1
yog, km s kOflm^
Irredundant
Illustrating construction of g (contd.)

Example (contd.)
a b c
bc (y1 ) 1
Fac :
c (y2 )
a
b (y3 )
a 0
a b c
(Fac )b (unate): ac (y2 )
ab (y3 )
y2 y3 2 g (~y )
a b c
(Fac )b (unate): bc (y1 )
c (y2 )
a
y1 y2 2 g (~y )
TECHNO
OF LO
TE
GY
ITU
IAN INST
KH
ARAGPUR
IND

19 5 1
yog, km s kOflm^
Irredundant

Example (contd.)
a b c
bc (y1 ) 1
Fac :
c (y2 )
a
b (y3 )
a 0
a b c
ab (y3 )
y2 y3 2 g (~y )
a b c
c (y2 )
a
y1 y2 2 g (~y )
TECHNO
OF LO
TE
GY
ITU
IAN INST
KH
ARAGPUR
IND

19 5 1
yog, km s kOflm^
Irredundant

Example (contd.)
a b c
bc (y1 ) 1
Fac :
c (y2 )
a
b (y3 )
a 0
a b c
ab (y3 )
y2 y3 2 g (~y )
a b c
c (y2 )
a
y1 y2 2 g (~y )
TECHNO
OF LO
TE
GY
ITU
IAN INST
KH
ARAGPUR
IND

19 5 1
yog, km s kOflm^
Irredundant

Example (contd.)
a b c
bc (y1 ) 1
Fac :
c (y2 )
a
b (y3 )
a 0
a b c
ab (y3 )
y2 y3 2 g (~y )
a b c
c (y2 )
a
y1 y2 2 g (~y )
TECHNO
OF LO
TE
GY
ITU
IAN INST
KH
ARAGPUR
IND

19 5 1
yog, km s kOflm^
Irredundant

Example (contd.)
a b c
bc (y1 ) 1
Fac :
c (y2 )
a
b (y3 )
a 0
a b c
ab (y3 )
y2 y3 2 g (~y )
a b c
c (y2 )
a
y1 y2 2 g (~y )
TECHNO
OF LO
TE
GY
ITU
IAN INST
KH
ARAGPUR
IND

19 5 1
yog, km s kOflm^
Irredundant

Example (contd.)
a b c
c (y2 )
a 1
Fac :
b (y3 )
a
c (y4 )
b 0
a b c
(Fac )c (unate): ab (y3 )
b c (y4 )
y3 y4 2 g (~y )
a b c
(Fac )c (unate): ac (y2 )
ab (y3 )
y2 y3 2 g (~y )
TECHNO
OF LO
TE
GY
ITU
IAN INST
KH
ARAGPUR
IND

19 5 1
yog, km s kOflm^
Irredundant

Example (contd.)
a b c
c (y2 )
a 1
Fac :
b (y3 )
a
c (y4 )
b 0
a b c
b c (y4 )
y3 y4 2 g (~y )
a b c
ab (y3 )
y2 y3 2 g (~y )
TECHNO
OF LO
TE
GY
ITU
IAN INST
KH
ARAGPUR
IND

19 5 1
yog, km s kOflm^
Irredundant

Example (contd.)
a b c
c (y2 )
a 1
Fac :
b (y3 )
a
c (y4 )
b 0
a b c
b c (y4 )
y3 y4 2 g (~y )
a b c
ab (y3 )
y2 y3 2 g (~y )
TECHNO
OF LO
TE
GY
ITU
IAN INST
KH
ARAGPUR
IND

19 5 1
yog, km s kOflm^
Irredundant

Example (contd.)
a b c
c (y2 )
a 1
Fac :
b (y3 )
a
c (y4 )
b 0
a b c
b c (y4 )
y3 y4 2 g (~y )
a b c
ab (y3 )
y2 y3 2 g (~y )
TECHNO
OF LO
TE
GY
ITU
IAN INST
KH
ARAGPUR
IND

19 5 1
yog, km s kOflm^
Irredundant

Example (contd.)
a b c
Fbc (unate):
bc (y4 )
y4 2 g (~y )
y1 y2 y3 y4
y1 1
y y 1 1
Cover matrix of g (~y ): 2 3
y1 y2 1 1
y3 y4 1 1
y4 1
MCCs of Boolean matrix of g (~y ): fy1 ; y2 ; y4 g ; fy1 ; y3 ; y4 g
Irredundant cover: fy1 ; y2 ; y4 g or fy1 ; y3 ; y4 g
g (~y ) = y1 y2 y4 + y1 y3 y4
TECHNO
OF LO
TE
GY
ITU
IAN INST
KH
ARAGPUR
IND

19 5 1
yog, km s kOflm^
Irredundant

Example (contd.)
a b c
Fbc (unate):
bc (y4 )
y4 2 g (~y )
y1 y2 y3 y4
y1 1
y y 1 1
y1 y2 1 1
y3 y4 1 1
y4 1
g (~y ) = y1 y2 y4 + y1 y3 y4
TECHNO
OF LO
TE
GY
ITU
IAN INST
KH
ARAGPUR
IND

19 5 1
yog, km s kOflm^
Irredundant

Example (contd.)
a b c
Fbc (unate):
bc (y4 )
y4 2 g (~y )
y1 y2 y3 y4
y1 1
y y 1 1
y1 y2 1 1
y3 y4 1 1
y4 1
g (~y ) = y1 y2 y4 + y1 y3 y4
TECHNO
OF LO
TE
GY
ITU
IAN INST
KH
ARAGPUR
IND

19 5 1
yog, km s kOflm^
Irredundant

Example (contd.)
a b c
Fbc (unate):
bc (y4 )
y4 2 g (~y )
y1 y2 y3 y4
y1 1
y y 1 1
y1 y2 1 1
y3 y4 1 1
y4 1
g (~y ) = y1 y2 y4 + y1 y3 y4
TECHNO
OF LO
TE
GY
ITU
IAN INST
KH
ARAGPUR
IND

19 5 1
yog, km s kOflm^
Irredundant Comparison with QM covering
Relationship with QM
The covering problem of QM also requires identification of MCCs

In QM the columns correspond to prime implicants and rows to
minterms
For irredundant cover we do not consider all prime implicants, but
only some cover of F which we try to make irredundant
columns correspond to decisions variables
In the cover matrix of g

yi s while rows correspond to products of these variables
TECHNO
OF LO
TE
GY
ITU
IAN INST
KH
ARAGPUR
IND

19 5 1
yog, km s kOflm^
Expand
Section outline
33 Expand
Issues in expanding a cube
Blocking matrix
Literals to delete using blocking matrix
Expanding to form a supercube
TECHNO
OF LO
TE
GY
ITU
IAN INST
KH
ARAGPUR
IND

19 5 1
yog, km s kOflm^
Expand Issues in expanding a cube

Expansion of a cube in F
Take cube c in F and make it prime by removing literals
remove a literal li from c to get a bigger cube c 0 so that c 0 f + d

could be used in a greedy approach
expansion could also be constrained so that c 0 \ R = ; where R
is some cover of r
remove as many such literals as possible with a more global
view
in general any one of several different sets of literals may be
removed
which set should be chosen for deletion for cube expansion?
a literal selection function similar to cube selection function for TE
OF
TECHNO
LO
GY
ITU
IAN INST
KH
ARAGPUR
IND
irredundant could be considered

19 5 1
yog, km s kOflm^


is some cover of r
view
removed
OF
TECHNO
LO
GY
ITU
IAN INST
KH
ARAGPUR
IND

19 5 1
yog, km s kOflm^


is some cover of r
view
removed
OF
TECHNO
LO
GY
ITU
IAN INST
KH
ARAGPUR
IND

19 5 1
yog, km s kOflm^
Expand Blocking matrix
Blocking matrix B c for cube c

Let R = fri g be any cover of r (OFF-set)
Consider B c with rows corresponding to literals in c and columns
corresponding to cubes in R constructed as follows:

Bij = 1 ,
xj 2 c ^ xj 2 ri or
xj 2 c ^ x j 2 ri
Example
Let c z
= wxy
Let R = fx z + wx z + w y z g

w x y z
x z 0 1 0 1
Blocking matrix B c is:
wx z 1 0 0 0
w y z
TECHNO
OF
1 0 1 0
LO
TE
GY
ITU
IAN INST
KH
ARAGPUR
IND

19 5 1
yog, km s kOflm^
Blocking matrix B c for cube c (contd.)

F = fci g f + d, ci = lj , R = fri g is any cover of r (OFF-set)
Bij = 1 , lj 2 c ^ lj 2 ri
Bij = 1 means that literal lj of c has a conflict with cube ri of R
If lj is not dropped from c then c \ ri = is ensured
We only need to ensure that when we choose a set of literals of c
to delete (to expand it), the remaining literals have a conflict with
each of the cubes of R
TECHNO
OF LO
TE
GY
ITU
IAN INST
KH
ARAGPUR
IND

19 5 1
yog, km s kOflm^

Bij = 1 , lj 2 c ^ lj 2 ri
TECHNO
OF LO
TE
GY
ITU
IAN INST
KH
ARAGPUR
IND

19 5 1
yog, km s kOflm^

Bij = 1 , lj 2 c ^ lj 2 ri
TECHNO
OF LO
TE
GY
ITU
IAN INST
KH
ARAGPUR
IND

19 5 1
yog, km s kOflm^
Illustration of expansion wrt B c
Example
z
Let c = wxy

w x y z
x z 0 1 0 1
wx z 1 0 0 0
w y z 1 0 1 0
and z ensure conflicts with
Okay to drop x and y because w
cubes of R
Literals y and z can also be dropped as w
and x also ensure
conflicts with cubes of R

Cannot drop w OF
TECHNO
LO
TE
GY
ITU
IAN INST
KH
ARAGPUR
IND

19 5 1
yog, km s kOflm^
Illustration of expansion wrt B c
Example
z
Let c = wxy

w x y z
x z 0 1 0 1
wx z 1 0 0 0
w y z 1 0 1 0
and z ensure conflicts with
Okay to drop x and y because w
cubes of R
Literals y and z can also be dropped as w
and x also ensure
conflicts with cubes of R

Cannot drop w OF
TECHNO
LO
TE
GY
ITU
IAN INST
KH
ARAGPUR
IND

19 5 1
yog, km s kOflm^
Expand Literals to delete using blocking matrix
Deciding the set of literals to delete
First the blocking matrix helps us determine whether the cube has
enough literals to ensure that it does not exapand into R
We might like to delete maximum number of literals from c
Conversely, we would like to retain minimum number literals of c
Also,
1 the 1 entries of the retained literals indicate presence of a conflict
with a cube of R and
2 there should be a conflict with each cube of R
So we are are after a MCC of B c !
We retain the literals in the MCC and drop the rest
We might have other considerations for expanding a cube
An important objective of the expand operation is for a cube ci to
expand to a super cube to cover as many other cubes as possible TE
OF
TECHNO
LO
GY
ITU
IAN INST
KH
ARAGPUR
IND

19 5 1
yog, km s kOflm^
Also,
OF
TECHNO
LO
GY
ITU
IAN INST
KH
ARAGPUR
IND

19 5 1
yog, km s kOflm^
Also,
OF
TECHNO
LO
GY
ITU
IAN INST
KH
ARAGPUR
IND

19 5 1
yog, km s kOflm^
Also,
OF
TECHNO
LO
GY
ITU
IAN INST
KH
ARAGPUR
IND

19 5 1
yog, km s kOflm^
Also,
OF
TECHNO
LO
GY
ITU
IAN INST
KH
ARAGPUR
IND

19 5 1
yog, km s kOflm^
Deciding the set of literals to delete (contd.)
Example
Column cover of B c is shown below:
z
wxy
w x y z
x z 0 1 0 1
wx z 1 0 0 0
w y z 1 0 1 0
and z form a MCC
w
and z ; drop x and y
Retain w
z wrt R = fx z + wx z + w y z g
z is expanded to c = w
c = wxy
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Expand Expanding to form a supercube
Expanding to the smallest super cube of ci and cj

Definition (Smallest Super Cube)
The Smallest Super Cube s = SSC(cj ; ci ) of ci and cj , is the smallest
cube containing both ci and cj .
If ci has l and cj has l or then any SSC of ci cik cjk sk yk

and cj should be made independent of x,
0 0 0
x = supp(l )
0 1 0
Adjoining table indicates necesssary decisions 1 0 0
(yk = 0) for dropping literals for forming a super 1 1 1
cube 0 0
In the last column, yk = 0 if lk of ci is dropped, 1 0
and (dont care) otherwise (why?) 0
A dont care literal need not be dropped, 1
however, if dropped, does not affect formation of
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the super cube



0 0 0
x = supp(l )
0 1 0
cube 0 0
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the super cube



0 0 0
x = supp(l )
0 1 0
cube 0 0
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the super cube

Expanding to the smallest super cube

Example

d R = ab cd ; abcd
; abc
bcd ; abcd
F = a
bcd is shown
Blocking matrix for a
Minterms of F and R shown via the Karnaughs map
Super cubes formed to cover minterms of R (in the map) should
not trespass into minterms of R
ab
cd 00 01 11 10
abcd a b c d 00 R
ab cd 0 1 0 1 01 F R
abcd 1 0 0 0 10 F
11 F

Possible expansion decisions of abc d: y2 y3 or y3 y4 ,

corresponding to formation of ad (dropping b; c) or ab (dropping TE
OF
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Example

d R = ab cd ; abcd
; abc
bcd ; abcd
F = a
bcd is shown
ab
cd 00 01 11 10
abcd a b c d 00 R
ab cd 0 1 0 1 01 F R
abcd 1 0 0 0 10 F
11 F


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Example

d R = ab cd ; abcd
; abc
bcd ; abcd
F = a
bcd is shown
ab
cd 00 01 11 10
abcd a b c d 00 R
ab cd 0 1 0 1 01 F R
abcd 1 0 0 0 10 F
11 F


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c; d)
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Single cube expansion to cover other cubes
Let b(cj ; s) = 1 if expansion of cj to s is blocked by the blocking

matrix and 0, otherwise
cj 2 F , possible expansions to cover other cubes are
For each
Xj = sji jsji = SSC(cj ; ci ) ^ ci 2 F ^ ci 6= cj ^ b(cj ; sji ) = 0
PjF j
~j ) = k =1 dkj represent the decisions to drop
1
For cube cj let h(Y
literals of cj to get each super cube in Xj , attempting to cover the
remaining jF j 1 cubes of F
Example
Let c1 = a
bcd, c2 = abcd, d
bc
c3 = a

F = fc1 ; c2 ; c3 g and R = a
b cd ; abcd
d = SSC(c1 ; c2 ), ab = SSC(c1 ; c3 ) and X1 = fad ; abg
a
d11 = y2 y3 , d21 = y3 y4 and h(Y~1 ) = d11 + d21
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Single cube expansion to cover other cubes
Let b(cj ; s) = 1 if expansion of cj to s is blocked by the blocking

matrix and 0, otherwise
cj 2 F , possible expansions to cover other cubes are
For each
Xj = sji jsji = SSC(cj ; ci ) ^ ci 2 F ^ ci 6= cj ^ b(cj ; sji ) = 0
PjF j
~j ) = k =1 dkj represent the decisions to drop
1
For cube cj let h(Y
literals of cj to get each super cube in Xj , attempting to cover the
remaining jF j 1 cubes of F
Example
Let c1 = a
bcd, c2 = abcd, d
bc
c3 = a

F = fc1 ; c2 ; c3 g and R = a
b cd ; abcd
d = SSC(c1 ; c2 ), ab = SSC(c1 ; c3 ) and X1 = fad ; abg
a
d11 = y2 y3 , d21 = y3 y4 and h(Y~1 ) = d11 + d21
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Single cube expansion to cover other cubes (contd.)
~j ) is negative unate in Y~j

h(Y
Maximal expansion for a single cube to attain maximal coverage of other
cubes may be considered

' h(Y~j ) and Bc
c
C j
Consider the composite matrix c
B j , where C cj j is the
blocking matrix for cj
When a row from the upper part (C cj ) is chosen, the columns where 1s
are present (in the top part) are neutralised (1 ! 2 in the top part and
1 ! 0 in the bottom part)
A choice of a row of C cj that causes any row of B cj to become all 0s is
not permitted (to prevent encroachment into cubes of R)
Determine literals to be dropped (choosing rows from the top part) so
that none of the rows of B cj become all-zeroes and most of the rows of
C cj become free of ones TE
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Example
; abc

bcd ; abcd
F = a d ,
Both remaining cubes cannot
R= a bcd ; abcd , c = abcd
be covered by way of cube
Composite matrix for c: expansion of c
b c d
a
0 1 Composite matrix after
2 1 1 2
B
B C choosing top row:
B 2 2 1 1 C C b c d
a
B
B 0 1 0 1 C C 0 1
@ A 2 2 2 2
1 0 0 0 B
B C
B 2 2 2 1 C C
For the two possible B
B 0 0 0 1 C C
@ A
expansions, either expansion 1 0 0 0
covers one extra cube TE
OF
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Example
; abc

bcd ; abcd
F = a d ,
Both remaining cubes cannot
R= a bcd ; abcd , c = abcd
be covered by way of cube
Composite matrix for c: expansion of c
b c d
a
0 1 Composite matrix after
2 1 1 2
B
B C choosing top row:
B 2 2 1 1 C C b c d
a
B
B 0 1 0 1 C C 0 1
@ A 2 2 2 2
1 0 0 0 B
B C
B 2 2 2 1 C C
For the two possible B
B 0 0 0 1 C C
@ A
expansions, either expansion 1 0 0 0
covers one extra cube TE
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Note that check wrt B is not required for dropping literals for
individual rows of C, but needed for multiple rows
This is a type of column covering problem for B with the objective
to minimise coverage for C
This problem may be solved with greedy heuristics?
Note that expansion is commutative: if ci can expand to cover cj
and then ck , cj can also expand to cover ck and then cj
This property can be used to determine the expansion of ci to
cover maximum number of other cubes pseudocode ... ?
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Note that check wrt B is not required for dropping literals for
individual rows of C, but needed for multiple rows
This is a type of column covering problem for B with the objective
to minimise coverage for C
This problem may be solved with greedy heuristics?
Note that expansion is commutative: if ci can expand to cover cj
and then ck , cj can also expand to cover ck and then cj
This property can be used to determine the expansion of ci to
cover maximum number of other cubes pseudocode ... ?
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Reduce
Section outline
34 Reduce
Formulation
Reduce using Shannon cofactors
Supercube of complement
SCCC of unate cover
Recursive computation of SCCC
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Reduce Formulation
Reduce
Reducing a large cube

Given a cover F and c 2 F , find the smallest cube c 0 ; c 0 c such that
F n fc g [ fc 0 g is still a cover; c 0 is called the maximally reduced cube of
c
Reduce a prime to a (smaller) non-prime but still maintain cover

Reduction of cubes is order dependent
Aim is to get out of a local minimum (result of prime and
irredundant represent local minima)
Thereafter have a set of non-prime cubes in the future these can
again be expanded again possibly in different directions
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Reduce Formulation
Reduce (contd.)
F = fc1 ; c2 ; : : : ; ck g
F (i ) = (F + D )n fci g = fc1 ; c2 ; : : : ; ci 1 ; ci +1 ; : : : ; ck g + D
F (i ): a cover of all of r and minterms covered exclusively by ci .
(ci \ F (i )) is the set of points exclusively covered by ci (and not by
any other cj or D)
Reduced cube: ci0 : smallest cube containing (ci \ F (i ))
Thus, ci0 is the smallest cube containing the minterms of ci which
are not in F (i ). Therefore, c 0 = SSC(ci \ F (i ))
i
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Reduce Reduce using Shannon cofactors
Reduce using Shannon cofactors
We need to focus only inside ci do so using Shannon cofactors

Fci (i ): cover of minterms of ci excluding minterms of ci 2 f
covered exclusively by ci (but replicated in all cubes X where
supp(X ) = supp(ci ))
Fci (i ): cover of minterms of ci 2 f covered exclusively by ci (but
replicated in all cubes X where supp(X ) = supp(ci ))
Hence, ci0 = SSC(ci Fci (i )) = ci SSC(Fci (i )) = ci SCCC(Fci (i )),
SCCC smallest supercube containing complement
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Reduce Reduce using Shannon cofactors
Pseudocode for reduce
reduce(F, D) {
F order(F) // suitably order F
for (1 j jFj) do {
cj0 maxReduce(cj , F, D)

F F [ cj0 - cj
}
return F
}
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Reduce Supercube of complement
Supercube of the complement of a single cube
Example
c 0 1 2 2 2 b
a
c
1 2 2 2 2 a
2 0 2 2 2 b
In the a-plane, both polarities need to be covered while covering
b = ab + ab
b:
In the b-plane also, both polarities need to be covered while
covering a: a = ab + ab
As a result, SCCC(c ) needs to be the universal cube
SCCC(c ) = SSC(c) 2 2 2 2 2
For a cube c with at least 2 literals, SCCC(c ) is the universal cube TE

OF
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Example
c 0 1 2 2 2 b
a
c
1 2 2 2 2 a
2 0 2 2 2 b
b = ab + ab
b:
SCCC(c ) = SSC(c) 2 2 2 2 2

OF
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Example
c 0 1 2 2 2 b
a
c
1 2 2 2 2 a
2 0 2 2 2 b
b = ab + ab
b:
SCCC(c ) = SSC(c) 2 2 2 2 2

OF
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Reduce SCCC of unate cover
SCCC of cubes of a unate cover

SCCC of single cube with at least 2 literals is the tautology
P
Consider SCCC( j
j li1 lij ) = SSC(Qj (lij + : : : + lij ))
j 1 j
Q
Consider the SOP expansion of j (lij + : : : + lij ) at least 2 literals/sum
1 j
Example
U = ab + bc
+ b)(b + c)) =
SCCC(U ) = SSC(ab + bc ) = SSC((a
SSC(ab + ac + b + bc)
All instances of each variable have the same polarity because the
cover is unate
In the SOP, for each literal lj , there is a cube where it is absent (dont
care)
Q
Therefore, SSC( j (li + : : : + li ) needs to be the universal cube
TECHNO
OF LO
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IAN INST
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1 j
SCCC of cubes of a unate cover

SCCC of single cube with at least 2 literals is the tautology
P
Consider SCCC( j
j li1 lij ) = SSC(Qj (lij + : : : + lij ))
j 1 j
Q
Consider the SOP expansion of j (lij + : : : + lij ) at least 2 literals/sum
1 j
Example
U = ab + bc
+ b)(b + c)) =
SCCC(U ) = SSC(ab + bc ) = SSC((a
SSC(ab + ac + b + bc)
All instances of each variable have the same polarity because the
cover is unate
In the SOP, for each literal lj , there is a cube where it is absent (dont
care)
Q
Therefore, SSC( j (li + : : : + li ) needs to be the universal cube
TECHNO
OF LO
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ITU
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IAN INST
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1 j
SCCC of unate cover having single literal cubes
Example
thus f = a(b + c)d, and SCCC(f ) ad
Let f = a + bc + d,
SCCC(l1 + : : : + lk + c1 + : : : + cm )
=SSC(l1 : : : lk c1 : : : cm )
= l1 : : : lk
Each cube cj has at least two literals

Q
Note that SCCC of j cj is the universal cube
TECHNO
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Rules for computing SCCC of a unate cover
If all the cubes in the unate cover C have at least two literals, then
SCCC(C ) 1
SCCC(C ) = , if there is a row of all 2s in U
Let 8= SCCC(C )
< lj ; if there is a singleton row having 0 in col j (cube is lj )
j = lj ; if there is a singleton row having 1 in col j (cube is lj )
:
2; otherwise
Computation of SCCC for a unate cover is easy!
TECHNO
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Rules for computing SCCC of a unate cover
If all the cubes in the unate cover C have at least two literals, then
SCCC(C ) 1
SCCC(C ) = , if there is a row of all 2s in U
Let 8= SCCC(C )
< lj ; if there is a singleton row having 0 in col j (cube is lj )
j = lj ; if there is a singleton row having 1 in col j (cube is lj )
:
2; otherwise
Computation of SCCC for a unate cover is easy!
TECHNO
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Reduce Recursive computation of SCCC
Recursive SCCC computation of non-unate cover
If F is binate in xp , then SCCC(F ) = SSC(xp Fxp + xp Fxp )

Note the outer application of SSC, it is not Fxp or Fxp we are after
SCCC(F ) =SSC(xp SCCC(Fxp ) + xp SCCC(Fxp )) =
SSC(xp c1 + xp c2 ) = , where c1 = SCCC(Fxp ), c2 = SCCC(Fxp )
and where = li1 li2 : : : lik
9j ; li
j
() c2 =
= xp
9j ; li
j
() c1 =
= xp
li = xq _ li = xq ; p =
j j
6 q ; () c1 li ^ c2 li (c1; c2 have li )
j j j
If c1 ^ c2 =6 , then 6 9j ; li = xp _ li = xp (DC wrt xp )

j j
6 q, is a DC in c1 or c2, then xq is also a DC in

If xq ; p =
6 q), then xq is also a
If xq is in c1 and xq is in c2 , or vice-versa (p =
DC in TE
OF
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9j ; li
j
() c2 =
= xp
9j ; li
j
() c1 =
= xp
li = xq _ li = xq ; p =
j j
j j j

j j

If xq ; p =
DC in TE
OF
TECHNO
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GY
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IND

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9j ; li
j
() c2 =
= xp
9j ; li
j
() c1 =
= xp
li = xq _ li = xq ; p =
j j
j j j

j j

If xq ; p =
DC in TE
OF
TECHNO
LO
GY
ITU
IAN INST
KH
ARAGPUR
IND

19 5 1
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9j ; li
j
() c2 =
= xp
9j ; li
j
() c1 =
= xp
li = xq _ li = xq ; p =
j j
j j j

j j

If xq ; p =
DC in TE
OF
TECHNO
LO
GY
ITU
IAN INST
KH
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IND

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9j ; li
j
() c2 =
= xp
9j ; li
j
() c1 =
= xp
li = xq _ li = xq ; p =
j j
j j j

j j

If xq ; p =
DC in TE
OF
TECHNO
LO
GY
ITU
IAN INST
KH
ARAGPUR
IND

19 5 1
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9j ; li
j
() c2 =
= xp
9j ; li
j
() c1 =
= xp
li = xq _ li = xq ; p =
j j
j j j

j j

If xq ; p =
DC in TE
OF
TECHNO
LO
GY
ITU
IAN INST
KH
ARAGPUR
IND

19 5 1
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9j ; li
j
() c2 =
= xp
9j ; li
j
() c1 =
= xp
li = xq _ li = xq ; p =
j j
j j j

j j

If xq ; p =
DC in TE
OF
TECHNO
LO
GY
ITU
IAN INST
KH
ARAGPUR
IND

19 5 1
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9j ; li
j
() c2 =
= xp
9j ; li
j
() c1 =
= xp
li = xq _ li = xq ; p =
j j
j j j

j j

If xq ; p =
DC in TE
OF
TECHNO
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IND

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Lastgasp
Section outline
35 Lastgasp
Directional nature of reduce
Maximal reduce
Formulation
The Espresso algorithm
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Lastgasp Directional nature of reduce
Example
Original cover F =
x2 x3 + x2 x3 + x1 x2 + x1 x2
Possible Reduction x2 x3 ! x1 x2 x3
and x2 x3 ! x1 x2 x3
x2
Another application of
Expand will not improve
coverage
x3
Another Reduction x2 x3 ! x1 x2 x3 x1
Expand will lead to a
better coverage TE
OF
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Example
Original cover F =
x2 x3 + x2 x3 + x1 x2 + x1 x2
x2
coverage
x3
better coverage TE
OF
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Example
Original cover F =
x2 x3 + x2 x3 + x1 x2 + x1 x2
x2
coverage
x3
better coverage TE
OF
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Lastgasp Maximal reduce
Maximal reduce
Given a cover F = fc1 ; c2 ; : : : ; cm g
Let ciM = ci \ SCCC(Fci (i )), for all cubes (8i)

Now consider the set E = c1M ; c2M ; : : : ; cm
M
E may not be a cover, but all cubes in it are maximally reduced

The reduction is direction independent
All cubes are reduced as if each were the first one to be reduced
reduce(F, D) {
reduceMaximal(F, D) {
F order(F)
G
for (1 j jFj) do {
// suitably order F
for (1 j jFj) do {
cj0
cj0
maxReduce(cj , F, D)

G [ cj0
maxReduce(cj , F, D)

F [ cj0 - cj
G
F
}
}
return G OF
TECHNO
return F
LO
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} 19 5 1
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}
Example of maximal reduce
Example
Original cover F = x2 x3 + x2 x3 + x2

x1 x2 + x1 x2
After Maximal Reduce x1 x2 x3
and x1 x2 x3 remain x3
x1
uncovered
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Example of maximal reduce
Example
Original cover F = x2 x3 + x2 x3 + x2

x1 x2 + x1 x2
After Maximal Reduce x1 x2 x3
and x1 x2 x3 remain x3
x1
uncovered
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Lastgasp Formulation
Lastgasp
lastgasp(F, D, R) {
G = reduceMaximal(F, D);
E = expandX(G, R); // all possible expansions
F = irredundant(F [ E, D);
}
Cubes in the minimally reduced set of cubes G are expanded to
prime cubes in all possible ways to form a set of cubes (E)
The cover F is augmented with E
An irredundant cover of F [ E is retained
Lastgasp does not guarantee a reduction of the cover size
Interesting variation was suggested by Goldberg (c.f. Goldbergs
Theorem)
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Lastgasp (contd.)
Example
Consider a Boolean function and a feasible cover, as shown below
After maximal reduce, only the circled nodes remain in the cover
The supercube of these two nodes does not help to reduce the overall
number of cubes
The original cover of this example was optimal, anyway
x2
x2
x2 x2 x2
x3
x1 x3
x3 x3 x1 x3
x1 x1 1 0 1 x1
1 2 2 2 1 2 2 2 1
0 1 1
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Lastgasp (contd.)
Example
number of cubes
x2
x2
x2 x2 x2
x3
x1 x3
x3 x3 x1 x3
x1 x1 1 0 1 x1
1 2 2 2 1 2 2 2 1
0 1 1
TECHNO
OF LO
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GY
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IAN INST
KH
ARAGPUR
IND

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Lastgasp (contd.)
Example
number of cubes
x2
x2
x2 x2 x2
x3
x1 x3
x3 x3 x1 x3
x1 x1 1 0 1 x1
1 2 2 2 1 2 2 2 1
0 1 1
TECHNO
OF LO
TE
GY
ITU
IAN INST
KH
ARAGPUR
IND

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Lastgasp The Espresso algorithm
Espresso
espresso(F, D) { // called with ON and DC covers
R = complement(F [ D); // OFF cover computed
F = irredundant(expand(F, R), D);
E = essentialPrimes(F, D);
F = F - E; D = D [ E; // lighten F
repeat {
2 = cost(F);
repeat {
1 = jFj;
F = reduce(F, D); // F might not cover
F = irredundant(expand(F, R), D);
} until (jFj 1 );
F = lastgasp(F, D, R);
} until (cost(F) 2 );
F = F [ E; D = D - E; // reconsititute F
F = make_sparse(F, D, R); // for PLA design TE
OF
TECHNO
LO
GY
ITU
IAN INST
KH
ARAGPUR
}
IND

19 5 1
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BDDs
Section outline
36 BDDs
BDD reduction
BDD operations
Implementation aspects
Common ROBDD operations
More general representation
BDDs for relations
ZDDs
TECHNO
OF LO
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GY
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IAN INST
KH
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IND

19 5 1
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BDDs
Binary Decision Diagrams

x1
1
x1 x2 x3 f 0
0 0 0 0 x2 x2
0 0 1 0
0 1 0 0 0 1 0 1
0 1 1 1 x3 x3 x3 x3
1 0 0 0
1 0 1 1 0 1 0 1 0 1 0 1
1 1 0 0
0 0 0 1 0 1 0 1
1 1 1 1
Diagram is not reduced
Diagram is ordered
OBDD is a (poor) canonical representation TE
OF
TECHNO
LO
GY
ITU
IAN INST
KH
ARAGPUR
IND

19 5 1
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BDDs BDD reduction
Reduction of Binary Decision Diagrams
Remove Duplicate Terminals Eliminate all but one terminal vertex

with a given label and redirect all arcs into the eliminated
vertices to the remaining one.
Remove Duplicate Nonterminals If nonterminal vertices u and v
have var(u) = var(v ), lo(u) = lo(v ), and hi(u) = hi(v ), then
eliminate one of the two vertices and redirect all incoming
arcs to the other vertex.
Remove Redundant Tests If nonterminal vertex v has lo(v ) = hi(v ),
then eliminate v and redirect all incoming arcs to lo(v ).
TECHNO
OF LO
TE
GY
ITU
IAN INST
KH
ARAGPUR
IND

19 5 1
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BDDs BDD reduction
Reduction of Binary Decision Diagrams (contd.)
x1
1
0
x2 x2
0 1 0 1
x3 x3 x3 x3
0 1 0 1 0 1 0 1
0 0 0 1 0 1 0 1
Original OBDD
TECHNO
OF LO
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GY
ITU
IAN INST
KH
ARAGPUR
IND

19 5 1
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BDDs BDD reduction
x1
1
0
x2 x2
0 1 0 1
x3 x3 x3 x3
0 1 0 1 0 10 1
0 1
Result of removing duplicate terminals

TECHNO
OF LO
TE
GY
ITU
IAN INST
KH
ARAGPUR
IND

19 5 1
yog, km s kOflm^
BDDs BDD reduction
x1
1
0
x2 x2
1 01
0
x3 x3
0 1
0 1
0 1
Result of removing duplicate non-terminals

TECHNO
OF LO
TE
GY
ITU
IAN INST
KH
ARAGPUR
IND

19 5 1
yog, km s kOflm^
BDDs BDD reduction
x1
0
x2 1
1
0 x3
0 1
0 1
Result of removing redundant tests

TECHNO
OF LO
TE
GY
ITU
IAN INST
KH
ARAGPUR
IND

19 5 1
yog, km s kOflm^
BDDs BDD reduction
This is a ROBDD variable ordering is: x1 ; x2 ; x3

Variable ordering can have a profound effect on the size of the
ROBDD
A BDD is a compressed Shannon co-factoring tree
TECHNO
OF LO
TE
GY
ITU
IAN INST
KH
ARAGPUR
IND

19 5 1
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BDDs BDD reduction
ROBDD complexity for common function classes
Function Class Complexity

Best Worst
Symmetric linear quadratic
Integer Addition (any bit) linear exponential
Integer Multiplication (middle bits) exponential exponential
TECHNO
OF LO
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GY
ITU
IAN INST
KH
ARAGPUR
IND

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BDDs BDD operations
Complementation of f
x1
0
x2 1
1
0 x3
0 1
0 1
f is to be complemented
Result of complementation only the terminal values of 0 and 1
need to be interchanged TE
OF
TECHNO
LO
GY
ITU
IAN INST
KH
ARAGPUR
IND

19 5 1
yog, km s kOflm^
BDDs BDD operations
Complementation of f
x1
0
x2 1
1
0 x3
0 1
1 0
f is to be complemented
Result of complementation only the terminal values of 0 and 1
need to be interchanged TE
OF
TECHNO
LO
GY
ITU
IAN INST
KH
ARAGPUR
IND

19 5 1
yog, km s kOflm^
BDDs BDD operations
Restriction of f
Restrict f so that x = k, denoted as: f jx k

It has several uses, such as: Shannon expansion, Composition,
where a function g is substituted for some variable x, Existential
quantification and Universal quantification
TECHNO
OF LO
TE
GY
ITU
IAN INST
KH
ARAGPUR
IND

19 5 1
yog, km s kOflm^
BDDs BDD operations
Restriction of f
Restrict f so that x = k, denoted as: f jx k

It has several uses, such as: Shannon expansion, Composition,
where a function g is substituted for some variable x, Existential
quantification and Universal quantification
TECHNO
OF LO
TE
GY
ITU
IAN INST
KH
ARAGPUR
IND

19 5 1
yog, km s kOflm^
BDDs BDD operations
Restriction of f on Its ROBDD representation

x1
0
x2 1
1
0 x3
0 1
0 1
ROBDD for f (x1 ; x2 ; x3 ), to be restricted as f jx1 1

Branch for x1 = 0 is no longer needed, may be dropped, leading
to redudancies
TECHNO
OF LO
TE
GY
ITU
IAN INST
KH
Result of further reduction to remove redundancies
ARAGPUR
IND

19 5 1
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BDDs BDD operations

x1
x2 1
1
0 x3
0 1
0 1

to redudancies
TECHNO
OF LO
TE
GY
ITU
IAN INST
KH
ARAGPUR
IND

19 5 1
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BDDs BDD operations
x3
0 1
0 1

to redudancies
TECHNO
OF LO
TE
GY
ITU
IAN INST
KH
ARAGPUR
IND

19 5 1
yog, km s kOflm^
BDDs BDD operations
Restriction of f on its ROBDD representation

x1
0
x2 1
1
0 x3
0 1
0 1

to redudancies
TECHNO
OF LO
TE
GY
ITU
IAN INST
KH
ARAGPUR
IND

19 5 1
yog, km s kOflm^
BDDs BDD operations

x1
0
x2 1
0 x3
0 1
0 1

to redudancies
TECHNO
OF LO
TE
GY
ITU
IAN INST
KH
ARAGPUR
IND

19 5 1
yog, km s kOflm^
BDDs BDD operations

x1
x3
0 1
0 1

to redudancies
TECHNO
OF LO
TE
GY
ITU
IAN INST
KH
ARAGPUR
IND

19 5 1
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BDDs BDD operations
Some Uses of Restriction
Shannon expansion:
f = x f jx 0 + x f jx 1
Existential quantification:
9x f = f jx 0 + f jx 1
Universal quantification:
8x f = f jx 0 f jx 1
Composition, where a function g is substituted for some variable x:
f jx g = g f jx 0 + g f jx 1 TE
OF
TECHNO
LO
GY
ITU
IAN INST
KH
ARAGPUR
IND

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yog, km s kOflm^
BDDs BDD operations
Shannon expansion:
f = x f jx 0 + x f jx 1
9x f = f jx 0 + f jx 1
OF
TECHNO
LO
GY
ITU
IAN INST
KH
ARAGPUR
IND

19 5 1
yog, km s kOflm^
BDDs BDD operations
Shannon expansion:
f = x f jx 0 + x f jx 1
9x f = f jx 0 + f jx 1
OF
TECHNO
LO
GY
ITU
IAN INST
KH
ARAGPUR
IND

19 5 1
yog, km s kOflm^
BDDs BDD operations
Shannon expansion:
f = x f jx 0 + x f jx 1
9x f = f jx 0 + f jx 1
OF
TECHNO
LO
GY
ITU
IAN INST
KH
ARAGPUR
IND

19 5 1
yog, km s kOflm^
BDDs BDD operations
Composition
Theorem
f jx g = g f jx 0 + g f jx 1
Proof.
Here g is to be substituted for x in f
Let the support of g be xj1 ; xj2 ; : : :
When g is 1 for some truth assignment of xj1 ; xj2 ; : : :, f should be
restricted to x 1, hence we get the clause g f jx 1
Essentially means restrict f such that x 1 when g is 1
Similarly, when g is 0 for some truth assignment of xj1 ; xj2 ; : : :, f
should be restricted such that x 0, hence we get the clause
f jx 0 , restricting f to 0 when g is 0
g
TECHNO
OF LO
TE
GY
ITU
IAN INST
KH
ARAGPUR
IND

19 5 1
yog, km s kOflm^
BDDs BDD operations
Composition
Theorem
f jx g = g f jx 0 + g f jx 1
Proof.
Here g is to be substituted for x in f
Let the support of g be xj1 ; xj2 ; : : :
When g is 1 for some truth assignment of xj1 ; xj2 ; : : :, f should be
restricted to x 1, hence we get the clause g f jx 1
Essentially means restrict f such that x 1 when g is 1
Similarly, when g is 0 for some truth assignment of xj1 ; xj2 ; : : :, f
should be restricted such that x 0, hence we get the clause
f jx 0 , restricting f to 0 when g is 0
g
TECHNO
OF LO
TE
GY
ITU
IAN INST
KH
ARAGPUR
IND

19 5 1
yog, km s kOflm^
BDDs BDD operations
Boolean operations on ROBDDs
Already seen how complementation is performed

What about other operations f _ g, f ^ g, f g, etc.?
Boolean difference @@xf = fx fx
If-then-else: ITE(v ; g ; h) = v :g + v h hhv ; g ; hii building block
of BDDs
f hopi g = x (f jx 0 hopi g jx 0) + x (f jx 1 hopi g jx 1)
When leaf nodes are reached, value of operation is determined
using the truth table of hopi
TECHNO
OF LO
TE
GY
ITU
IAN INST
KH
ARAGPUR
IND

19 5 1
yog, km s kOflm^
BDDs BDD operations
Boolean operations on ROBDDs
Already seen how complementation is performed

What about other operations f _ g, f ^ g, f g, etc.?
Boolean difference @@xf = fx fx
If-then-else: ITE(v ; g ; h) = v :g + v h hhv ; g ; hii building block
of BDDs
f hopi g = x (f jx 0 hopi g jx 0) + x (f jx 1 hopi g jx 1)
When leaf nodes are reached, value of operation is determined
using the truth table of hopi
TECHNO
OF LO
TE
GY
ITU
IAN INST
KH
ARAGPUR
IND

19 5 1
yog, km s kOflm^
BDDs BDD operations
Shared BDDs
Multiple functions can be represented as a multi-rooted DAG,

sharing common nodes
Each root and its descendants form an ROBDD to represent a
particular function
A global variable ordering is required
Good variable ordering for one function could be bad for another
TECHNO
OF LO
TE
GY
ITU
IAN INST
KH
ARAGPUR
IND

19 5 1
yog, km s kOflm^
BDDs Implementation aspects
ITE Operator for 2-input Functions
Table Subset Expr Equiv Form

0000 0 0 0
0001 AND(f ; g) fg ITE(f ; g ; 0)
0010 f >g fg ; 0)
ITE(f ; g
0011 f f f
0100 f <g f g ITE(f ; 0; g )
0101 g g g
0110 XOR(f ; g)
f g ; g )
ITE(f ; g
f +g ITE(f ; 1; g ) represent
OR(f ; g)
; f g ; f g; fg
The bit patterns
subsets of f g
0111
1000 NOR(f ; g) f +g ITE(f ; 0; g)
1001 XNOR(f ; g)
f g )
ITE(f ; g ; g
1010 NOT(g)
g ITE(g ; 0; 1)
1011 f g f +g ITE(f ; 1; g)
1100 NOT(f ) f ITE(f ; 0; 1)
1101 f g f + g ITE(f ; g ; 1)
1110 NAND(f ; g) fg ; 1)
ITE(f ; g
1111 1 1 1
TECHNO
OF LO
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IAN INST
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IND

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Cache for Construction of BDDs

The primitive item of storage is R = v ; Rg ; Rh =
ITE(v ; Rg ; Rh )

Before a node R = v ; Rg ; Rh = ITE(v ; Rg ; Rh ) ite(v ; g ; h)
is added to BDD data base, it is looked up in the unique-table
If it is there, then existing pointer to node is used to represent the
logic function
Otherwise, a new node is added to the unique-table and the new
pointer returned
Unique-table allows single multi-rooted DAG to represent all users
functions
Construction is done recursively
TECHNO
OF LO
TE
GY
ITU
IAN INST
KH
ARAGPUR
IND

19 5 1
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Recursive ITE based ROBDD construction

Let v be the top most variable in the ordering
ite(f ; g ; h) = fg + f h
= v (fg + f h)v + v (fg + f h)v
= v (fv gv + fv hv ) + v (fv gv + fv hv )
= ITE(v ; ite(fv ; gv ; hv ); ite(fv ; gv ; hv ))
R = ite(Rf ; Rg ; Rh ) hhv ; R1 ; R2 ii ; where
R1 = ite(fv ; gv ; hv )
R2 = ite(fv ; gv ; hv )
Base cases
ite(f ; g ; g ) = g ite(Rf ; Rg ; Rg ) = Rg
ite(0; f ; g ) = g ite(0; Rf ; Rg ) = Rg
ite(1; f ; g ) = f ite(1; Rf ; Rg ) = Rf
TECHNO
OF LO
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GY
ITU
IAN INST
KH
ARAGPUR
IND

19 5 1
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BDDs Common ROBDD operations
Common ROBDD operations
Operation Complexity Description

Reduce O (jGj) G is reduced to canonical
form
Apply O (jG1 jjG2 j) Any binary Boolean operator
Compose O (jG1 j2 jG2 j) Substitute g for x
Satisfy-one O (n) Find one satisfying assign-
ment of the n variables
Restrict O (jGj) Restrict a variable to a con-
stant
TECHNO
OF LO
TE
GY
ITU
IAN INST
KH
ARAGPUR
IND

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Complement Edges
G
G

0 1 0 1
available redundant
ROBDD for both G and G
Share with complement edge
Share leaf also with complement edge
TECHNO
OF LO
TE
GY
ITU
IAN INST
KH
ARAGPUR
IND

19 5 1
yog, km s kOflm^
Complement Edges

G
G
G G

0 1 0 1 0 1
available redundant
TECHNO
OF LO
TE
GY
ITU
IAN INST
KH
ARAGPUR
IND

19 5 1
yog, km s kOflm^
Complement Edges

G
G
G G

0 1 0 1 1
available redundant
TECHNO
OF LO
TE
GY
ITU
IAN INST
KH
ARAGPUR
IND

19 5 1
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Equivalences Arising from Complement Edges

(1/4)
v v
vf + v g = vf + v g = vf v g
= (v + f ) (v g ) = v g + v f + f g
= v g + v f + (v + v )f g = v (g + f g ) + v (f + f g )
= v (g (1 + f )) + v (f (1 + g )) = v g + v f = v f + v g
TECHNO
OF LO
TE
GY
ITU
IAN INST
KH
Preference is given to the left equivalent form so that the then leg has
ARAGPUR
IND

19 5 1
yog, km s kOflm^
no complement edge

(2/4)
v v
=) vf + v g = v f + v g
vf + v g = v f + v g
no complement edge TE
OF
TECHNO
LO
GY
ITU
IAN INST
KH
ARAGPUR
IND

19 5 1
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(3/4)
v v
=) vf + v g = v f + v g
OF
TECHNO
LO
GY
ITU
IAN INST
KH
ARAGPUR
IND

19 5 1
yog, km s kOflm^

(4/4)
v v
=) vf + v g = v f + v g
OF
TECHNO
LO
GY
ITU
IAN INST
KH
ARAGPUR
IND

19 5 1
yog, km s kOflm^
BDDs More general representation
Representing non-Binary Domains and Ranges
Example
t 0 1 X +t 0 1 X
0 0 0 0 0 0 1 X
1 0 1 X 1 1 1 1
X 0 X X X X 1 X
Ternary extension of AND Ternary extension of OR

:t
0 1
1 0
X X
Ternary extension of NOT TE

OF
TECHNO
LO
GY
ITU
IAN INST
KH
ARAGPUR
IND

19 5 1
yog, km s kOflm^
Representing non-Binary Domains and Ranges
Example
t 0 1 X +t 0 1 X
0 0 0 0 0 0 1 X
1 0 1 X 1 1 1 1
X 0 X X X X 1 X
Ternary extension of AND Ternary extension of OR

:t
0 1
1 0
X X
Ternary extension of NOT TE

OF
TECHNO
LO
GY
ITU
IAN INST
KH
ARAGPUR
IND

19 5 1
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Non-Binary Domains and Ranges (contd.)
Necessary to encode elements of domain using multiple bits

If the domain has N elements, then lg N bits will be needed
Example (contd.)
For the encoding
(0) = h0; 1i ; (1) = h1; 0i ; and (X ) = h1; 1i
the extended operations can be implemented as follows:
ha1; a0i t hb1; b0i = ha1 b1; a0 + b0i

ha1; a0i +t hb1; b0i = ha1 + b1; a0 b0i
: ha1; a0i = ha0; a1i TE
OF
TECHNO
LO
GY
ITU
IAN INST
KH
ARAGPUR
IND

19 5 1
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Formalisation of the Representation of non-Binary

Domains and Ranges
Consider a finite set of elements A, where jAj = N

We can encode an element of A as a vector of n binary values, where
n = lg N This encoding is denoted by a function : A ! f0; 1g
n
Let i (a) denote the i th element in this encoding

A function mapping elements in A to elements in A, f : A ! A is
represented as a vector of n Boolean functions ~f , where each
fi : f0; 1g ! f0; 1g is defined as:
n
fi ( (a)) = i (f (a))
The COSMOS symbolic simulator [Cho and Bryant 1989] uses ROBDDs
to compute the behavior of a transistor circuit symbolically
TECHNO
OF LO
TE
GY
ITU
IAN INST
KH
ARAGPUR
IND

19 5 1
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Domains and Ranges

n

n
fi ( (a)) = i (f (a))
TECHNO
OF LO
TE
GY
ITU
IAN INST
KH
ARAGPUR
IND

19 5 1
yog, km s kOflm^

Domains and Ranges

n

n
fi ( (a)) = i (f (a))
TECHNO
OF LO
TE
GY
ITU
IAN INST
KH
ARAGPUR
IND

19 5 1
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Representation of Sets
Given an encoding of the elements of a set A, we can represent

and manipulate its subsets using characteristic functions
n = lg jAj bits are required to encode the elements
A set S A is denoted by the Boolean function
S (~x ) : f0; 1gn ! f0; 1g
TECHNO
OF LO
TE
GY
ITU
IAN INST
KH
ARAGPUR
IND

19 5 1
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Representation of Sets
Example (A characteristic function and its ROBDD)
The set S has eight elements e1 ; : : : ; e8
encoded using three bits.
The table below shows the encoding and
also the charactersistic function S (~x ) de- x1
fined on the encoding.
element x1 x2 x3 S (~x ) 0
e1 0 0 0 0 x2 1
e2 0 0 1 0 1
e3 0 1 0 0
e4 0 1 1 1 0 x3
e5 1 0 0 0
e6 1 0 1 1 0 1
e7 1 1 0 0
0 1 TE
OF
TECHNO
LO
GY
ITU
IAN INST
KH
e8 1 1 1 1
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IND

19 5 1
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Operations on Sets
Empty Set = 0
Set Union (S [T ) = S + T
Set Intersection (S \T ) = S T
Set Difference (S T ) = S T
The right hand side represents usual operations that can be performed
on ROBDDs
TECHNO
OF LO
TE
GY
ITU
IAN INST
KH
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IND

19 5 1
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BDDs BDDs for relations
Representation of Relations
A k -ary relation can be defined as a set of ordered k -tuples

Also represent and manipulate relations using characteristic
functions represented as ROBDDs
A binary relation R A A is denoted by the Boolean function fR
corresponding to the characteristic function R
If each element of A is encoded in n bits, then each tuple of R is
encoded in 2n bits
The basic scheme for constructing the characteristic function is as
tuple x1;1 : : : x1;n x2;1 : : : x2;n fR = R
follows: ei1 ej1 xi1 ;1 : : : xi1 ;n xj1 ;1 : : : xj1 ;n 0/1
:::
ROBDD corresponding to this characteristic function is
constructed TE
OF
TECHNO
LO
GY
ITU
IAN INST
KH
ARAGPUR
IND

19 5 1
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encoded in 2n bits
tuple x1;1 : : : x1;n x2;1 : : : x2;n fR = R
:::
constructed TE
OF
TECHNO
LO
GY
ITU
IAN INST
KH
ARAGPUR
IND

19 5 1
yog, km s kOflm^

encoded in 2n bits
tuple x1;1 : : : x1;n x2;1 : : : x2;n fR = R
:::
constructed TE
OF
TECHNO
LO
GY
ITU
IAN INST
KH
ARAGPUR
IND

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yog, km s kOflm^
Representation of Relations (contd.)
Composition of relations R and S:
(RS) = (9~z )R (~x ; ~z ) S (~z ; ~y )

Since ~z = hz1 ; : : : ; zn i,
(RS) = (9z1 ; : : : ; zn )R (~x ; hz1 ; : : : ; zn i) S (hz1 ; : : : ; zn i ; ~y )

= (9z2 ; : : : ; zn ) [
R (~x ; hz1 ; : : : ; zn i)jz1 0 S (hz1 ; : : : ; zn i ; ~y )jz1 0
+ R (~x ; hz1 ; : : : ; zn i)jz1 1 S (hz1 ; : : : ; zn i ; ~y )jz1 1 ]
= :::
TECHNO
OF LO
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GY
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IAN INST
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IND

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Transitive Closure of a Relation
If R is the characteristic function of R, then that of the transitive

closure is represented as R
R is computed as the fixed point of the sequence R0 = I,
Ri +1 = I [ R Ri , where I denotes the identity relation
Termination is determine by equivalence testing of ROBDDs as
Ri 1 = Ri in at most N 1 iterations, where N = jAj
Faster convergence is achieved using iterative squaring as:
R0 = I [ R, Ri +1 = Ri [ Ri , reducing the maximum number of
iterations to lg N [Burch et al 1990]
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A m/c that accepts strings over f0; 1g ending in 1

Example
0 1 1 x1;1 x1;2 x2;1 x2;2

0 1 0 1 1 1
1 1 1 1
0
1 1 1 0
0 0 0 0
0 0 0 1
1 0 0 0
1 0 0 1
Moore m/c representing recogniser, not a pure relation
Result of input non-determinism on left state
Result of input non-determinism on right state
Transitions between input capturing states a pure relation TE
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Tuples for which R (~x ) = 1, for other tuples R (~x ) = 0

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Example
0 1 1 x1;1 x1;2 x2;1 x2;2

01 1 0 1 1 1
1 1 1 1
0
1 1 1 0
0 0 0 0
0 0 0 1
00
1 0 0 0
1 0 0 1
OF
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Example
0 1 1 x1;1 x1;2 x2;1 x2;2

01 11 0 1 1 1
1 1 1 1
0
1 1 1 0
0 0 0 0
0 0 0 1
00 10
1 0 0 0
1 0 0 1
OF
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Example
0 1 1 x1;1 x1;2 x2;1 x2;2

01 11 0 1 1 1
1 1 1 1
0
1 1 1 0
0 0 0 0
0 0 0 1
00 10
1 0 0 0
1 0 0 1
OF
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Representation of Subsets
Example
Consider the following subsets

ffa; bg ; fa; c g ; fc gg of the set
fa; b; c g.
These subsets could be a
1
captured by the function 0
+ abc
F = abc + abc b b
0 1
The ROBDD for this function is 0
as show 1 c c
1
The starred nodes are 0 1 0
unwanted their then edge
goes to 0 0 1
Now number of levels equals TE
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BDDs ZDDs
Zero Supressed BDDs (ZDD)
Example
BDD can be reduced by

dropping the unwanted a
1
nodes at the cost of not 0
dropping redundant tests b b
0 1
Redundant non-terminals are 0
dropped 1 c c
Redundant nodes are merged 1
0 1 0
Unwanted nodes are dropped
0 1
Result of zero-suppressing
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BDDs ZDDs
Zero Supressed BDDs (ZDD)
Example
BDD can be reduced by

dropping the unwanted a
1
nodes at the cost of not
dropping redundant tests 0 b
Redundant non-terminals are 0
dropped c 1
Redundant nodes are merged 1
0
Unwanted nodes are dropped
0 1
Result of zero-suppressing
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BDDs ZDDs
ZDD for F = ab + cd
Example
a
1
0
b b
0 1 1
0
c c
1 0 1
1 d d
1
0 1
0
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0 1

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BDDs ZDDs
ZDD for F = ab + cd
Example
a
1
0
b b
1
0 1 0 c
0 1
d d
1
0 1
0
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0 1

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BDDs ZDDs
ZDD Representation of Cube Covers
Two variables are used for each primary input: one of them stands
for the positive literal and another for the negative literal
The minterm has those variables in the positive polarity that
correspond to literals present in the cube and those variables in
the negative polarity that correspond to literals missing in the cube
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BDDs ZDDs
Example of ZDD Representation of Cube Covers
Example
a1
1
F = ab + cd 0 b1
Eight variables are used:
a1 ; a0 , b1 ; b0 , c1 ; c0 , d1 ; d0 c1
Characteristic function is: 1
0 1
a1 a0 b1 b0 c1 c0 d1 d0 +
0
a1 a0 b1 b0 c1 c0 d1 d0 d1
1
0
0 1
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Part VII
Multi-level logic synthesis
37 Introduction to multi-level logic synthesis
38 Algebraic methods for multi-level optimisation
39 Restructuring Boolean networks
40 Division
41 Kernels and co-kernels TE

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Introduction to multi-level logic synthesis
Section outline
37 Introduction to multi-level logic synthesis

PLA v/s multi-level
Optimisation criteria
Boolean network
Manipulation of Boolean Networks
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Introduction to multi-level logic synthesis PLA v/s multi-level
PLA v/s multi-level
PLA
Multi-level
control logic
constrained layout all logic
highly automatic general (e.g. standard cell, FPGAs)
technology automatic
independent partially technology independent
very predictable very hard to predict
addressed by 2L 2L logic optimisation not enough
logic optimisation
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Introduction to multi-level logic synthesis PLA v/s multi-level
PLA v/s multi-level
PLA
Multi-level
control logic
constrained layout all logic
highly automatic general (e.g. standard cell, FPGAs)
technology automatic
independent partially technology independent
very predictable very hard to predict
addressed by 2L 2L logic optimisation not enough
logic optimisation
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Introduction to multi-level logic synthesis Optimisation criteria
Optimisation criteria
Minimise some function of:

Area occupied by the logic gates and interconnect
approximated by literals = transistors in technology independent
optimization
Critical path delay of the longest path through the logic
Degree of testability of the circuit
measured in terms of the percentage of faults covered by a
specified set of test vectors for an approximate fault model (e.g.
faults)
single or multiple stuckAat
Power consumed by the logic gates
Noise Immunity
Placeability, Wireability
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Example (Area-delay tradeoff)
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Relevance of Multi-level synthesis
Example
Behaviour
w=ab+ab
If w, then z=cd+ad ; u=cd+ad+e(f+b)
else z=e(f+b) ; u=(cd+ad)e(f+b)
Simple higher h/w cost, lower delay, less flexibility
w=ab+ab
z=w(cd+ad) + we(f+b)
u=w(cd+ad+e(f+b)) + w((cd+ad)e(f+b))
Structured more options for cost/delay tradeoff
w=ab+ab
t=cd+ad
s=e(f+b)
z=wt+ws
u=w(t+s)+wts TE
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Representation
Common representations
Boolean network, Factored forms, BDDs
Guiding factors
A structure is needed on which a theory and supporting
algorithms can be developed independent of technology
Manipulations can be made
Optimization progress can be well estimated
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Introduction to multi-level logic synthesis Boolean network
Boolean network
Directed acyclic graph (DAG)

Nodes implement logic function
Representation of node j: fj (x ; y )
Node variable yj : yj = fj (x ; y )
Edge (i ; j) if fj depends explicitly on yi
Inputs: ~x = fx1 ; x2 ; : : : ; xn g
Outputs: ~z = fz1 ; z2 ; : : : ; zp g
External dont cares: d1 (~x ); d2 (~x ); : : : ; dp (~x )
Controllability dont care set Input patterns never produced by
the environment at the input of n/w
Observability dont care set Input patterns representing
conditions when an output is not observed by the OF
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Introduction to multi-level logic synthesis Boolean network
Boolean network
Directed acyclic graph (DAG)

Nodes implement logic function
Representation of node j: fj (x ; y )
Node variable yj : yj = fj (x ; y )
Edge (i ; j) if fj depends explicitly on yi
Inputs: ~x = fx1 ; x2 ; : : : ; xn g
Outputs: ~z = fz1 ; z2 ; : : : ; zp g
External dont cares: d1 (~x ); d2 (~x ); : : : ; dp (~x )
Controllability dont care set Input patterns never produced by
the environment at the input of n/w
Observability dont care set Input patterns representing
conditions when an output is not observed by the OF
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Introduction to multi-level logic synthesis Manipulation of Boolean Networks
Manipulation of Boolean Networks
Basic techniques:
Global structural operations change topology
Algebraic methods
Boolean methods
Local node simplification change node functions
dont cares
node minimisation
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Boolean and algebraic methods

Example
f = ab + ac + ad + a0 c + a0 d
Algebraic treat functions symbolically as polynomials

exploit properties of polynomial algebra
simpler andA faster, but weaker
Example (with algebraic simplication)
f = a(b + c + d ) + a0 (c + d ) 7 literals
Boolean exploit properties of Boolean algebra

use dont cares
more complex, more general
Example (with Boolean simplication)
f = ab + c + d 4 literals
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Boolean and algebraic methods

Example
f = ab + ac + ad + a0 c + a0 d
Algebraic treat functions symbolically as polynomials

exploit properties of polynomial algebra
simpler andA faster, but weaker
Example (with algebraic simplication)
f = a(b + c + d ) + a0 (c + d ) 7 literals
Boolean exploit properties of Boolean algebra

use dont cares
more complex, more general
Example (with Boolean simplication)
f = ab + c + d 4 literals
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Algebraic methods for multi-level optimisation
Section outline
38 Algebraic methods for multi-level optimisation

Algebraic expressions and products
Factored forms
Cofactor of factored forms
Factorization value
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Algebraic methods for multi-level optimisation Algebraic expressions and products
Algebraic expressions and products

Algebraic expression
f is an algebraic expression if f is a set of cubes (SOP), such that no
single cube contains another (minimal with respect to single cube
containment)
Example
a + bc is an algebraic expression
a + ab is not an algebraic expression (factoring gives a(1 + b))
Product
The product of two expressions f and g is a set defined by
fg = fcd jc 2 f ^ d 2 g ^ cd 6= 0g
Example
(a + b)(c + d + a0 ) = ac + ad + bc + bd + a0 b
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Algebraic methods for multi-level optimisation Algebraic expressions and products
Algebraic product
Algebraic product
fg is an algebraic product if f and g are algebraic expressions and have
disjoint support (that is, they have no input variables in common)
Example
(a + b)(c + d ) = ac + ad + bc + bd is an algebraic product
Example
(a + b + c )(c + d + e) is not an algebraic product
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Algebraic methods for multi-level optimisation Factored forms
Factored forms
Definition (Factored forms)

1 A product is either a single literal or a product of factored form
2 A sum is either a single literal or a sum of factored forms
3 A factored form is either a product or a sum
Factoring trees
Graphical representation of factored forms
Labeled trees, in which each internal node including the root is
labeled with either
OR (+)
AND ()
each leaf has a label of either a variable or its complement (literal)
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Factored forms (contd.)
Example
f = (ad + b0 c )(c + d 0 (e + ac 0 )) + (d + e)fg
Example
f = ad + ae + bd + be + cd + cef 0 a0b0c 0 + d 0e0 (a + b + c )(d + e)

Example (Boolean network but not a FF)
f = (a0 + b0 )0 c 0 abc 0
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Example
f = (ad + b0 c )(c + d 0 (e + ac 0 )) + (d + e)fg
Example

f = (a0 + b0 )0 c 0 abc 0
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Example
f = (ad + b0 c )(c + d 0 (e + ac 0 )) + (d + e)fg
Example

f = (a0 + b0 )0 c 0 abc 0
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Advantages
Good representative of logic complexity
In many designs (e.g. complex gate CMOS) the implementation of
a function corresponds directly to its factored form
Good estimator of logic implementation complexity
Does not blow up easily
Literal count _ transistor count _ area
Disadvantages
Not as many algorithms available for manipulation
Just convert into SOP before manipulation
Example (Achilles heel function)
Qn=2
i +1 (x2i 1 + x2i )
n literals in the factored form
(n=2) 2n=2 literals in the SOP form
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Algebraic and Boolean Factored Forms
Algebraic FF
A factored form f is said to be algebraic if the SOP expression
obtained by multiplying f out directly (i.e. without using the special laws
of Boolean algebra) is algebraic.
If the resulting expression is not algebraic, the FF is Boolean.
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Examples of algebraic and Boolean FFs
Example (Algebraic FF)
f = (b + c )(d + e) + ((d + e + g )f + (b + c )g )a
= (bd + be + cd + ce) + (df + ef + gf + bg + cg )a
= bd + ce + be + cd + abg + acg + adf + aef + afg
Example (Boolean FF)
f = (af + b + c )(ag + d + e)
= afag + afd + afe + bag + bd + be + cag + cd + ce
= afg + adf + aef + abg + acg + bd + be + cd + ce
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Same expression can have both algebraic and Boolean factored forms
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Examples of algebraic and Boolean FFs
Example (Algebraic FF)
f = (b + c )(d + e) + ((d + e + g )f + (b + c )g )a
= (bd + be + cd + ce) + (df + ef + gf + bg + cg )a
= bd + ce + be + cd + abg + acg + adf + aef + afg
Example (Boolean FF)
f = (af + b + c )(ag + d + e)
= afag + afd + afe + bag + bd + be + cag + cd + ce
= afg + adf + aef + abg + acg + bd + be + cd + ce
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Same expression can have both algebraic and Boolean factored forms
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Equivalent Factorizations
Equivalence
Two factored forms are equivalent if they represent the same logic
function.
Example
a(b + c ) + bc ab + c (a + b)
Syntactic equivalence
Two factored forms are syntactically equivalent if their factoring tree
are isomorphic can be made identical by renaming.
Example
(a + b)(c + d )e (c + d )e(a + b)
a(b + c ) + bc ab + c (a + b)
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Equivalent Factorizations
Equivalence
Two factored forms are equivalent if they represent the same logic
function.
Example
a(b + c ) + bc ab + c (a + b)
Syntactic equivalence
Two factored forms are syntactically equivalent if their factoring tree
are isomorphic can be made identical by renaming.
Example
(a + b)(c + d )e (c + d )e(a + b)
a(b + c ) + bc ab + c (a + b)
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Maximal Factorization
Maximal factorisation
A factored form is maximally factored if
For every sum of products, there are no two syntactically
equivalent factors in the products
For every product of sums, there are no two syntactically
equivalent factors in the sums
Example
ab + ac is not maximally factored, a(b + c ) is.
Example
(a + b)(a + c ) is not maximally factored, a + bc is.
Example TE
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ab + (a + b)c is maximally factored.
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Optimum Factored Forms

(f )
The size of a factored form f , (f ), is the number of literals in that
factored form.
Example
((a + b)ca0 ) = 4
((a + b + cd )(a0 + b0 )) = 6
Optimum FF
A factored form is optimum if no other equivalent factored form has
fewer literals.
Example
ab + a0 c + bc is not optimum, ab + a0 c ( ab + a0 c + bc ) is.
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(f )
The size of a factored form f , (f ), is the number of literals in that
factored form.
Example
((a + b)ca0 ) = 4
((a + b + cd )(a0 + b0 )) = 6
Optimum FF
A factored form is optimum if no other equivalent factored form has
fewer literals.
Example
ab + a0 c + bc is not optimum, ab + a0 c ( ab + a0 c + bc ) is.
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Unate factored forms
Positive unate FF
A factored form F is positive unate in x, if x appears in F , but x 0 does
not.
Negative unate FF
A factored form F is negative unate in x, if x 0 appears in F , but x does
not.
Example
(a + b0 )c + a0 is positive unate in c, negative unate in b and binate in a.
Binate FF
A factored form F is binate in x, if both x 0 and x appear in F . TE
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Algebraic methods for multi-level optimisation Cofactor of factored forms
Cofactor of FF
The cofactor of a factored form F with respect to a literal x (or x 0 ) is
the factored form Fx = Fx =1 (x ) (or Fx 0 = Fx =0 (x )) obtained by:
1 replacing all occurrences of x by 1, and x 0 by 0
2 simplifying the factored form using the Boolean algebra identities:
1y = y 1+y =1 0y = 0 0+y =y
3 performing constant propagation (all constants are removed)
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Algebraic methods for multi-level optimisation Cofactor of factored forms
Cofactor of a FF wrt a cube C

The cofactor of a factored form F , with respect to a cube C, is a
factored form FC obtained by successively cofactoring F with each
literal in C
Example
F = (x + y 0 + z )(x 0 u + z 0 y 0 (v + u 0 )) and C= vz 0
Fz 0 = (x + y 0 )(x 0 u + y 0 (v + u 0 ))
Fz 0 v = (x + y 0 )(x 0 u + y 0 ) = FC
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Algebraic methods for multi-level optimisation Factorization value
Factorization value
Definition (Factorization value of F = G1 G2 + R)
The factorization value of an algebraic factorization F = G1 G2 + R is
defined as:
fact val(F; G2 ) = lits(F ) (lits(G1 ) + lits(G2 ) + lits(R ))

= (jG1 j 1)lits(G2 ) + (jG2 j 1)lits(G1 )
assuming G1 ; G2 and R are algebraic expressions and jH j is the

number of cubes in the SOP form of H
Let G be product of G1 and G2

lits(F ) = lits(G) + lits(R )
lits(G1 G2 + R ) = lits(G1 ) + lits(G2 ) + lits(R )
Thus, fact val(F; G2 ) =
(lits(G) + lits(R )) (lits(G1 ) + lits(G2 ) + lits(R )) = TE
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lits(G) (lits(G1 ) + lits(G2 ))

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Factorisation value (contd.)

G = G1 G2 has the form
(p1;1 + p1;2 + : : : + p1;n1 )(p2;1 + p2; 2 + : : : + p2;n2 ) =
p1;1 p2;1 + p1;1 p2;2 + : : : + p1;1 p2;n2 +
p2;1 p2;1 + p2;1 p2;2 + : : : + p2;1 p2;n2 +
:::
pn1 ;1 p2;1 + pn1 ;1 p2;2 + : : : + pn1 ;1 p2;n2
Since the factorization is algebraic, G1 and G2 have disjoint
support and so the number of literals in pi ;j pl ;m is li ;j + ll ;m , where
li ;j is the number of literals in pi ;j
The number of literals in row i is
li ;1 + l2;1 + li ;1 + l2;2 + : : : + li ;1 + l2;n2 =
li ;1 jG2 j + (l2;1 + l2;2 + : : : + l2;n2 ) = li1 jG2 j + lits(G2 )
There are jG1 rows, so the total number of literals is
lits(G1 )jG2 j + jG1 jlits(G2 )
fact val(F; G2 ) = lits(G1 )jG2 j + jG1 jlits(G2 ) (lits(G1 ) + lits(G2 )) TE
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= (jG1 j 1)lits(G2 ) + (jG2 j 1)lits(G1 )
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Factorisation value (contd.)
Example
Let F = ae + af + ag + bce + bcf + bcg + bde + bdf + bdg
G1 = (a + bc + bd )
G2 = (e + f + g )
F can be expressed in the form
F = G1 G2 + R = (a + b(c + d ))(e + f + g ), where R = .
F requires 7 literals, rather than 24; saving is 17
fact val(F; G2 ) = 23+25=16.
The actual factored form above saves 17 literals, not 16.
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Restructuring Boolean networks
Section outline
39 Restructuring Boolean networks

Decomposition
Extraction
Factoring
Substitution
Elimination
Product
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Given initial network, find best network.

Important steps
find good common subfunctions
effect the division
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Restructuring Boolean networks Decomposition
Decomposition
Decomposition
From
cd + b cd
F = abc + abd + a
we may obtain
X = ab
Y =c+d
Y
F = XY + X
A single Boolean function is expressed as a collection of new

functions
The resulting form is similar to a DAG, very much context sensitive TE
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Restructuring Boolean networks Extraction
Extraction
Extraction
From
F = (a + b)cd + e
G = (a + b)e
H = cde
we may obtain
X =a+b Y = cd
F = XY + e
G = Xe
H = Ye
Extraction is applied to several to functions and is similar to

decomposition TE
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Restructuring Boolean networks Factoring
Factoring
Factoring
From
F = ac + ad + bc + bd + e
we may obtain
F = (a + b)(c + d ) + e
Factoring leads to a factored form of a SOP representation
series-parallel (tree-like) decomposition, it is context free
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Restructuring Boolean networks Substitution
Substitution
Substitution
G =a+b
can be substituted into
F = a + bc
to obtain
F = G(a + c ) = a + bc
As a result an arc is created from one node to another in a Boolean

network
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Restructuring Boolean networks Elimination
Elimination
Elimination or Collapsing
G =a+b
F = G(a + c )
F can be flattened to obtain
F = a + ac + ab + bc
= a(1 + c + b) + bc
= a + bc
G may be dropped if it is not otherwise needed

Factoring, resubstitution, extraction make use of division TE
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Value of a Node and Elimination
Example
Before
0 0 a + x (y + z ) + x 0 (bd ) After
x (ab + a b )
(a0 c + aby )(ab + a0 b0 )

1 2
1 2
a + (a0 c + aby )(y + z )+
(a + c 0 )(a0 + b0 + y 0 )(bd )
x 3 a0 c + aby
Literals before = 5+7+5 = 17, literals after = 9+15 = 24, difference = 7

n1 = 1 (1 occurrence of x in node 1), n2 = 2 (1 occurrence x and 1 of x
in node 2), l3 = 5 (3 literals in node 3)
value(3) = ((n1 + n2 ) 1)(l3 1) 1 = ((1+2)-1)(5-1)-1 = 7
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Value of a Node and Elimination (contd.)

i1 ; li1 i2 ; li2 i3 ; li3
y j j ; lj
ni = number of times literals yj and yj0 occur in factored form fi , lj =

number of literals in factored fj , FO: fanout
P
literal count with factoring: lj + i 2FO(j ) ni + c
P
literal count without factoring: lj i 2FO(j ) ni + c
value = (without factoring) - (with factoring)
P
value(j ) = 2
i FO(j ) ni 1 ( lj 1) 1
Can treat yj and yj0 the same since (Fj ) = (Fj0 )
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Value of a Node and Elimination (contd.)
Example
f1 = b(n + ag ) + h and f2 = i (n + aj ) + k; result of elimination
l=d+e value=-1
m=cl+f value=-1
n=am value=0 n=a(c(d+e)+f) value=5
f1 f2 f1 f2 TE
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Restructuring Boolean networks Optimum Factored Forms
Lemma
Let f = g + h such that g ? h, then (f ) = (g ) + (h)
Corollary
Let f = gh such that g ? h, then (f ) = (g ) + (h)
Corollary
P Q
Let f = n1=1 m
P Q j =1 ij
f such that fij ? fkl ; i 6= j ^ j 6= l, then
(f ) = n1=1 mj=1 (fij )
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Optimum Factored Forms (contd.)
Redundant variable
For an incompletely specified function (f ; d ), if no optimum factored
form of (f ; d ) can contain variable x, then x is said to be redundant
Lemma
If F covers (f ; d ), then Fc covers (fc ; dc ) for any cube c
Theorem
Let (f ; d + e) be an incompletely specified function such that
sup(f + d ) \ sup(e) = , then variables in sup(e) are redundant, which
implies (f ; d + e) = (f ; d )
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Let f be a Boolean function, if there is a sum of product representation

whose cube matrix has the structure as indicated in the figure, where
the support of A and B are X and Y respectively, then no prime p
contains variables from both X and Y
A 2
f 2 B
X Y
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Not only does this theorem show the uniqueness of the partition (if
cubes are made prime), it also indicates a procedure for obtaining it.
Given an incompletely specified function (F ; D ):
expand all cubes of F + D to primes,
build a cube matrix M,
partition M into blocks of disjoint supports,
remove from M each block of the partition that is contained
entirely in D
A 2 F
2
D1
f =
2 B 2 D2
X Y X Y
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Restructuring Boolean networks Product
Product
Product of two algebraic expressions
P
Given two algebraic expressions f and g ; fg ; is a i ;j ci dj ; where f

= fci g and
g = dj ; made irredundant w.r.t single cube containment.
Example
ab + a = a
Algebraic product is defined only when f and g have disjoint supports.

Boolean product: otherwise.
Example
(a + b)(c + d ) = ac + ad + bc + bd is an algebraic product
(a + b)(a + c ) = aa + ac + ab + bc = a + bc is a Boolean product, TE
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because the terms of the product do not have disjoint support
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Division
Section outline
40 Division
Division (f = gh + r )
Factors and divisors
Division with incompletely specified functions
Boolean Division algorithm
Algebraic quotient computation
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Division Division (f = gh + r )
Division (f = gh + r )
Boolean divisor
Function g is a Boolean divisor of f if h and r exist such that
f = gh + r ; gh 6= 0
Factor
Function g is said to be a factor of f if, in addition, r = 0; i.e., f = gh
h is called the quotient.

r is called the remainder.
h and r may not be unique.
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Division (f = gh + r ) (contd.)
Algebraic quotient
If gh is restricted to an algebraic product, then h is the algebraic
quotient, denoted f ==g
Boolean quotient
Otherwise, h is a (non-unique) Boolean quotient denoted f g
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Division (f = gh + r ) (contd.)
Algebraic divisor
If h 6= 0; and h can be obtained using algebraic division, then g is an
algebraic divisor of f (note g ? h)
Otherwise, g is a Boolean divisor of f.
Algebraic divisor dividing evenly

A algebraic divisor g is said to divide evenly if r =
Algebraic factor
Function g is an algebraic factor of f if there exists an algebraic
expression h such that
f = gh (using algebraic multiplication) TE

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Division example
Example
f = ad + ae + bcd + j
g1 = a + bc
g2 = a + b
Algebraic division
f ==a = d + e; f ==a = d ; f ==a = e not unique

f ==(bc ) = d
h1 = f ==g1 = d ; r1 = ae + j
Boolean division
h2 = f g2 = (a + c )d ; r2 = ae + j
= (a + b)(a + c )d + ae + j
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Division Factors and divisors
Factors and divisors
Property of factors
A logic function g is a Boolean factor of a logic function f , if and only if
f g (i:e: f g = ; i:e: g f )
h = f works fine
Given f and g ; h is not unique
Small h is desirable and is same as getting a small f + r : Since
rg = 0; minimizing f with don0 t care = g
is required
Property of divisors
A logic function g is a Boolean divisor of a logic function f if and only if
fg 6= TE
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Division Division with incompletely specified functions
Division with incompletely specified functions
Boolean divisor of an incompletely specified functions

A completely specified logic function g is a Boolean divisor of F if there
exist h; and e (completely specified) such that
f gh + e f + d and gh
=d
Boolean factor of incompletely specified function

Function g is a Boolean factor of F if there exists h such that
f gh f + d
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Boolean division related properties of

incompletely specified functions
Property for Boolean factor

f g if and only if g is a Boolean factor of F
)
Obtain h = f + k by simplifying f with DC = (d + g
Property for Boolean divisor

6 0 if and only if g is a Boolean divisor of F
fg =
6 0
Choose g such that fg =
) to get h
Simplify fg with DC = (d + g
with DC = (d + fg ) to get e (could use DC = d + gh )
Simplify f g
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Linkage between algebraic and Boolean division
Divisors
Suppose g is an algebraic divisor of F ; a cover of (f ; d ; r ). If f
=e
(where e is the remainder in the algebraic division, i.e. F = gh + e)
then g is a Boolean divisor of F
Factors
If g is an algebraic factor of F a cover of (f ; d ; r ), then g is a Boolean
factor of F
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Division Boolean Division algorithm
Boolean Division algorithm
Write a cover for (f ; d ; r ) in the form gh + e where h; and e are minimal

in some sense (say, minimum factored form)
Algorithm outline
Create a new variable x to represent g
Form the DC-set d 0 = x g 6 g)
+ x g (Since x = g we dont care if x =
Minimize (f d0 ; d + d 0 ; r d0 ) to get f 0
Return (h = f 0 =x ; e) where e is the remainder of the weak division.
(These are simply the terms not containing x)
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Division Boolean Division algorithm
Boolean Division algorithm (contd.)
booleanDivide_1(F,D,G) {
D_1 = D + xG + xG // (dont care)
F_1 = FD_1 // (on-set)
R_1 = (F_1 + D_1) = F_1D_1 = FD_1
// (OFF-set)
F_2 = remove x from F_1
F_3 = MIN_LITERAL(F_2, R_1, x)
// Filter for Espresso
// (min. literal support including x)
F4 = ESPRESSO(F_3,D_1,R_1)
H = F4/x // (quotient)
E = F4 - fxH g ==(remainder )
return (HG+E)
}
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Division Algebraic quotient computation
Algebraic quotient computation
Let F and G be given as F = [1

jf j fb g and G = [jg j fa g
i 1 i
Let Hi = [j cj jai cj 2 F ; 1 i jGj
jg j
Let H = \ H 1 i
R = F nGH
F = GH + R
O (jF jjGj) operations
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Algebraic quotient computation (contd.)
Example
F = abc + abd + de
G = ab + e
H1 = fc ; d g
Hh = fd g
H = h1 \ h2 = fd g
R = abc
F = (ab + e)d + abc
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Application of division
Application to multi-level logic optimization

Given a set of functions fFi g ; find common weak (algebraic) divisors.
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Special expressions for division
Cube-free expression
A Boolean expression is cube-free if no cube divides the expression
evenly (i.e. the cubes do not have a common literal)
A cube-free expression must have more than one cube.
Example
ab + c is cube-free, but ab + ac (a is a commoncube ) and abc
(singleton cube) are not cube-free
Primary divisors
The primary divisors of an expression F are the set of expressions
D (F ) = fF =c jc is a cubeg TE
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Kernels and co-kernels
Section outline
41 Kernels and co-kernels
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Kernels
The kernels of an expression F are the set of expressions
K (F ) = fGjG 2 D (F ) and G is cube freeg :
Thus, the kernels of an expression F are the cube-free primary

divisors of F
Co-kernel
A cube c used to obtain the kernel K = F =c is called a co-kernel of K
C (F ) is used to denote the set of co-kernels of F
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Sample computation of kernels and co-kernels
Example
F = adf + aef + bdf + bef + cdf + cef + g

= (a + b + c )(d + e)f + g
Kernels Co-kernels
a+b+c df ; ef
d +e af ; bf ; cf
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Fundamental Theorem on kernels
Fundamental Theorem
If two expressions F and G have the property that
8kF 2 K (F ); 8kG 2 K (G) ) jkG [ kF j 1

(kG and kF have at most one term in common), then F and G have no
common algebraic multiple divisors (i.e. with more than one cube)
If all functions are kernel-ed and there are no non-trivial intersections,

then the only common algebraic divisors left are single cube divisors
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Kernel levels
Level of a kernel
A kernel is of level 0 (K 0 ) if it contains no kernels except itself.
A kernel is of level n (K n ) if it contains at least one kernel of level
(n 1); but no kernels (except itself) of level n or greater
K 0 (F ) K 1 (F ) K 2 (F ) : : : K n (F ) K (F )
level-n kernels: K n (F )nK n 1 (F )
K n (F ) is the set of kernels of level k or less
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Kernel levels
Example
F = (a + b(c + d ))(e + g )
k1 = a + b(c + d ) 2 K 1 2= K 0
k2 = c + d 2 K0
k3 = e + g 2 K 0
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Kerneling Algorithm
kernel(j, G) {
R=
if(cubeFree(G)) R = G
for(i = j + 1; : : : ; n) {
if(li appears only in one term) continue
if(9k i ; lk 2 all cubes of G=li ) continue
// efficiency factor
// each co-kernel is tried only once
// may be used to generate all co-kernels
R = R [ kernel(i,makeCubeFree(G=li ))
}
return R
}
MAKE_CUBE_FREE(F ) removes algebraic cube factor from F
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Single-Cube Containment (SCC)
Given any two cubes, c1 and c2 , cube c1 is single-cube contained in

c2 , if c2 contains (covers) c1
Single-cube containment of a set
Let C = fc1 ; c2 ; : : : ; ck g
The single-cube containment of set C is the resulting set after
applying single-cube containment to every pair of cubes in C
P = SCC(consensus(P1; P0))
Example

SCC(C ) = fx1 x2 x3 ; x1 x2 ; x2 x3 x4 ; x1 x4 g TE
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Algebraic expressions
Algebraic expression
It is a SOP representation of a logic function which is minimal w.r.t.
single cube containment.
Example
ab + abc + cd is not an algebraic expression
ab + cd is an algebraic expression
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Part VIII
Partitioning
42 Role of partitioning
43 Representation issues
44 Problem description
45 Kernighan-Lin approach
46 Fiduccia-Mattheyses approach
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47 Ratio cut partitioning

Role of partitioning
Section outline
42 Role of partitioning
Terminology
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Role of partitioning
Importance
Key to applying divide-and-conquer methodology to solve

problems of high complexity
System-level partitioning for multi-chip designs inter-chip
interconnection delay dominates system performance
Circuit level partitioning to deal with physical design in a
hierarchical manner
In deep-submicron designs, partitioning defines local and global
interconnect, and has significant impact on circuit performance
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Role of partitioning Terminology
Terminology
Partitioning
Dividing bigger circuits into a small number of partitions
(top down)
Clustering
Cluster small cells into bigger clusters (bottom up)
Covering / Technology Mapping
Clustering such that each partition (cluster) has some
special structure (e.g., can be implemented by a cell in a
cell library)
k-way Partitioning
Dividing into k partitions
Bipartitioning
2-way partitioning
Bisectioning
Bipartitioning such that the two partitions have the same
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size
Representation issues
Section outline
43 Representation issues
Circuit representation
Edge weights for multi-terminal nets
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Representation issues Circuit representation
Netlist The thing that is actually available.
Gates: A, B, C, D
Nets: fA, B, Cg, fB, Dg, fC, Dg
Hypergraph This is an abstract representation of netlists

Vertices: A, B, C, D
Hyperedges: fA, B, Cg, fB, Dg, fC, Dg
Vertex label: Gate size/area
Hyperedge label: Importance of net (weight)
Prefereable to represent circuit as a graph
instead of a hypergraph TE
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Representation issues Circuit representation
Netlist The thing that is actually available.
Gates: A, B, C, D
Nets: fA, B, Cg, fB, Dg, fC, Dg
Hypergraph This is an abstract representation of netlists

Vertices: A, B, C, D
Hyperedges: fA, B, Cg, fB, Dg, fC, Dg
Vertex label: Gate size/area
Hyperedge label: Importance of net (weight)
Prefereable to represent circuit as a graph
instead of a hypergraph TE
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Representation issues Edge weights for multi-terminal nets
Edge weights for multi-terminal nets
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Edge weights for multi-terminal nets (contd.)

Replace each net with its complete graph
Necessary to assign weight to each resulting edge
Weight assignment should be such that cost of partitioning should
be realistic
some options:
assign weight of 1 to each resulting edge
For a n-pin net, w = n 1 1
For any cut, cost 1
Provides an upper bound on the cost of a cut in the actual netlist
Leads to highly sub-optimal partitions
Maximum edges (arising from the hyperedge) cut when nodes are
divided equally between two partitions n (n 4mod 2)
2
4
Each edge is assigned weight n2 (n mod 2)
Example: Let n = 3, w = 4
= 0:5
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32 1

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be realistic
some options:
For any cut, cost 1
2
4
= 0:5
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32 1

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be realistic
some options:
For any cut, cost 1
2
4
= 0:5
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32 1

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be realistic
some options:
For any cut, cost 1
2
4
= 0:5
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Problem description
Section outline
44 Problem description
Circuit bi-partitioning formulations
Description and search space
Partitioning approaches
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Problem description Circuit bi-partitioning formulations
Circuit bi-partitioning formulations
Aim is to minimise interconnections

between partitions
Example (Performance of
Let the vertices be partitioned into cuts)
two sets: X and X 0
Let CX ;X 0 denote the cost of the
edges crossing between X and X 0 ,
then we have:
Minimum cut: minX CX ;X 0
Minimum bisection: minX CX ;X 0 , s.t.
jX j = jX 0j Min-cut size: 13
CX ;X 0
Ratio cut: RX ;X 0 = X X0
j jj j Min-bisection size: 300
Ratio-cut size: 19
Ratio-cut helps to
identify natural clusters
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Problem description Description and search space

Problem description
Given a graph, G, having n nodes
nodes have weights (sizes)
wi : 0 < wi p; i = 1; : : : ; n
edges have weights (costs)
partition the nodes of G into k subsets (k > 0)
each subset is no larger than a given maximum size
p criterion for admissibility
objective is to minimize the total cost of the edges cut
Search space of problem
n = kp nodes are to be partitioned into k subsets,
ofsizep
each
1
k! p
n n p
p 2pp pp ways altogether
exponential in n TE
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Enumeration of candidate solutions is not an option

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Problem description Description and search space

Problem description
Given a graph, G, having n nodes
nodes have weights (sizes)
wi : 0 < wi p; i = 1; : : : ; n
edges have weights (costs)
partition the nodes of G into k subsets (k > 0)
each subset is no larger than a given maximum size
p criterion for admissibility
objective is to minimize the total cost of the edges cut
Search space of problem
n = kp nodes are to be partitioned into k subsets,
ofsizep
each
1
k! p
n n p
p 2pp pp ways altogether
exponential in n TE
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Problem description Partitioning approaches
Problem is NP-complete, hence non-exact optimisation methods are

preferred
Heuristic growth Start with seed node for each partition and assign
nodes to each partition using some criterion (e.g. sum of
weighted connections into partition)
Heuristic migration Start with (random) initial partition and migrate
nodes among partitions via some heuristic
Stochastic optimization based a general-purpose stochastic
approach such as simulated annealing or genetic
algorithms
Spectral based using metrics beyond connection graph to form node
clusters
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preferred
algorithms
clusters
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preferred
algorithms
clusters
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Well known partitioning techniques
Greedy iterative improvement method

Kernighan-Lin 1970
Fiduccia-Mattheyses 1982
Krishnamurthy 1984
Simulated Annealing
Kirkpartrick-Gelatt-Vecchi 1983
Greene-Supowit 1984
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Kernighan-Lin approach
Section outline
45 Kernighan-Lin approach
Outline of K-L
Vertex swapping
K-L algorithm steps
Complexity analysis of K-L
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Kernighan-Lin approach Outline of K-L
Outline of K-L
Classic technique An Efficient Heuristic Procedure for Partitioning

Graphs, The Bell System Technical Journal, vol 49(2), pp
291-307, 1970
Scope For circuit bisectioning
All gates are of the same size
Works only for 2-terminal nets
Hypergraps must be suitably transformed
Formulation Input A graph with
Set vertices V (jV j = 2n)
Set of edges E (jE j = m)
Cost ci ;j of each edge fi ; j g 2 E
Output Two partitions X and Y such that total cost of
edges cut is minimized TE
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Outline of K-L

291-307, 1970
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Outline of K-L

291-307, 1970
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Outline of K-L

291-307, 1970
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Method used in K-L
Outline of method
Start with any arbitrary partition hX0 ; Y0 i of V having
cost T0 and jX0 j = jY0 j
In the j-th step, try to decrease
the cost
Tj by
interchanging nodes between Xj ; Yj
The method is greedy continues so long as the cost
decreases in the long run
Global optimality is not guaranteed
Cost of a partition For a vertex u 2 X
P
External cost Eu =P v 2Y cu ;v
Internal cost Iu = v 2X cu ;v
Cost difference For each w 2 V , Dw = Ew Iw
Interchange gain For x 2 X ; y 2 Y , gx ;y = Dx + Dy 2cx ;y TE
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Method used in K-L
Outline of method
the cost
Tj by
P
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Method used in K-L
Outline of method
the cost
Tj by
P
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Method used in K-L
Outline of method
the cost
Tj by
P
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Kernighan-Lin approach Vertex swapping
Vertex swapping
Chossing a pair to swap

1 For each u 2 V , compute Du
2 Choose hx ; y i such that gx ;y is maximal
3 Recalculate the D values for all the elements of
X f x g ; Y fy g
8u 2 X fx g ; Du0 = Du + 2cu;x 2cu ;y
8v 2 Y fy g ; Dv0 = Dv + 2cv ;y 2cv ;x
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Kernighan-Lin approach Vertex swapping
Vertex swapping
Chossing a pair to swap

1 For each u 2 V , compute Du
2 Choose hx ; y i such that gx ;y is maximal
3 Recalculate the D values for all the elements of
X f x g ; Y fy g
8u 2 X fx g ; Du0 = Du + 2cu;x 2cu ;y
8v 2 Y fy g ; Dv0 = Dv + 2cv ;y 2cv ;x
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Kernighan-Lin approach K-L algorithm steps
K-L algorithm steps

Perform initialisations
/* Compute global value of individual node swaps */
Repeat until no further improvement f
for i = 1 to N do f
find pair of unlocked nodes xi in X
and yi in Y whose exchange leads to
largest decrease or smallest increase in
cost (Ci ) due to exchanging xj and yj
lock down xi and yi so they dont
participate in future moves
g
/* find best sequence
P of swaps */
find l such that j l Cj is maximized
move xj ; j l from X to Y
move yj ; j l
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Kernighan-Lin approach Complexity analysis of K-L
The sequence of operations needed to determine a pair of sets to

exchange is a pass of K-L
Initial computation of D for all the nodes is O (n2 )
Updating D after locking pairs: O ((n 1) + (n 2) + : : : + 2 + 1)
= O (n2 )
Selecting next pair to exchange involves sorting the D values:
O (n lg n + (n 1) lg(n 1) + (n 2) lg(n 2) + : : : + 2 lg 2) =
O (n2 lg n) dominant term
Complexity of K-L: O (n2 lg n)
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The sequence of operations needed to determine a pair of sets to

exchange is a pass of K-L
Initial computation of D for all the nodes is O (n2 )
Updating D after locking pairs: O ((n 1) + (n 2) + : : : + 2 + 1)
= O (n2 )
Selecting next pair to exchange involves sorting the D values:
O (n lg n + (n 1) lg(n 1) + (n 2) lg(n 2) + : : : + 2 lg 2) =
O (n2 lg n) dominant term
Complexity of K-L: O (n2 lg n)
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K-L example
Example
Initialisation X = f2; 3; 4g ; Y = f1; 5; 6g

D-values D1 = E1 I1 =1 0 = +1
D2 = E2 I2 =1 2= 1
D3 = E3 I3 =0 1= 1
D4 = E4 I4 =2 1 = +1
D5 = E5 I5 =1 1 = +0
D6 = E6 I6 =1 1 = +0 TE
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K-L example (contd.)

Example
Gains g2;1 = D2 + D1 2c2 1 = ( 1) + (+1) 2(1) = 2
;
g2;5 = D2 + D5 2c2 5 = ( 1) + (+0) 2(0) = 1

;
g2;6 = D2 + D6 2c2 6 = ( 1) + (+0) 2(0) = 1

;
g3;1 = D3 + D1 2c3 1 = ( 1) + (+1) 2(0) = +0

;
g3;5 = D3 + D5 2c3 5 = ( 1) + (+0) 2(0) = 1

;
g3;6 = D3 + D6 2c3 6 = ( 1) + (+0) 2(0) = 1

;
g4;1 = D4 + D1 2c4 1 = (+1) + (+1) 2(0) = +2

;
g4;5 = D4 + D5 2c4 5 = (+1) + (+0) 2(1) = 1

;
g4;6 = D4 + D6 2c4 6 = (+1) + (+0) 2(1) = 1

;
Update sets X 0 =X f4g = f2; 3g, Y 0 = Y f1g = f5; 6g

Update D-values Consider nodes connected to h4; 1i f2g X 0 ,
f5; 6g Y 0
D20 = D2 + 2c2 4 2c2;1 = 1 + 2(1 1) = 1
D50
;
= D5 + 2c5 1 2c5;4 = +0 + 2(0 1) = 2 TE

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= D6 + 2c6 1 = +0 + 2(0 1) =
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Example
Gains g2;1 = D2 + D1 2c2 1 = ( 1) + (+1) 2(1) = 2
;
g2;5 = D2 + D5 2c2 5 = ( 1) + (+0) 2(0) = 1

;
g2;6 = D2 + D6 2c2 6 = ( 1) + (+0) 2(0) = 1

;
g3;1 = D3 + D1 2c3 1 = ( 1) + (+1) 2(0) = +0

;
g3;5 = D3 + D5 2c3 5 = ( 1) + (+0) 2(0) = 1

;
g3;6 = D3 + D6 2c3 6 = ( 1) + (+0) 2(0) = 1

;
g4;1 = D4 + D1 2c4 1 = (+1) + (+1) 2(0) = +2

;
g4;5 = D4 + D5 2c4 5 = (+1) + (+0) 2(1) = 1

;
g4;6 = D4 + D6 2c4 6 = (+1) + (+0) 2(1) = 1

;

f5; 6g Y 0
D20 = D2 + 2c2 4 2c2;1 = 1 + 2(1 1) = 1
D50
;
= D5 + 2c5 1 2c5;4 = +0 + 2(0 1) = 2 TE

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Example
Gains g2;1 = D2 + D1 2c2 1 = ( 1) + (+1) 2(1) = 2
;
g2;5 = D2 + D5 2c2 5 = ( 1) + (+0) 2(0) = 1

;
g2;6 = D2 + D6 2c2 6 = ( 1) + (+0) 2(0) = 1

;
g3;1 = D3 + D1 2c3 1 = ( 1) + (+1) 2(0) = +0

;
g3;5 = D3 + D5 2c3 5 = ( 1) + (+0) 2(0) = 1

;
g3;6 = D3 + D6 2c3 6 = ( 1) + (+0) 2(0) = 1

;
g4;1 = D4 + D1 2c4 1 = (+1) + (+1) 2(0) = +2

;
g4;5 = D4 + D5 2c4 5 = (+1) + (+0) 2(1) = 1

;
g4;6 = D4 + D6 2c4 6 = (+1) + (+0) 2(1) = 1

;

f5; 6g Y 0
D20 = D2 + 2c2 4 2c2;1 = 1 + 2(1 1) = 1
D50
;
= D5 + 2c5 1 2c5;4 = +0 + 2(0 1) = 2 TE

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Fiduccia-Mattheyses approach
Section outline
46 Fiduccia-Mattheyses approach
Outline of FM
Object gains
Complexity analysis of FM
Extensions to FM
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Fiduccia-Mattheyses approach Outline of FM
Outline of FM
Classic technique A Linear-time Heuristics for Improving Network
Partitions, 19-th DAC, pp 175-181, 1982
Features Extends K-L
Can handle non-uniform vertex weights (areas)
Allow unbalanced partitions
Extended to handle hypergraphs
Clever way to select vertices to move, run faster
Input A hypergraph
Set vertices V (jV j = n)
Set of hyperedges E (total number pins in netlist: p)
Area au for each vertex u in V
Cost ce for each hyperedge e
An area ratio r
Output Two partitions X and Y such that
Total cost of hyperedges cut is minimized
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area(X ) / (area(X ) + area(Y )) is near about r

Outline of FM
Input A hypergraph
An area ratio r
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Outline of FM
Input A hypergraph
An area ratio r
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Outline of FM
Input A hypergraph
An area ratio r
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Comparison with K-L

Similarities
Work in passes
Lock vertices after moved
Actually, only move those vertices up to the
maximum partial sum of gain
Differences
Not exchanging pairs of vertices
Move only one vertex at each time
The use of gain bucket data structure
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Comparison with K-L

Similarities
Work in passes
Lock vertices after moved
Actually, only move those vertices up to the
maximum partial sum of gain
Differences
Not exchanging pairs of vertices
Move only one vertex at each time
The use of gain bucket data structure
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Fiduccia-Mattheyses approach Object gains
Object gains
Object Gain: The amount of change in cut crossings that will

occur if an object is moved from its current partition into the other
partition
Moves are made based on object gain
Each object is assigned a gain
Objects are put into a sorted gain list
Object with the highest gain from the larger of the two sides is
selected and moved the moved object is locked
Gains of touched objects are recomputed
Gain lists are resorted
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Object gains
Object Gain: The amount of change in cut crossings that will

occur if an object is moved from its current partition into the other
partition
Moves are made based on object gain
Each object is assigned a gain
Objects are put into a sorted gain list
Object with the highest gain from the larger of the two sides is
selected and moved the moved object is locked
Gains of touched objects are recomputed
Gain lists are resorted
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FM example
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FM example (contd.)
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FM example (contd.)
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FM example (contd.)
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FM example (contd.)
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FM example (contd.)
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FM example (contd.)
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FM example (contd.)
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FM example (contd.)
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FM example (contd.)
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FM example (contd.)
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FM example (contd.)
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FM example (contd.)
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Fiduccia-Mattheyses approach Complexity analysis of FM
Complexity analysis of FM
For each pass

Constant time to find the best vertex to move
After each move, time to update gain buckets is proportional to
degree of vertex moved
Total time is O (p), where p is total number of pins
Number of passes is usually small
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Fiduccia-Mattheyses approach Extensions to FM
Extensions to FM
An Improved Min-Cut Algorithm for Partitioning VLSI Networks,

Krishnamurthy, IEEE Trans. Computer, vol 33(5), pp 438-446,
1984
For each vertex, instead of having a gain bucket, a gain vector is
used
Gain vector is a sequence of potential gain values corresponding
to numbers of possible moves into the future
The r -th entry looks r moves ahead
Time complexity is O (pr ), where r is max number of look-ahead
moves stored in gain vector
If ties still occur, some researchers observe that LIFO order
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Fiduccia-Mattheyses approach Extensions to FM
Extensions to FM (contd.)
Towards Efficient Hierarchical Designs by Ratio Cut Partitioning,

Wei and Cheng, ICCAD, pp 298-301, 1989
It is not desirable to have some pre-defined ratio on the partition
sizes
Try to locate natural clusters in circuit and force the partitions to be
of similar sizes at the same time
A heuristic based on FM was proposed
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Ratio cut partitioning
Section outline
47 Ratio cut partitioning

Heuristic algorithm for ratio cut partitioning
Initialisation
Iterative shifting
Group swapping for ratio cut
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Ratio cut partitioning Heuristic algorithm for ratio cut partitioning
Heuristic algorithm for ratio cut partitioning
Problem of finding optimum ratio cut is NP-complete

Heuristic algorithm based on FM partitioning is available
Three major phases in algorithm
1 initialisation
2 iterative shifting
3 group swapping
Wei, Y.-C.; Cheng, C.-K.;, Ratio cut partitioning for hierarchical
designs, IEEE Transactions on Computer-Aided Design of
Integrated Circuits and Systems, v-10, #7, pp 911-921, Jul 1991,
doi: 10.1109/43.87601
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Ratio cut partitioning Initialisation
Initialisation
1 Randomly choose a module s. Find the other seed module t at

the end of a longest path by breadth-first search starting from s.
Let X = fsg, and Y = M fs; t g.
2 Choose a module i in Y whose movement to X will generate the
best ratio among all the other competing modules. Move module i
from Y to X ; update X = X [ fi g, and Y = Y fi g.
3 Repeat second step until Y = .
4 Repeat second and third steps with X = ft g and Y = M fs ; t g
until Y = .
5 The cut giving the minimum ratio found in the procedure forms the
initial partitioning.
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Ratio cut partitioning Iterative shifting
Iterative shifting
Definition (Shifting for ratio cut)

Right (left) shifting operation is defined as shifting the modules with the
best resultant ratio value from s(t ) towards t (s)
1 Repeat right shifting operations until all the modules are

exhausted.
2 Choose the minimal ratio value obtained in the first step If the new
ratio value is reduced from the first step, then the cut producing
this ratio forms a new starting partition; otherwise, output the
previous partition and exit the process
3 Repeat the first and the second steps with left shifting operations
4 Repeat all the earlier steps
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Ratio cut partitioning Group swapping for ratio cut
Group swapping for ratio cut

Definition (Ratio gain)
The ratio gain r (i ) of a module i is said to be the ratio decreased if module i
(barring the two seeds s and t) were moved from its current subset to the
other.
The ratio gain could be a negative real number if the module movement
increases the ratio value of the cut.
1 Calculate the ratio gain r (i ) for every module i, and set all modules to
the unlocked state.
2 Select an unlocked module i with the largest ratio gain from two subsets
3 Move module i to the other side, and lock it.
4 Update the ratio gains for the remaining affected and
5 Repeat the previous three steps until all modules are locked.
6 If the largest accumulated ratio gain during this process is positive, swap
TECHNO
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steps; otherwise, output the previous partition and stop.

yog, km s kOflm^
Part IX
Floorplanning
48 Role of floorplanning
49 Floorplan representation
50 Area optimization using shape curves
51 Simulated annealing algorithm for FP
52 Stockmeyer algorithm
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53 GALLO: A genetic algorithm for FP

Role of floorplanning
Section outline
48 Role of floorplanning
Hierarchical design
Objectives of floorplanning
Comparison with placement
Description of problem
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Role of floorplanning Hierarchical design
Hierarchical design
Design reduction obtained after partitioning

Another dimension also added to the problem what to do with
each partition?
If the geometry of the partitions were available, then we could go
about placing them
However, enough information is not available to determine
desirable geometry of the partitions to design them first
Gives rise to the floorplanning problem
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Role of floorplanning Objectives of floorplanning
Objectives of floorplanning
The floorplanning problem is to plan the positions and shapes of the

modules (partitions) to optimize the circuit performance:
chip area
total wirelength
delay of critical path
routability
others, e.g., noise, heat dissipation, etc.
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Role of floorplanning Comparison with placement
Comparison with placement
Both determine block positions to optimize the circuit

performance
Floorplanning
Details like shapes of blocks, I/O pin positions, etc.
are not yet fixed
Working with blocks with flexible shape called soft
blocks
Placement
Details like module shapes and I/O pin positions are
fixed
Working with blocks with fixed shape called hard
blocks (can be rotated)
Possible to bypass FP by recursive application TE
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Role of floorplanning Description of problem
Description of problem
Input Blocks with areas A1 ; : : : ; An ; bounds ri and si on the

aspect ratio of block Bi
Output Coordinates (xi ; yi ), width wi and height hi or each block
such that hi wi = Ai and ri whii si
Restriction on aspect ratio needed to avoid strip shaped
blocks
Such blocks are not suitable either for routing or for
internal design
A weighted sum of area and estimated wire length
(A + L) may be used as the objective function
Half perimeter of rectangle enclosing centers of blocks /
center to center lengths may be used
Objective To optimize the circuit performance. TE
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Floorplan representation
Section outline
49 Floorplan representation
Slicing and non-slicing floorplans
Polar graph representation
Slicing tree representation of slicing FP
Bounding box of a slicing tree
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Floorplan representation Slicing and non-slicing floorplans
Slicing and non-slicing floorplans
Slicing floorplans
Can be obtained by repetitively subdividing
(slicing) rectangles horizontally or vertically
Slicing floorplans are easier to represent and
manipulate
Non-slicing floorplans
May not be obtained by repetitively subdividing
alone
The adjoining wheel structure turns out to be a
key element for the recursive representation of
non-slicing floorplans
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Floorplan representation Polar graph representation
Polar graph representation

Each floorplan is modeled by a pair of directed acyclic graphs:
horizontal polar graph and vertical polar graph
For the horizontal polar graph:
a vertical cut represents a vertex
an edge is present from from u to v if v represents the immediate
next (left-to-right) cut along a horizontal line through u and v
the weight of the edge corresponds to the width of the module
between u and v
For the vertical polar graph:
a horizontal cut represents a vertex
an edge is present from from u to v if v represents the immediate
next (top-to-bottom) cut along a vertical line through u and v
the weight of the edge corresponds to the height of the module
between u and v
General representation scheme (handles both slicing and TE
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non-slicing cases)
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Floorplan representation Polar graph representation
Example of polar graphs of a non-slicing FP

Example
VPG
HPG
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Node labels and edge weights are not shown
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Floorplan representation Slicing tree representation of slicing FP
Slicing tree representation of slicing FP

Internal nodes of the tree represent vertical cuts (with V nodes)
or horizontal cuts (with H nodes)
Leaf nodes represent individual modules
It is a binary tree (not necessarily unique)
Can be represented by the postorder traversal of slicing tree
called a Polish expression
For n blocks, a Polish Expression contains n operands
(blocks/modules) and n 1 (H/V) operators
Unique representation is possible using skewed slicing tree
Skewed slicing tree no node and its right son are the same
ensured using left rotations, if necessary
Normalised Polish expression (NPE) no consecutive Hs or Vs if
derived from skewed slicing trees TE
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Possible to modify a give NPE by way of moves
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Floorplan representation Slicing tree representation of slicing FP
Slicing tree example
Example
Slicing floorplan Slicing tree
Initial NPE: P1 = 25V1H374VH6V8VH

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Floorplan representation Bounding box of a slicing tree
Bounding box of a slicing tree

Leaf node It is a module whose height and width are known
V node Its height and width are from its subtrees:
V.w = V!left.w + V!right.w
V.h = max (V!left.h, V!right.h)
H node Its height and width are from its subtrees:
H.w = max(H!left.w, H!right.w)
H.h = H!left.h + H!right.h
Bounding box of FP Width and height of root node is the bounding
box of a given slicing FP
A postorder traversal of the slicing tree containing
modules of fixed orientation and size, starting at the root
node may be performed to compute the values
If size and/or orientation is flexible, then shape curves are TE
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Area optimization using shape curves
Section outline
50 Area optimization using shape curves

Shape curves
Combining shape curves
Complexity analysis of combining shape curves
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Area optimization using shape curves Shape curves
Shape curves
Various vertical and horizontal

dimensions are possible for a soft
module with aspect ratio , 1r r
These can be modelled by a shape curve
is a smooth, continuous curve in the

first quadrant, such that the x and y
coordinates of points lying on or above
the curve define the feasible region
Shape curves are piece wise contiguous
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Area optimization using shape curves Combining shape curves
Combining shape curves
Pairs of soft modules, A and B, can be combined by adding their

shape curves
For horizontal slicing: AB H add along the y direction
For vertical slicing: AB V add along the x direction
Curve end points mark the limits of flexibility for the rectangles
Resultant shape curve can be computed simply by adding
together the so-called corners of the curves for the component
modules
Shape curves can be combined bottom-up in a slicing tree for a
slicing floorplan
Combinations are performed from interval to interval of the piece
wise sections
Rotation of modules is not permitted TE
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Area optimization using shape curves Complexity analysis of combining shape curves
Complexity analysis of combining shape curves
Keeping k points for each shape curve, time for shape curve
computation for each NPE is O (kn)
After each move, there is only small change in the floorplan
No need to start shape curve computation from scratch
We can update shape curves incrementally after each move
Run time is about O (k log n)
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Area optimization using shape curves Complexity analysis of combining shape curves
Combining of shape curves illustrated

Example (Combination for horizontal slicing)
Possible height and width for

A, B and for the enclosing
rectangle AB H are depicted
Shape flexibility for A is 2 and
B is 3
Note the empty space in the
enclosing rectange of area of
6 units, where the width limit of
A has been reached
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Simulated annealing algorithm for FP
Section outline
51 Simulated annealing algorithm for FP

SA for FP
Moves on NPE
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Simulated annealing algorithm for FP SA for FP
SA for FP
Generic SA is used
Solution is represented using NPE
Moves (M1, M2 and M3) are defined on NPEs to perturb the
solution
Solution cost: weighted sum of bounding box and wire length
estimate
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Simulated annealing algorithm for FP Moves on NPE
Moves on NPE
Chain A sequence of H/V operators (without intervening

operands)
Example
NPE: 16H35V2HV74HV; chains: H, V, HV, HV
Moves Operations to modify a given NPE

M1 Swap adjacent operands (ignoring chains
M2 Complement some chain
M3 Swap 2 adjacent operand and operator (necessary to
check validity of resulting PE after applying M3)
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Illustration of move M1
Example (M1: swap 37)

NPE after M1: P2 = 25V1H734VH6V8VH
Area: 11 15 ! 13 14
Slicing tree
Slicing floorplan
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Example (M2: complement final VH)

NPE after M2: P3 = 25V1H734VH6V8HV
Area: 13 14 ! 15 11
Slicing tree
Slicing floorplan
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Example (M3: swap 6V)

Initial NPE: P2 = 25V1H734VH6V8HV
NPE after M2: P3 = 25V1H734VHV68HV
Area: 15 11 ! 15 7
Slicing tree
Slicing floorplan
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Stockmeyer algorithm
Section outline
52 Stockmeyer algorithm
Problem of determining module orientations
Outline of algorithm
Vertical node sizing
Horizontal node sizing
Complexity analysis of node sizing
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Stockmeyer algorithm Problem of determining module orientations
Problem of determining module orientations
Working with slicing FP

How to determine optimal module orientations to minimise the
area of the floorplan
We are working with a set of irredundant choices of the form
fhx1; y1i ; hxi ; yi i ; hxi +1; yi +1i ; : : :g, xi < xi +1; yi > yi +1
Choices of left and right subtrees of a node are to be combined to
form a new irredundant frontier
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Stockmeyer algorithm Outline of algorithm
Outline of algorithm
Phase I (bottom-up)
given slicing floorplan tree
given module shapes as a sorted irredundant list
perform vertical and horizontal node sizing
after processing root node, the feasible/best sets can
be determined
Phase II (top-down)
FP tree is traversed to set module locations
Optimal cost members of the children nodes that
contributed to the optimal cost member of the parent
node are identified
Eventially optimal orientations of the leaf modules
are determined TE
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Stockmeyer algorithm Vertical node sizing
Vertical node sizing

verticalNodeSizing(L, R) {
// (VNdSz) for vertical cut
// L: fha1 ; b1 i ; : : : ; has ; bs ig,
// ai < aj ; bi > bj ; i < j
// R: fhx1 ; y1 i ; : : : ; hxt ; yt ig,
// xi < xj ; yi > yj ; i < j
// O: H = fhc1 ; d1 i ; : : : ; hcu ; du ig,
// u s + t 1 and ci < cj ; di > dj ; i <j hx1 ; y1 i
H , i 1, j 1, k 1
while (i s and j t) do {
ha1 ; b1 i
hck ; dk i hai + xj ; max(bi ; yj )i Sub-optimal, as max was from y1
H H [ hck ; dk i
if (dk = bi ) then i++
ha2 ; b2 i
if (dk = yj ) then j++
// see illustration ha1 ; b1 i hx2 ; y2 i
k++
} Sub-optimal, as max was from y1
ha2 ; b2 i
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}

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Stockmeyer algorithm Horizontal node sizing
Horizontal node sizing
horizontalNodeSizing(L, R) {
// (HNdSz) for vertical cut
// L: fha1 ; b1 i ; : : : ; has ; bs ig,
// ai > aj ; bi < bj ; i < j
// R: fhx1 ; y1 i ; : : : ; hxt ; yt ig,
// xi > xj ; yi < yj ; i < j
// O: H = fhc1 ; d1 i ; : : : ; hcu ; du ig,
// u s + t 1 and ci > cj ; di < dj ; i <j
H , i 1, j 1, k 1 hx1 ; y1 i
while (i s and j t) do {
hck ; dk i hmax(ai ; xj ); bi + yj i
H H [ hck ; dk i hx2 ; y2 i
if (ck = ai ) then i++
if (ck = xj ) then j++
ha1 ; b1 i
// see illustration Sub-optimal, as max was from x1 , x2 or a1
ha2 ; b2 i
k++ TE
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}
Stockmeyer algorithm Complexity analysis of node sizing
Complexity analysis of node sizing
Analysis for two possible orientation of modules

n = # of leaves = 2 # of modules (as each module
has two orientations)
d = depth of the tree
Running time = O (nd )
Storage = O (nd ), because, at depth k ,
sum of the lengths of the lists=O (n)
time to construct these lists=O (n)
a configurations stored at this node cannot be
released as soon as the node is processed because
the list needs to be revisited during the top-down
traversal
Extension Each module has k possible shapes
Running time and storage O (nkd ) TE
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Illustration of Stockmeyer algorithm

Example (Determining optimal orientation of blocks)
Internal nodes in the slicing tree: top-H-bottom, left-V-right
Block dimension: h1 : 2; 4i, h2 : 1; 3i, h3 : 3; 3i, h4 : 3; 5i, h5 : 3; 2i,
h6 : 5; 3i, h7 : 1; 2i, h8 : 2; 4i
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Illustration of Stockmeyer algorithm (contd.)

Example (Bottom-up tree traversal)
Visiting node a(V)
L = fh51 : 2; 3i ; h52 : 3; 2ig,
R = fh11 : 2; 4i ; h12 : 4; 2ig
Compose 51 and 11 as
h2 + 2; max(3; 4)i = ha1 : 4; 4i
Since the maximum came from R, compose 51 and
12 as h2 + 4; max(3; 2)i = ha2 : 6; 3i
Since the maximum came from L, compose 52 and
12 as h3 + 4; max(2; 2)i = ha2 : 7; 2i
After VNdSz: fha1 : 4; 4i ; ha2 : 6; 3i ; ha3 : 7; 2ig
Visiting node b(H)
L = fh81 : 4; 2i ; h82 : 2; 4ig,
R = fh21 : 3; 1i ; h22 : 1; 3ig TE
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After HNdSz: fhb1 : 4; 3i ; hb2 : 3; 5i ; hb3 : 2; 7ig
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Example (Bottom-up tree traversal)
Visiting node c(V)
L = fha1 : 4; 4i ; ha2 : 6; 3i ; ha3 : 7; 2ig,
R = fhb1 : 2; 7i ; hb2 : 3; 5i ; hb3 : 4; 3ig
After VNdSz:
fhc1 : 6; 7i ; hc2 : 7; 5i ; hc3 : 8; 4i ; hc4 : 10; 3ig
Visiting node d(V)
L = fhc1 : 6; 7i ; hc2 : 7; 5i ; hc3 : 8; 4i ; hc4 : 10; 3ig,
R = fh41 : 3; 5i ; h42 : 5; 3ig
After VNdSz:
fhd1 : 9; 7i ; hd2 : 10; 5i ; hd3 : 13; 4i ; hd4 : 15; 3ig
Visiting node f(V)
L = fhd1 : 9; 7i ; hd2 : 10; 5i ; hd3 : 13; 4i ; hd4 : 15; 3ig
R = fh61 : 3; 5i ; h62 : 5; 3ig
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After VNdSz:
yog, km s kOflm^
Chittaranjan Mandal fhf1 : 12; 7i ; hf2 CAD

(IIT Kharagpur) i ; hf3 : 18; 4i ; hf4 : 20
: 13for; 5VLSI ; 3ig16, 2016
August 557 / 565

Example (Handling the root node)
Visiting node g(H)
L = fhe1 : 3; 4ig,
R = fhf1 : 20; 3i ; hf2 : 18; 4i ; hf3 : 13; 5i ; hf4 : 12; 7ig
After HNdSz:
fhg1 : 20; 7i ; hg2 : 18; 8i ; hg3 : 13; 9i ; hg4 : 12; 11ig
Minimum area floorplan: g3 : 13 9 = 117
Top-down traversal Helps to identify optimal cost members of the children
nodes that contributed to the optimal cost member of the
parent node, eventially leading to optimal orientations of the
leaf modules
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GALLO: A genetic algorithm for FP
Section outline
53 GALLO: A genetic algorithm for FP

Solution representation in GALLO
Working of GALLO
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GALLO: A genetic algorithm for FP Solution representation in GALLO
Solution representation in GALLO
A floorplan consists of an enveloping rectangle partitioned into

non-overlapping basic rectangles (or modules).
For every basic rectangle, a set of implementations is given, which
have a rectangular shape characterized by a width w and a height
h.
The relative positions of the basic rectangles are specified by the
floorplan tree:
leaves being the basic rectangles
root being the enveloping rectangle
the internal nodes are the composite rectangles
Each of the composite rectangles is divided into k parts in a
hierarchical floorplan of order k:
if k=2 (slicing floorplan) a vertical or horizontal line is used
if k=5 a right or left wheel is obtained. TE
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GALLO: A genetic algorithm for FP Working of GALLO
Working of GALLO
Three mutation operations have been defined:
1 A gene is randomly selected, and its value is changed simplest
2 An integer k is generated, and the genes k, 2k, 3k , : : : are randomly
changed more widespread
3 For each gene, the next implementation in the implementation list
(ordered by the aspect ratios of the implementations) is chosen; the
operator executes a rotation of all the modules radical transformation
The classical two-cuts cross-over operator is adopted:
Two members X and Y are first selected (e.g. by roulette wheel
technique) such that better members have a higher selection probability
Two numbers i and j (i < j) in [0 n] are then randomly generated and a
new individual Z is created; for the basic rectangles from 0 to i
implementations from X are inhertited used while the rest are derived
from Y TE
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A hybrid GA using heuristic operators HO1 and HO2 has been developed
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Other aspects of FP
Section outline
54 Other aspects of FP
Complexity considerations for floorplanning
P admissibility
Compactness of placement
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Other aspects of FP Complexity considerations for floorplanning
Complexity considerations for floorplanning
Given a slicing floorplan, the block orientation and sizing can be

done in polynomial time
Block orientation problem for a given general (non-slicing)
floorplan is NP-complete [Optimal orientations of cells in slicing
floorplan designs, L Stockmeyer, Inf. Control, v:57, i:2-3, pp:
91101, 1984]
General problem of identifying an optimal floorplan is NP-complete
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Other aspects of FP
P admissibility
P admissibility
Definition (P admissibility)
Representation is P -admissible if:
The solution space is finite
Every solution is feasible
Packing and cost evaluation can be done in polynomial time
The best evaluated packing in the space corresponds to an
optimal placement
The geometric relation between each pair of modules is defined in
the placement
Example
Non P admissible representations Slicing tree, Normalized Polish
expression, O-tree, B -tree and Corner block list OF
TECHNO
P admissible representations Sequence pair, BSG, and TCG.

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Other aspects of FP Compactness of placement
Compactness of placement
Definition (Compactness of placement)

Assuming that only one block is to be shifted keeping other blocks
fixed, we have the following notions of compactness:
Lcompact if no block can be shifted left
Bcompact if no block can be shifted bottom
LBcompact if both L-compact and B-compact
is minimal area placement, therefore admissible
obtained by sequence of compactions in x-direction
and y-direction with fixed left and bottom edges of
bounding box
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CAD for VLSI

Dept of Computer Sc & Engg

August 16, 2016

Part I: VLSI CAD

Part II: High level synthesis

Part III: Equivalence checking

Part IV: Basic concepts in logic synthesis

Part V: Use of unateness in logic synthesis

Part VI: The Espresso logic synthesis tool OF

Part VII: Multi-level logic synthesis

Part VIII: Partitioning

Part IX: Floorplanning

3 CAD and VLSI

4 VLSI design choices

5 Iterative improvement search TE

Asymtotic upper bound

Definition (Big-O Notation)

Asymtotic upper bound

Definition (Big-O Notation)

Asymtotic upper bound

Definition (Big-O Notation)

Asymtotic upper bound (contd.)

In general T (n) is a complicated function whose behaviour may

Asymtotic upper bound (contd.)

In general T (n) is a complicated function whose behaviour may

Asymtotic upper bound (contd.)

In general T (n) is a complicated function whose behaviour may

Other upper bounds

Definition (Big-omega Notation)

Now f (n) is a lower bound of T (n)

Now f (n) is a tight bound of T (n)

CNF satisfiability (SAT)

F = (vi ; _ vi ; _ : : : _ vi ; ) ^ (vi ; _ vi ; _ : : : _ vi ; ) ^ : : : ^ (vi ; _ vi ; _ : : : _ vi ; )

Example (CNF formula)

Aim is to determine truth assignments of the variables, if possible, to

Can be recast as decision problems yog, km s kOflm^

Example (ND algorithm for SAT)

Both parts take polynomial time, thus SAT is in NP

3-SAT and SAT

From SAT to 3-SAT

3-SAT and SAT (contd.)

Given any SAT formula F , it is possible to construct a 3-SAT

Polynomial time reducibility

Let E be a problem in NP (E 2 NP)

SAT P 3-SAT P Vertex Cover

3 CAD and VLSI

In 1965, Gordon Moore noted that the number of transistors on a chip

Moores Law (contd.)

Models of circuits that need to be used are also becoming more

RTL design flow

netlist manual design/module generator

Library logic minimisation

netlist manual design/module generators

Physical design flow

read NL partitioning region ordering compation

floorplanning placement detailed routing output layout

routing regions global routing costs

Scope of VLSI CAD

Design of electronic systems and semiconductor components are completely

4 VLSI design choices

In Full-custom design most of the components are individually

In Full-custom design most of the components are individually

Standard cell based design

SAT P 3-SAT P Vertex Cover

High temparature random walk