EE660: Computer Architecture Spring, 2017

Assignment No. 2 (Due: Feburary 24, 2017)

Score: /100
Student: Kyle Yu, 24775929Date: February 3, 2017

ADD R5 , R6 , F D XA XA W
R7
SUB R6 , R7 , F D XB XB W
R8
LW R10 , R6 F D XB XB W
(0)
ADDIU R12 , F D XA XA W
R13 , 1
LW R15 , R6 F D XB XB W
(4)
LW R15 , R15 ( F D S XB XB W
4)
ADD R6 , R9 , F D XA XA W
R10
ADDIU R8 , R10 , F D S XB XB W
R11

F D I X0
X1 W
1 F D I
X0
2 F D
I
3 F
D
4 F
We have 4 instructions that need to be killed, 5 excluding BNE. So, for 2 pipelines,
there are 2*4 + 1 = 9 instructions, and for 3 pipelines, there are 3*4 + 2 = 14
instructions.

3.3
1 6 7 12 19 20 21 2
2
1 LD 2-5 DIVD 7-18 LD 8- ADD 1 ADD 20 ADD SUB 2
11 D 3 D I 2

2 MULTD ADDI SD BNZ

This takes 22 cycles.

3.4
1. Should N and N+1 write to the same register or memory, and N replaces N+1,
this is wrong.
2. Should there be an interrupt between N and N+1, N+1 cannot write results
permanently.
2.4

MUL R6 , R7 , Y Y Y Y
F D I W C
R8 0 1 2 3
ADD R9 , R10 , X
F D I W r C
R11 0
ADD R11 , R12 , X
F D I W r C
R13 0
ADD R13 , R14 , X
F D I I W r C
R15 0
ADD R19 , R13 , X
F D D I W r C
R10 0
L L
LW R2 , R3 F F D I W r C
0 1
ADD R12 , X
F D I I W r C
R16 , R19 0
L L
LW R5 , R2 F D D I W C
0 1
ADD R15 , X
F F D I I W C
R20 , R21 0

2.5
0 1 2 3 4 5 6 7 8 9 0 1 2 3 4 5
0MUL R6 , R7 Y Y Y Y
F D I W C
, R8 0 1 2 3
1ADD R9 , X
F D I I I I W C
R6 , R11 0
2MUL R7 , Y Y Y Y
F D D D D I W C
R1 , R2 0 1 2 3
3LW R10 ,
F F F F D I L0 L1 W R C
R12

D I 4 3 2 1 0 Des
t
1 0
2 1 0
3 1 R6
4 1 R6
5 1 R6
6 2 1 1 R6
7 3 2 1 1 R6 R9
8 3 1 1 R9 R7
9 1 1 R7 R10
10 1 1 R7 R10
11 1 1 R7 R10
12 1 R7
13
14
15