I/O Interfacing

What we are going to learn in this

session:
M68230 Parallel Interface Timer.
Registers in the M68230.
Port initialization method.
How M68230 interfaces with various
devices.
Delay subroutine.
The M68230
Parallel
Interface/Timer
M68230 Parallel Interface/Timer
Used by M68000 to communicate with external
devices.
Parallel data transfer.
Has three ports:
Port A, Port B, Port C.
Each port is 8-bits long.
Ports connect to devices.
Ports need to be initialized before used.
M68230 Interfacing

Memory

CS*

MAD
M68k
(LED, Switches, Motor,
7-Segment, Keypad, etc.)
CS*
Port A Device #1
Data Bus
M68230 Port B Device #2

Port C Device #3
How M68230 connects to M68k
D0-D7 D0-D7 PA0-PA7

DTACK* DTACK*

PB0-PB7
R/W* R/W*

CLK CLK
PC0-PC7
RESET* RESET*

A6-A23

MAD CS*

RS1-RS5 (Register select pins)

A1-A5

M68k M68230
M68230 Ports
Registers in M68230
M68230 contains 23 registers.
Each of the registers have a unique address that
refers to them.
To initialize ports, some registers need to be
configured.
Port General Control Register.
Port X Control Register (A, B).
Port X Data Direction Register (A, B, C).
Port X Data Register (A, B, C).
PGCR
Port General Control Register.
Used to set the operation of Port A & Port
B.
You only need to know (and use) Mode 0.
MOVE.B #$00,PGCR
PGCR Settings

PGCR= Mode Description

$00 0 Unidirectional 8-bit transfer (Port A, Port B)

$40 1 Unidirectional 16-bit transfer (Port A + Port B)

Bidirectional 8-bit transfer on

$80 2
Port B, bit I/O on Port A.

$C0 3 Bidirectional 16-bit transfer (Port A + Port B)

Port X Control Register
Used to set buffering of input/output on
PXDR.
Three modes:
Mode 00.
Mode 01.
Mode 1X.
You only need to know (and use) mode
1X.
PXCR Settings

PXCR= Sub-mode Description

$00 00 Double-buffered input

$40 01 Double-buffered output

$80 1X Bit I/O

Port X Data Direction Register
Used to specify the direction of data
transfer for each bit in the port.
Two states:
If PXDDR bit = 0, will be set as input.
If PXDDR bit = 1, will be set as output.
Port X Data Register
Contains the data sent/received to/from
devices.
Each PXDR carries 8-bits of data.
There are three data registers in the
M68230: PADR, PBDR, PCDR.
Port Initialization
To perform port initialization:
Assign the register addresses to a unique
name.
PGCR must be set to #$00.
PXCR must be set to #$80.
Set PXDDR to input or output.
Port Initialization Example
Port Address START ORG $XXXXXX
PGCR EQU $A00001
PGCR $A00001 PACR EQU $A0000D
PACR $A0000D PBCR EQU $A0000F
PADDR EQU $A00005
PBCR $A0000F PBDDR EQU $A00007
PADDR $A00005 PCDDR EQU $A00009
PADR EQU $A00011
PBDDR $A00007 PBDR EQU $A00013
PCDDR $A00009 PCDR EQU $A00019

PADR $A00011 MOVE.B #$00,PGCR

PBDR $A00013 MOVE.B #$80,PACR/PBCR
MOVE.B #$XX,PADDR/PBDDR/PCDDR
PCDR $A00019 (DEPENDING ON THE H/W)
68230 Interfacing
M68230 Interfacing
M68230 interfacing is similar to memory
interfacing in last chapter.
Instead of interfacing memory, M68230 is
interfaced.
A1-A5 is reserved for M68230, the rest
used for decoder.
Example: Full Decoding
Interface M68230 with M68k so that its
base address is $A50000.
Discussion
For M68230 interfacing, 5 lines are
automatically reserved for M68230.
 Step 1: Allocate Address Line

A23 A22 A21 A20 A19 A18 A17 A16 A15 A14 A13 A12 A11 A10 A9 A8 A7 A6 A5 A4 A3 A2 A1 A0

X X X X X

5 lines allocated

UDS/LDS
(reserved)
 Step 2: Set Base Address

A23 A22 A21 A20 A19 A18 A17 A16 A15 A14 A13 A12 A11 A10 A9 A8 A7 A6 A5 A4 A3 A2 A1 A0

1 0 1 0 0 1 0 1 0 0 0 0 0 0 0 0 0 0 X X X X X

A 5 0 0

UDS/LDS
(reserved)
 Step 3: Find Lower Range

A23 A22 A21 A20 A19 A18 A17 A16 A15 A14 A13 A12 A11 A10 A9 A8 A7 A6 A5 A4 A3 A2 A1 A0

1 0 1 0 0 1 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

A 5 0 0 0 0
 Step 4: Find Upper Range

A23 A22 A21 A20 A19 A18 A17 A16 A15 A14 A13 A12 A11 A10 A9 A8 A7 A6 A5 A4 A3 A2 A1 A0

1 0 1 0 0 1 0 1 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1

A 5 0 0 3 F
 Step 5: Design Decoder
A23 A22 A21 A20 A19 A18 A17 A16 A15 A14 A13 A12 A11 A10 A9 A8 A7 A6

1 0 1 0 0 1 0 1 0 0 0 0 0 0 0 0 0 0

A 5 0 0

SELIO*
NAND

NAND

NAND
A23 A16 A15 A8 A7 A6 AS*
Memory Block Diagram
$000000

unused

$A50000 (Lower Range)

Interfaced with M68k (M68230 I/O)

$A5003F (Upper Range)

unused

$FFFFFF
Sample Programs
LEDs & Switches
Example 1
 Example 1: Set LED
M68230
A set of LEDs are connected to LED0
PB0
Port B in M68230. Write a program
that turns on LED3 and LED4, and PB1 LED1
turns off the rest.
PB2 LED2
Port Address

PGCR $800001
PB3 LED3
PACR $800005

PB4 LED4
PBCR $800007

PADDR $800009 LED5

PB5
PBDDR $80000D
LED6
PCDDR $80000F PB6
PADR $800011
LED7
PBDR $800013
PB7
PCDR $800019
Discussion
Port B should be initialized before being
used.
To turn on LED, the voltage at Port B bits
should be high.
To turn off LED, the voltage at Port B
should be low.
LED Operation

A B

A B LED

0 0 Zero biased (OFF)

0 1 Reverse biased (OFF)

1 0 Forward biased (ON)

1 1 Zero biased (OFF)

Solution
START ORG $1000
PGCR EQU $800001
PBCR EQU $800007
PBDDR EQU $80000D
PBDR EQU $800013

INIT MOVE.B #$00,PGCR

MOVE.B #$80,PBCR
MOVE.B #$FF,PBDDR
ONLED MOVE.B #%00011000,PBDR

END START
Example 1: Set LED
M68230
0 LED0
PB0

PB1 0 LED1

0 LED2
PB2

PB3 1 LED3

1 LED4
PB4
0 LED5
PB5
0 LED6
PB6
0 LED7
PB7
Example 2
Example 2: Read Switches &
Output to LED
A set of switches are connected to Port A,
and a set of LEDs are connected to Port B
in M68230. Write a program that reads
the value in the switches and turns on the
respective LEDs.
Switch Operation
+5V

Switch A

OPEN 0

A CLOSE 1

R
Switch Operation
+5V

R
Switch A
A
OPEN 1

CLOSE 0
Circuit Diagram
+5V

M68230
LED0
PA0 PB0
R

PA1 PB1 LED1

R

PA2 PB2 LED2

R

PA3 PB3 LED3

R

PA4 PB4 LED4

R
LED5
PA5 PB5
R
LED6
PA6 PB6
R
LED7
PA7 PB7
R
Port Assignments
Port Address
PGCR $A00001
PACR $A0000D
PBCR $A0000F
PADDR $A00005
PBDDR $A00007
PCDDR $A00009
PADR $A00011
PBDR $A00013
PCDR $A00019
Discussion
Both Port A & B should be initialized
before being used.
When the switch is OPEN, 5V is passed to
M68230 (logic high).
When the switch is CLOSE, 0V is passed
to M68230 (logic low).
Solution Initialize Ports
INIT MOVE.B #$00,PGCR
MOVE.B #$80,PACR
MOVE.B #$80,PBCR
MOVE.B #$00,PADDR
MOVE.B #$FF,PBDDR
Solution Solve Problem
LOOP MOVE.B PADR,D0
MOVE.B D0,PBDR
BRA LOOP
Solution Complete Program
START ORG $1000
PGCR EQU $A00001
PACR EQU $A0000D
PBCR EQU $A0000F
PADDR EQU $A00005
PBDDR EQU $A00007
PADR EQU $A00011
PADR EQU $A00013

INIT MOVE.B #$00,PGCR

MOVE.B #$80,PACR
MOVE.B #$80,PBCR
MOVE.B #$00,PADDR
MOVE.B #$FF,PBDDR

LOOP MOVE.B PADR,D0

MOVE.B D0,PBDR
BRA LOOP

END START
Sample Output
+5V

M68230
0 LED0
PA0 PB0
R

PA1 PB1 1 LED1

R
1 LED2
PA2 PB2
R
0 LED3
PA3 PB3
R
1 LED4
PA4 PB4
R
1 LED5
PA5 PB5
R
0 LED6
PA6 PB6
R
1 LED7
PA7 PB7
R

PADR D0 PBDR
7-Segment
7-Segment
Consists of 7-LEDs
arranged together.
Can display numbers and
characters.
Each segment is marked
with a letter (a to g).
To display characters,
need to turn on/off certain
segments.
Also has E (enable) pin to
turn on/off 7-segment.
Interfacing 7-Segment with M68230

To interface with M68230, each segment

(a to g) is connected to a port in M68230.
The E signal must also be connected to a
port to enable/disable the 7-segment.
7-Segment Types
There are two types of 7-segment
displays:
Common cathode.
Common anode.

Each type differs in how they behave with

certain inputs.
Common Cathode 7-Segment
Input (from M68230)

E Input Output
0 0 OFF
0 1 ON
1 0 OFF
1 1 ON
Example: Interfacing CC 7-Segment
with M68230 (No Transistor)
a
M68230 B0
b
B1
c
B2

B3 d

B4 e

B5 f

B6 g

B7 E

(Common cathode)

To turn on the 7-segment, E must be set to 0,

and the input to be turned on must be set to 1.
Example: Interfacing CC 7-Segment
with M68230 (With Transistor)
a
M68230 B0
b
B1
c
B2

B3 d

B4 e

B5 f

B6 g

B7
E

(Common cathode)
To turn on the 7-segment, R

E must be set to 1,
and the input to be turned on
must be set to 1.
By setting E to 1, the transistor is
turned ON, providing a
path to GND.
Displaying Numbers: CC7S (No Transistor)
E a b c d e f g Number
1 X X X X X X X None
0 1 1 0 0 0 0 0 1
0 1 1 0 1 1 0 1 2
0 1 1 1 1 0 0 1 3
0 0 1 1 0 0 1 1 4
0 1 0 1 1 0 1 1 5
0 0 0 1 1 1 1 1 6
0 1 1 1 0 0 0 0 7
0 1 1 1 1 1 1 1 8
0 1 1 1 0 0 1 1 9
0 1 1 1 1 1 1 0 0
Displaying Numbers: CC7S (with Transistor)
E a b c d e f g Number
0 X X X X X X X None
1 1 1 0 0 0 0 0 1
1 1 1 0 1 1 0 1 2
1 1 1 1 1 0 0 1 3
1 0 1 1 0 0 1 1 4
1 1 0 1 1 0 1 1 5
1 0 0 1 1 1 1 1 6
1 1 1 1 0 0 0 0 7
1 1 1 1 1 1 1 1 8
1 1 1 1 0 0 1 1 9
1 1 1 1 1 1 1 0 0
Common Anode 7-Segment
E

Input (to M68230)

E Input Output
0 0 OFF
0 1 OFF
1 0 ON
1 1 OFF
Example: Interfacing CA 7-Segment
with M68230
a
M68230 B0
b
B1
c
B2

B3 d

B4 e

B5 f

B6 g

B7 E

(Common anode)

To turn on the 7-segment, E must be set to 1,

and the input to be turned on must be set to 0.
Displaying Numbers: CA7S (No Transistor)
E a b c d e f g Number
0 X X X X X X X None
1 0 0 1 1 1 1 1 0
1 0 0 1 0 0 1 0 1
1 0 0 0 0 1 1 0 3
1 1 0 0 1 1 0 0 4
1 0 1 0 0 1 0 0 5
1 1 1 0 0 0 0 0 6
1 0 0 0 1 1 1 1 7
1 0 0 0 0 0 0 0 8
1 0 0 0 1 1 0 0 9
1 0 0 0 0 0 0 1 1
Example 1
 Example: Displaying C on 7-Seg
a=1
M68230 B0
b=0
B1
c=0
B2

B3 d=1

B4 e=1

B5 f=1

B6 g=0

B7
E=1

(Common cathode)
R
MOVE.B #$00,PGCR
MOVE.B #$80,PBCR
MOVE.B #$FF,PBDDR
ULANG MOVE.B #$B9,PBDR
BRA ULANG
Displaying More Numbers/Characters

7-Segments can also be grouped together

to display multiple numbers/characters.
Usually done using a technique called
multiplexing.
 Interfacing 2 7-Segments with
M68230
a a
M68230 B0
b b
B1
c c
B2

B3 d d

B4 e e

B5 f f

B6 g g

B7

(Common cathode)
E1
A0

A1
E2
Example 2
Example: Displaying on Multiple 7-Segs

Write a program to display 12 on 2 7-

Segment displays. The circuit diagram is
shown.
 Example: Displaying 12 on 2 7-Segments
a a
M68230 B0
b b
B1
c c
B2

B3 d d

B4 e e

B5 f f

B6 g g

B7

(Common cathode)
E1
A0

A1
E2
Step 1: Init Ports
MOVE.B #$00,PGCR
MOVE.B #$80,PACR
MOVE.B #$80,PBCR
MOVE.B #$FF,PADDR
MOVE.B #$FF,PBDDR
Step 2: Activate E2, Send First Number

MOVE.B #$01,PADR * activate E2

MOVE.B #$5B,PBDR * display 2
BSR DELAY * delay for a while to
* allow 7-seg to
* turn on.
Example: Displaying 12 on 2 7-Segments
a a
B0=1
b b
B1=1
c c
B2=0

B3=1
d d
B4=1
e OFF e
B5=0
f f
B6=1
g g
B7

(Common cathode)
E1 = 1 (off)
A0

A1
E2 = 0 (on)

M68230
Step 2: Activate E1, Send Second Number

MOVE.B #$02,PADR * activate E1

MOVE.B #$06,PBDR * display 1
BSR DELAY * delay for a while to
* allow 7-seg to
* turn on.
Example: Displaying 12 on 2 7-Segments
a a
B0=0
b b
B1=1
c c
B2=1

B3=0
d d
B4=0
e e OFF
B5=0
f f
B6=0
g g
B7

(Common cathode)
E1 = 0 (on)
A0

A1
E2 = 1 (off)

M68230
Step 3: Activate E2 Back, Send First Number
Again

MOVE.B #$01,PADR * activate E2

MOVE.B #$5B,PBDR * display 2
BSR DELAY * delay for a while to
* allow 7-seg to
* turn on.
Example: Displaying 12 on 2 7-Segments
a a
B0=1
b b
B1=1
c c
B2=0

B3=1
d d
B4=1
e OFF e
B5=0
f f
B6=1
g g
B7

(Common cathode)
E1 = 0 (off)
A0

A1
E2 = 1 (on)

M68230
Discussion
Using multiplexing, only one digit may be
turned on at one time.
But, if the delay is fast enough (<100ms),
our eyes wont be able to catch the
change.
 Example: Displaying 12 on 2 7-Segments
a a
M68230 B0
b b
B1
c c
B2

B3 d d

B4 e e

B5 f f

B6 g g

B7

(Common cathode)
E1
A0

A1
E2
Complete Program
ORG $080C00
INIT MOVE.B #$00,PGCR
DELAY MOVE.L #50,D7 MOVE.B #$80,PACR
DELLOOP SUB.L #1,D7 MOVE.B #$80,PBCR
CMP.L #0,D7 MOVE.B #$03,PADDR
BNE DELLOOP MOVE.B #$7F,PBDDR
RTS
BEGIN MOVE.B #$01,PADR
MOVE.B #$5B,PBDR
START ORG $080D00 BSR DELAY

PGCR EQU $100001 MOVE.B #$02,PADR

PADDR EQU $100005 MOVE.B #$06,PBDR
PBDDR EQU $100007 BSR DELAY
PCDDR EQU $100009
PADR EQU $100011 BRA BEGIN
PBDR EQU $100013
PCDR EQU $100019 END START
PACR EQU $10000D
PBCR EQU $10000F
Example 2
Example: Displaying on 5 7-Segs.

A set of 7-segment displays are connected

on Port A and Port B in M68230. Write a
program to display the message HELLO
on the 7-segment display.
Circuit Diagram
M68230
R
A0
A1
A2
A3
A4
A5
A6
A7
R
B0
B1
B2
E4 E3 E2 E1 E0
B3
B4
B5
B6
B7
Algorithm
Turn on E4,
Display H.
Delay for a while.
Turn on E3,
Display E.
Delay for a while.
Turn on E2,
Display L.
Delay for a while.
Turn on E1,
Display L.
Delay for a while.
Turn on E0,
Display O.
Delay for a while.
Do E4 again.
Character H
A=0
B=1
C=1 MOVE.B #%01110110,PBDR
D=0
E=1 OR
F=1
G=1 MOVE.B #$76,PBDR
Character E
A=1
B=0
C=0 MOVE.B #%01111001,PBDR
D=1
E=1 OR
F=1
G=1 MOVE.B #$79,PBDR
Character L
A=1
B=0
C=0 MOVE.B #%00111001,PBDR
D=1
E=1 OR
F=1
G=0 MOVE.B #$39,PBDR
Character H
A=1
B=1
C=1 MOVE.B #%00111111,PBDR
D=1
E=1 OR
F=1
G=0 MOVE.B #$3F,PBDR
Program
ORG $080C00 HELLO MOVE.B #$0F,PADR * ACTIVATE E4
MOVE.B #$76,PBDR * DISPLAY H
DELAY MOVE.L #50,D7 * 80 MS DELAY BSR DELAY
DELLOOP SUB.L #1,D7
CMP.L #0,D7 MOVE.B #$17,PADR * ACTIVATE E3
BNE DELLOOP MOVE.B #$79,PBDR * DISPLAY E
RTS BSR DELAY

MOVE.B #$1B,PADR * ACTIVATE E2

START ORG $080D00 MOVE.B #$39,PBDR * DISPLAY L
BSR DELAY
PGCR EQU $100001
PADDR EQU $100005 MOVE.B #$1D,PADR * ACTIVATE E1
PBDDR EQU $100007 MOVE.B #$39,PBDR * DISPLAY L
PADR EQU $100011 BSR DELAY
PBDR EQU $100013
PACR EQU $10000D MOVE.B #$1E,PADR * ACTIVATE E0
PBCR EQU $10000F MOVE.B #$3F,PBDR * DISPLAY O
BSR DELAY
INIT MOVE.B #$00,PGCR
MOVE.B #$80,PACR BRA HELLO
MOVE.B #$80,PBCR
MOVE.B #$FF,PADDR END START
MOVE.B #$FF,PBDDR
7-Segment + BCD
Decoder
7-Segment + BCD Decoder
A BCD 7-Segment decoder can be
used to simplify the interface to M68230.
Just send a BCD number, and it will be
automatically displayed at 7-segment.
Also reduces the number of connections
required to display 7-segment values.
 Example: 7-Segment + BCD
Decoder
a a
M68230 B0
b b
B1
c c
B2
BCD
B3 d d
7-Seg
e e
B4 Decoder
B5 f f

B6 g g

B7

(Common cathode)
E1
A0

A1
E2
BCD Decoder I/O
B3 B2 B1 B0 Number
0 0 0 1 1
0 0 1 0 2
0 0 1 1 3
0 1 0 0 4
0 1 0 1 5
0 1 1 0 6
0 1 1 1 7
1 0 0 0 8
1 0 0 1 9
0 0 0 0 0
Example 3
Displaying 12 on 7-Segments
A circuit is wired as in the next figure.
Write a program that displays 12 on the
7-Segment.
 Example: 7-Segment + BCD
Decoder
a a
M68230 B0
b b
B1
c c
B2
BCD
B3 d d
7-Seg
e e
B4 Decoder
B5 f f

B6 g g

B7

(Common cathode)
E1
A0

A1
E2
Step 1: Init Ports
MOVE.B #$00,PGCR
MOVE.B #$80,PACR
MOVE.B #$80,PBCR
MOVE.B #$FF,PADDR
MOVE.B #$FF,PBDDR
Step 2: Activate E2, Send First Number

MOVE.B #$01,PADR * activate E2

MOVE.B #$02,PADR * display 2
BSR DELAY * delay for a
* while to allow 7-seg
* to turn on.
Example: Displaying 12 on 2 7-Segments
a
a
B0=0
b
b
B1=1
c
c
B2=0
BCD
B3=0 d
7-Seg d
B4 Decoder e OFF e
B5 f
f
B6 g
g
B7

(Common cathode)
E1 = 1 (off)
A0

A1
E2 = 0 (on)

M68230
Step 2: Activate E1, Send Second Number

MOVE.B #$02,PADR * activate E1

MOVE.B #$01,PADR * display 1
BSR DELAY * delay for a while
* to allow 7-seg
* to turn on.
Example: Displaying 12 on 2 7-Segments
a
a
B0=0
b
b
B1=1
c
c
B2=1
BCD
B3=0 d
7-Seg d
B4=0 Decoder e
e OFF
B5=0 f
f
B6=0 g
g
B7

(Common cathode)
E1 = 0 (on)
A0

A1
E2 = 1 (off)

M68230
Step 4: Activate E2 Back, Send First Number
Again

MOVE.B #$01,PADR * activate E2

MOVE.B #$02,PADR * display 2
BSR DELAY * delay for a
* while to allow 7-seg
* to turn on.
Example: Displaying 12 on 2 7-Segments
a
a
B0=0
b
b
B1=1
c
c
B2=0
BCD
B3=0 d
7-Seg d
B4 Decoder e OFF e
B5 f
f
B6 g
g
B7

(Common cathode)
E1 = 1 (off)
A0

A1
E2 = 0 (on)

M68230
Discussion
Using multiplexing, only one digit may be
turned on at one time.
But, if the delay is fast enough (<100ms),
our eyes wont be able to catch the
change.
 Example: Displaying 12 on 2 7-Segments
a a
M68230 B0
b b
B1
c c
B2
BCD
B3 d d
7-Seg
e e
B4 Decoder
B5 f f

B6 g g

B7

(Common cathode)
E1
A0

A1
E2
Complete Program
ORG $080C00
INIT MOVE.B #$00,PGCR
DELAY MOVE.L #50,D7 MOVE.B #$80,PACR
DELLOOP SUB.L #1,D7
CMP.L #0,D7 MOVE.B #$80,PBCR
BNE DELLOOP MOVE.B #$FF,PADDR
RTS MOVE.B #$FF,PBDDR
BEGIN MOVE.B #$01,PADR
MOVE.B #$02,PBDR
START ORG $080D00 BSR DELAY
MOVE.B #$02,PADR
PGCR EQU $100001 MOVE.B #$01,PBDR
PADDR EQU $100005 BSR DELAY
PBDDR EQU $100007 BRA BEGIN
PCDDR EQU $100009
PADR EQU $100011 END START
PBDR EQU $100013
PCDR EQU $100019
PACR EQU $10000D
PBCR EQU $10000F
DC Motor
Controlling DC Motors
Has two terminals (positive/negative),
connected to DC voltage.
If positive voltage applied at positive
terminal, motor moves clockwise.
If negative voltage applied at positive
terminal, motor moves anti-clockwise.
 DC Motor
+12V +12V

+ - + -

+ with + = clockwise + with - = anti-clockwise

Interfacing DC Motor with M68230
Single Direction
+12V

M68230
R
A0
+
A1

A2 - MOVE.B #$00,PGCR
A3 R MOVE.B #$80,PACR
A4
MOVE.B #$FF,PADDR
MOVE.B #$10,PADR
A5

A6
R
A7
 Interfacing DC Motor with M68230 (Two Directions)

+12V

R
R

R R
T1 T2
A0 A2
+

-
R R

A1 T4 T3 A3

PNP transistors are

turned on by 0 at base.
NPN transistors are
turned on by 1 at base.
Moving the Motor Clockwise
MOVE.B #$00,PGCR
MOVE.B #$80,PACR
MOVE.B #$FF,PADDR
MOVE.B #%00001100,PADR
(Turn on T1 and T3)
 Interfacing DC Motor with M68230 (Clockwise)

+12V

R
R

0 1 R R 0 1
T1 T2
A0 A2
+

1 0 R R 1 0
A1 T4 T3 A3

Positive meets positive, clockwise direction

Moving the Motor Anti-clockwise
MOVE.B #$00,PGCR
MOVE.B #$80,PACR
MOVE.B #$FF,PADDR
MOVE.B #%00000011,PADR
(Turn on T2 and T4)
 Interfacing DC Motor with M68230 (Anti-clockwise)

+12V

R
R

1 0 R R
1 0
T1 T2
A0 A2
+

0 1 R R 0 1
A1 T4 T3 A3

Positive meets negative, anti-clockwise direction

Keypad
Keypad
A set of switches.
CPU determines what button pressed by
scanning each column in turn.
Need to be de-bounced after each key
press:
Done using de-bouncing subroutine.
Keypad
P0 P1 P2

1 2 3
P4

4 5 6
P5

7 8 9
P6

* 0 # P7
Step 1: Initialization
Lets say Port A is connected to keypad.
MOVE.B #$00,PGCR
MOVE.B #$80,PACR
MOVE.B #$0F,PADDR
Step 2 Scan 1st Column
P0=1 P1 P2

1 2 3
P4

4 5 6
P5

7 8 9
P6

* 0 # P7
Step 2: Scan 1st Column
COL1 BCLR.B #1,PBDR IS4 MOVE.B #4,D0
BCLR.B #2,PBDR BSR WAIT
BSET.B #0,PBDR
MOVE.B #9,D3
MOVE.B PBDR,D1 TRAP #0
AND.B #$F0,D1 BRA COL1
CMP.B #$10,D1
BEQ IS1 IS7 MOVE.B #7,D0
CMP.B #$20,D1 BSR WAIT
BEQ IS4
MOVE.B #9,D3
CMP.B #$40,D1
BEQ IS7 TRAP #0
CMP.B #$80,D1 BRA COL1
BEQ ISSTAR
BNE COL2 ISSTAR MOVE.B #$00,D0
BSR WAIT
IS1 MOVE.B #1,D0
MOVE.B #9,D3
BSR WAIT
MOVE.B #9,D3 TRAP #0
TRAP #0 BRA COL1
BRA COL1

* MOVE.B #9,D3 and TRAP #0 are used as an example to display

the output to screen. Replace it with your own code.
Step 3 Scan 2nd Column
P0 P1=1 P2

1 2 3
P4

4 5 6
P5

7 8 9
P6

* 0 # P7
Step 3: Scan 2nd Column
COL2 BCLR.B #0,PBDR IS5 MOVE.B #5,D0
BCLR.B #2,PBDR BSR WAIT
BSET.B #1,PBDR MOVE.B #9,D3
MOVE.B PBDR,D1 TRAP #0
AND.B #$F0,D1 BRA COL1
CMP.B #$10,D1
BEQ IS2 IS8 MOVE.B #8,D0
CMP.B #$20,D1 BSR WAIT
BEQ IS5 MOVE.B #9,D3
CMP.B #$40,D1 TRAP #0
BEQ IS8 BRA COL1
CMP.B #$80,D1
BEQ IS0 IS0 MOVE.B #0,D0
BNE COL3 BSR WAIT
MOVE.B #9,D3
IS2 MOVE.B #2,D0 TRAP #0
BSR WAIT BRA COL1
MOVE.B #9,D3
TRAP #0
BRA COL1
Step 4 Scan 3rd Column
P0 P1 P2=1

1 2 3
P4

4 5 6
P5

7 8 9
P6

* 0 # P7
Step 4: Scan 3rd Column
COL3 BCLR.B #0,PBDR IS6 MOVE.B #6,D0
BCLR.B #1,PBDR BSR WAIT
BSET.B #2,PBDR MOVE.B #9,D3
MOVE.B PBDR,D1 TRAP #0
AND.B #$F0,D1 BRA COL1
CMP.B #$10,D1
BEQ IS3 IS9 MOVE.B #9,D0
CMP.B #$20,D1 BSR WAIT
BEQ IS6 MOVE.B #9,D3
CMP.B #$40,D1 TRAP #0
BEQ IS9 BRA COL1
CMP.B #$80,D1
BEQ ISHASH ISHASH MOVE.B #0,D0
BNE COL1 BSR WAIT
MOVE.B #9,D3
IS3 MOVE.B #3,D0 TRAP #0
BSR WAIT BRA COL1
MOVE.B #9,D3
TRAP #0
BRA COL1
Complete Program
ORG $080C00 COL1BCLR.B #1,PBDR ISSTAR MOVE.B
BCLR.B #2,PBDR #$00,D0
DELAY MOVE.B #$1F,D4 BSET.B #0,PBDR BSR WAIT
NEXTDEL SUB.B #1,D4 MOVE.B PBDR,D1 MOVE.B #9,D3
BNE NEXTDEL AND.B #$F0,D1 TRAP #0
CMP.B #$10,D1 BRA COL1
WAIT MOVE.B PBDR,D2 BEQ IS1 END
AND.B #$F0,D2 CMP.B #$20,D1 START
CMP.B #$00,D2 BEQ IS4
BNE WAIT CMP.B #$40,D1 COL2BCLR.B #0,PBDR
RTS BEQ IS7 BCLR.B #2,PBDR
CMP.B #$80,D1 BSET.B #1,PBDR
BEQ ISSTAR MOVE.B PBDR,D1
START ORG $080D00 AND.B #$F0,D1
BNE COL2 CMP.B #$10,D1
PGCR EQU $100001 BEQ IS2
PACR EQU $10000D IS1 MOVE.B #1,D0 CMP.B #$20,D1
PBCR EQU $10000F BSR WAIT BEQ IS5
MOVE.B #9,D3 CMP.B #$40,D1
PADDR EQU $100005 TRAP #0 BEQ IS8
PBDDR EQU $100007 BRA COL1 CMP.B #$80,D1
PCDDR EQU $100009 BEQ IS0
PADR EQU $100011 IS4 MOVE.B #4,D0 BNE COL3
PBDR EQU $100013 BSR WAIT
PCDR EQU $100019 MOVE.B #9,D3 IS2 MOVE.B #2,D0
TRAP #0 BSR WAIT
BRA COL1 MOVE.B #9,D3
INIT MOVE.B #$00,PGCR TRAP #0
MOVE.B #$80,PACR IS7 MOVE.B #7,D0 BRA COL1
MOVE.B #$80,PBCR BSR WAIT
MOVE.B #$0F,PBDDR MOVE.B #9,D3
MOVE.B #$00,PBDR TRAP #0
BRA COL1
Complete Program
IS5 MOVE.B #5,D0 IS3 MOVE.B #3,D0
BSR WAIT BSR WAIT
MOVE.B #9,D3 MOVE.B #9,D3
TRAP #0 TRAP #0
BRA COL1 BRA COL1
IS8 MOVE.B #8,D0
BSR WAIT IS6 MOVE.B #6,D0
MOVE.B #9,D3 BSR WAIT
TRAP #0 MOVE.B #9,D3
BRA COL1 TRAP #0
BRA COL1
IS0 MOVE.B #0,D0
BSR WAIT IS9 MOVE.B #9,D0
MOVE.B #9,D3 BSR WAIT
TRAP #0 MOVE.B #9,D3
BRA COL1 TRAP #0
BRA COL1
COL3BCLR.B #0,PBDR
BCLR.B #1,PBDR ISHASH MOVE.B #0,D0
BSET.B #2,PBDR BSR WAIT
MOVE.B PBDR,D1 MOVE.B #9,D3
AND.B #$F0,D1 TRAP #0
CMP.B #$10,D1 BRA COL1
BEQ IS3
CMP.B #$20,D1
BEQ IS6
CMP.B #$40,D1
BEQ IS9
CMP.B #$80,D1
BEQ ISHASH
BNE COL1
Example
Example 4 Pressed
P0 P1 P2

1 2 3
P4

4 5 6
P5

7 8 9
P6

* 0 # P7
Step 2: Scan 1st Column
COL1 BCLR.B #1,PBDR IS4 MOVE.B #4,D0
BCLR.B #2,PBDR BSR WAIT
BSET.B #0,PBDR
MOVE.B #9,D3
MOVE.B PBDR,D1 TRAP #0
AND.B #$F0,D1 BRA COL1
CMP.B #$10,D1
BEQ IS1 IS7 MOVE.B #7,D0
CMP.B #$20,D1 BSR WAIT
BEQ IS4
MOVE.B #9,D3
CMP.B #$40,D1
BEQ IS7 TRAP #0
CMP.B #$80,D1 BRA COL1
BEQ ISSTAR
BNE COL2 ISSTAR MOVE.B #$00,D0
BSR WAIT
IS1 MOVE.B #1,D0
MOVE.B #9,D3
BSR WAIT
MOVE.B #9,D3 TRAP #0
TRAP #0 BRA COL1
BRA COL1
Example 8 Pressed
P0 P1 P2

1 2 3
P4

4 5 6
P5

7 8 9
P6

* 0 # P7
Step 3: Scan 2nd Column
COL2 BCLR.B #0,PBDR IS5 MOVE.B #5,D0
BCLR.B #2,PBDR BSR WAIT
BSET.B #1,PBDR MOVE.B #9,D3
MOVE.B PBDR,D1 TRAP #0
AND.B #$F0,D1 BRA COL1
CMP.B #$10,D1
BEQ IS2 IS8 MOVE.B #8,D0
CMP.B #$20,D1 BSR WAIT
BEQ IS5 MOVE.B #9,D3
CMP.B #$40,D1 TRAP #0
BEQ IS8 BRA COL1
CMP.B #$80,D1
BEQ IS0 IS0 MOVE.B #0,D0
BNE COL3 BSR WAIT
MOVE.B #9,D3
IS2 MOVE.B #2,D0 TRAP #0
BSR WAIT BRA COL1
MOVE.B #9,D3
TRAP #0
BRA COL1
Example 6 Pressed
P0 P1 P2

1 2 3
P4

4 5 6
P5

7 8 9
P6

* 0 # P7
Step 4: Scan 3rd Column
COL3 BCLR.B #0,PBDR IS6 MOVE.B #6,D0
BCLR.B #1,PBDR BSR WAIT
BSET.B #2,PBDR MOVE.B #9,D3
MOVE.B PBDR,D1 TRAP #0
AND.B #$F0,D1 BRA COL1
CMP.B #$10,D1
BEQ IS3 IS9 MOVE.B #9,D0
CMP.B #$20,D1 BSR WAIT
BEQ IS6 MOVE.B #9,D3
CMP.B #$40,D1 TRAP #0
BEQ IS9 BRA COL1
CMP.B #$80,D1
BEQ ISHASH ISHASH MOVE.B #0,D0
BNE COL1 BSR WAIT
MOVE.B #9,D3
IS3 MOVE.B #3,D0 TRAP #0
BSR WAIT BRA COL1
MOVE.B #9,D3
TRAP #0
BRA COL1
Delay Subroutine
Delay Subroutine
In some applications, we may need to delay the
output before executing next instruction.
Can be achieved using delay subroutine:
Does some meaningless repetitive task over and
over.
Wastes processing time of M68k.
Can be set to repeat until desired delay is achieved.
Delay Subroutine Example
DELAY MOVE.L #xxx,Dn
LOOP SUB.L #1,Dn
CMP.L #0,Dn
BNE LOOP
RTS
 Calculating The Delay
To calculate delay, you need to know the
time required to execute each instruction:

Instruction Clock Cycles to Complete Time (M68k @10MHz)

MOVE.L 12 0.0000012s
Executed n times.

SUB.L 16 0.0000016s

CMP.L 14 0.0000014s

BNE 10 0.0000010s

RTS 16 0.0000016s

M68k @ 10MHz T = 1/10MHz = 1x10-7secs.

Calculating the Delay M68k 10MHz

For 1 sec., 10,000,000 clock cycles are

required.
10,000,000 = 12 + 16 + (16 + 14 + 10)n

10,000,000 = 28 + 40n

n = (10,000,000 28)/40

n = (10,000,000 28)/40 = 249,999

Delay Subroutine Example 1s
DELAY MOVE.L #249999,D6
LOOP SUB.L #1,D6
CMP.L #0,D6
BNE LOOP
RTS
 Calculating The Delay 0.25s
To calculate delay, you need to know the
time required to execute each instruction:

Instruction Clock Cycles to Complete Time (M68k @10MHz)

MOVE.L 12 0.0000012s
Executed n times.

SUB.L 16 0.0000016s

CMP.L 14 0.0000014s

BNE 10 0.0000010s

RTS 16 0.0000016s

M68k @ 10MHz T = 1/10MHz = 1x10-7secs.

Calculating the Delay
For 0.25 sec., 2,500,000 clock cycles are
required.
2,500,000 = 12 + 16 + (16 + 14 + 10)n

2,500,000 = 28 + 40n

n = (2,500,000 28)/40

n = (2,500,000 28)/40 = 62,499

Delay Subroutine Example 0.25s

DELAY MOVE.L #62499,D6

LOOP SUB.L #1,D6
CMP.L #0,D6
BNE LOOP
RTS
Implementing Delay
START ORG $090000
INIT MOVEA.L #$100001,A6 * base address of pi/t
MOVE.B #$80,$E(A6) * configure port B control reg to mode 1x
MOVE.B #$FF,$6(A6) * configure port B data reg to o/p

LOOP MOVE.B #$FF,$100013

Turn on all LEDs,
BSR DELAY
Wait 1 second,
MOVE.B #$00,$100013
Turn off all LEDs,
BSR DELAY
Wait 1 second.
BRA LOOP

DELAY MOVE.L #249999,D7

DELLOOP SUB.L #1,D7
CMP.L #0,D7
BNE DELLOOP
RTS

END START
Conclusion
Conclusion
The M68230 is a parallel interface used by
M68k to connect with various devices.
The M68230 has three ports, which can be
configured to interface with many devices.
To use the ports, it MUST be initialized
first.
Conclusion
The delay subroutine is used to waste
the CPUs time by telling it to do repetitive
tasks.
The delay format is basically the same,
just adjust the counter to get the delay you
want.
The End

Please read:
Antonakos, pg. 352-366
M68230 Datasheet