BITS-Pilani K.K.
Birla Goa Campus
VLIW architectures: a survey of some popular
VLIW processors
Sreekesh S, Kiran Shinde, Abuturab Muhhammadi, Shubham Jain, Abhinav Gupta
AbstractVLIW architecture was conceived in the late 70s
and early 80s as a solution for achieving high performance
computing. Whereas other architectures like superscalar
processors rely on complicated hardware for scheduling
instructions on processors, VLIW leverages the compiler for
doing the same. In state-of-the-art, VLIW can be seen in several
DSP processors. However VLIW didnt stand out in test of time,
as several better architectures were proposed eventually. The
paper presents the milestones that led to VLIW and explores the
architectural features of popular CPUs ELI-512, Cedra, Intel
Italium.
Index Terms VLIW, IA-64, ELI-512, Cedra5, Software
pipelining, Trace Compiler
I. INTRODUCTION
architecture community in the late 1970s and
C OMPUTER
early 1980s believed that the intrinsic parallelism in
object code was limited due to branches and dependencies in
code. This was well established by the studies of Tjaden and
Flynn. Parallelism was limited because after a few lines of
codes (called the basic block) a branch instruction would be
hit, and within the parallel block there may be true data
dependencies.
John Fisher, a professor of University of Illinois, Urbana
Champaign was instrumental in developing VLIW
architecture by not sticking to this fundamental assumption.
One of Fishers key insights was that if those basic blocks are
too short to afford much parallelism, perhaps there was a way
to artificially lengthen them by hoisting code from beyond
those conditional branches and then to undo what should not
have been done when execution went the wrong way. For
achieving this he developed a technique called Trace
Scheduling, a complier, and a machine called ELI-512 to run
the code generated by the compiler [1].
II. GENERAL PRINCIPLES OF VLIW
In VLIW, many statically scheduled, tightly coupled, fine-
grained operations execute in parallel within a single and large
instruction stream. This is different from vector processors, in
the fact that a vector processor performs logically similar
operations in a long instruction (long in terms of time of
execution) whereas a VLIW performs logically unrelated
operations at the same time in different functional units. In
contrast, a vector processor only speeds up loops. A VLIW
has one central control unit issuing a single long instruction
per cycle. Many independent and tightly coupled operations
are carried out per instruction, and each operation takes a
statically predictable number of cycles to execute, with all the
instructions being pipelined in the machine.
In VLIW architectures, most of the performance comes
from the efficiency of complier to take long streams of code
and schedule it effectively. Leveraging the compiler for
scheduling instructions results in less complex hardware for a
given performance metric. However time has proved that this
method is more suitable for data dominated applications like
scientific computing and digital signal processing, and not for
general computing applications which are control driven.
Some of the general principles used in VLIW are discussed
below.
A. Trace Scheduling
Trace scheduling finds sufficient parallelism in ordinary
code to justify thinking about highly parallel VLIW. In
scientific code, it finds parallelism beyond basic blocks. A
basic block of code has no jumps in except at beginning and
no jumps out except at the end. Before Fisher, no one looked
for parallelism beyond basic block, as there was no way to tell
beforehand about the flow of control. Trace scheduling
replaces block-by-block compaction of code with compaction
of long streams of code. Dynamic information about jump
prediction is used at compile time to select streams with
highest probability of execution.
The compiler builds a graph with edges representing control
flows and blocks representing the basic blocks. From the
obtained graph, the trace scheduler selects the most frequently
executed group of blocks and makes it as a trace. Dynamic
information is made use for this. This is done in the
preprocessor stage.
After pre-processing, the scheduler has made many code
motions that will not correctly preserve the jumps from the
trace to the other blocks of the graphs. Post-processor inserts
new code at the trace exit and entrances to recover the correct
machine state. The process continues on the entire graph,
identifying the traces and compacting them the most
frequently executed trace first. Fig.1 shows an example of
trace schedule.
B. Software Pipelining and Loop unrolling
Software pipelining can be thought of as special case of
trace scheduling. In many scientific and signal processing
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Fig. 1. (a) A flow graph, with each block representing a basic block of code. (b) A trace picked from the flow graph. (c) The trace has been scheduled but
it hasn't been relinked to the rest of the code. (d) The sections of unscheduled code that allow re linking. (Joseph Fisher)
applications, there will be several loops running one after
another to perform operations on large arrays. In many cases,
two such loops could be combined as they operate on separate
arrays which dont have a true data dependency between them.
Many of the VLIW combines such independent loops into a
single loop and helps reduce computation. Loop unrolling
helps reduce the number of iterations. Both these techniques
effectively help to reduce the number of conditional jumps in
the code and increases the length of trace.
II. MULTIFLOW ENORMOUSLY LONGWORD INSTRUCTION-512
ELI-512 uses a 512 bit instruction word and can perform
the following operations per cycle:
10 ALU operations. 8 will be 32-bit integer
operations, and 8 will be done using 64-bit
ALUs with a varied repertoire, including
pipelined floating-point calculations.
8 pipelined memory references.
32 register accesses.
A multiway conditional jump based on several
independent tests.
To carry out these operations, ELI has 8 M-clusters and 8 F-
clusters arranged in a circular fashion and interconnected as
shown in fig.2. Each M-cluster has a local memory module,
an fixed point ALU, a multiport register bank, and a crossbar
switch which can select from 8 buses. Each F-cluster has a
floating point ALU, FP register bank and crossbar switch.
TTL ICs were used in implementing the ELI-512.[2]
Trace scheduling requires a mechanism to jump to n+1
locations based on the result of n tests. However to produce
n+1 address in an instruction takes a lot more space. To
circumvent this problem, only one jump address in specified
in the VLIW instruction and the machine calculates the jump
address combining this address with some bits of the test
result. It also supports delayed branches by which flushing of
the pipeline can be avoided when some jumps occur in
program. Delayed branches work by moving the code ahead of
a branch to below a branch, such that when the branch
decision is taken, these moved instructions which are in the
pipeline gets executed (rather than creating bubbles in the
pipeline) and the fetch from jump locations happen after these
instructions are executed.
Many of the operations packed in one instruction may be
memory references. This causes trouble as many functional
units try to access the memory bus at the same time, and the
arbitration scheme creates further delay. To reduce this, ELI
has a banked memory scheme, effectively increasing the
bandwidth of the memory system. The compiler takes care
that memory accesses which occur in a single instruction are
for different banks in memory and avoids conflicts. But there
are still problems with arrays and loops operating on it. The
anti-aliasing system used for unrolling the loops takes care of
this. However pointer arithmetic and its uses for accessing the
memory can lead the machine to access a location
unpredictable by the compiler. This is dealt with by
introducing additional shadow ports in the memory dedicated
for such unpredictable operations. With all banks combined,
the bandwidth of the memory system in ELI-512 is
400Mbytes/second.
III. CYNDROME CYDRA-5 DIRECTED DATAFLOW
ARCHITECTURE
Cyndrome has merged several innovative technologies into
a balanced and functionally complete mini-supercomputer
called the Cydra 5 departmental computer. The architecture of
the Cydra 5 is a numeric Processor and the compiler
technology that goes hand-in-hand. The chief virtue of this
combination is its ability to excel with a broad spectrum of
computations. It enables users to achieve larger performance
gains over super minis without re-arranging their existing
application software and algorithms. Any serious attempt at
high performance computing involves the concurrent
execution of multiple operations.
A. The Directed dataflow architecture
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Fig. 3. Architecture of Cydra-5
There are two major forms of parallelism: course grained
and fine grained. Course grained parallelism, popularly
referred to as parallel processing, means multiple processes
running on multiple processors in a cooperative fashion to
perform the job of simple program. In contrast fine grained
parallelism exists within a process at the level of individual
operations that constitute the program. Vector SIMD, VLIW
architecture are examples of architecture that use fine grained
parallelism.
The emphasis in supercomputer is on execution of
arithmetic (particularly floating point) operations. The starting
point for all supercomputer architecture is multiple, pipelined,
floating point functional units, in addition to any needed for
integer operations and memory accesses. The fundamental
objective is to keep them as busy as possible. Assuming this
Fig. 2. Architecture Multiflow ELI-512 showing interconnections of
the functional blocks(Joseph Fisher)
will be achieved, the hardware must be equipped to provide
two input operands per functional unit and to accept one
functional unit per cycle.
The VLIW architecture is properly viewed as the logical
extension to the scalar RISC architecture. The underlying
model is one of scalar code to be executed, but more than one
operation issued per cycle. Using trace scheduling technique,
VLIW can provide good speed up on scalar code. However,
given the lack of architectural emphasis on loops, VLIW does
not do as well on vectorizable computations as a vector
processor does. If greater generality is required in the
capabilities of the architecture, a more general model of
computation is needed, one that does not only on scalar and
vector code like the VLIW and vector architecture but also on
important class of loops that passes parallelism but are not
vectorizable.
The directed dataflow architecture is also significantly
influenced by another concept, one of moving complexity
and functionality out of hardware and into software
whenever possible. The benefits of this concept are reduced
hardware cost and often the ability to make better decisions
at compile time. In directed dataflow architecture, the
compiler makes most decisions regarding the scheduling at
operation at compile time rather than at runtime.
The compiler takes a program and first creates the
corresponding dataflow graph. It then enforces the rule of
dataflow execution, with full knowledge of execution
latency of each operation, to produce a schedule that
indicates exactly when and where each operation will be
performed. While scheduling at compile time, the compiler
can examine the whole program, in effect looking forward
into the execution. It thus creates a better schedule that
might have been possible with runtime scheduling. An
instruction for directed dataflow machine consist of a time
slice out of this schedule , that is , operations that the
schedule specifies for the initiation at the same time. Such an
BITS-Pilani K.K. Birla Goa Campus
Fig. 4. VLIW Instruction Encoding of TM3270
Fig. 5.Architecture summary of TM3270
instruction causes multiple operations to be issued in a single
instruction.
B. The architecture
The general-purpose subsystem consists of up to six
interactive processors, up to 64 Mbytes of support memory,
one or two 1/0 processors, and the service processor/system
console connected over a IOO-Mbyte/s system bus. Each 1/0
processor handles up to three VME buses, to which the
peripheral controllers are attached. Also connected to the
system bus, via a lOO-Mbyte/s port, is the pseudorandomly
interleaved main memory. The numeric processor has three
dedicated ports into the main memory, each providing lOO-
Mbyte/s bandwidth. One of these is for instructions; the other
two are for data. The main memory and support memory share
a common address space and are both accessible from any
processor. Fig.3. shows the architecture of Cedra-5.
IV. TM3270 MEDIA PROCESSOR
The TM3270 media-processor, is the latest TriMedia VLIW
processor, tuned to address the performance demands of
standard definition video processing, combined with
embedded processor requirements for the consumer market.
The processor incorporates instruction set architectural (ISA)
extensions and a load/store unit optimized for the video-
processing domain. The TM3270 is a VLIW-based media-
processor, which is backward source code compatible with
other processors in the TriMedia family i.e. C-code written for
previous TriMedia processors can be recompiled to run on the
TM3270. Fig.5. shows the key architectural features of
TM3270.
A. Operation Encoding
A VLIW instruction may contain up to five operations,
which are template-based encoded in a compressed format to
limit code size. Every VLIW instruction starts with a 10-bit
template field, which specifies the compression of the
operations in the next VLIW instruction. As a result, an
instructions compression template is available one cycle
before the instructions compressed encoding, which relaxes
the timing requirements of the decoding process. Jump target
VLIW instructions are not compressed and do not require an
explicit template field in the preceding instruction. The 10-bit
template field has five 2-bit compression sub-fields, which are
related to the processors issue slots 1 through 5. An issue
slots 2- bit compression field specifies the size of the
operation encoding. Figure 1 gives an example of a VLIW
instruction containing three operations in slots 2, 3, and 5.
Issue slots 1 and 4 are not used, as specified by the 11
encoding of the related compression fields. Since issue slot 1
is not used, the first encoded operation is for issue slot 2. A
VLIW instruction without any operations is efficiently
encoded in 2 bytes, with a 11:11:11:11:11 template field. A
VLIW with all operations of the maximum size of 42 bits is
encoded in 28 bytes, with a 10:10:10:10:10 template field
and 5 * 42 bits for the operation encoding. This compression
scheme allows for an efficient encoding of code with a low
amount of instruction level parallelism. Fig.4 shows the
instruction encoding scheme.
V. INTEL ITALIUM ARCHITECTURE
The IA-64 instruction set architecture provides hardware
support for instruction-level parallelism (ILP) and is very
much different from superscalar architectures because of
support for predicated execution, control& data speculation
and software pipelining. Teaming up with Hewlett-Packard
(HP) Intel developed a new 64-bit architecture, called IA-64 a
new architecture which exploits the vast circuitry and high
speeds available on the newest generations of microchips by a
systematic use of parallelism.
The basic concepts used in IA-64 are Instruction-level
parallelism that is explicit in the machine instructions rather
than being handled at run time by the processor, Long or Very
long instruction words (LIW/VLIW), Branch predication (not
same as branch prediction) and Speculative loading. Intel and
HP refer to this combination of concepts as explicitly parallel
instruction computing (EPIC). The first Intel product based on
this architecture was Itanium.
With the Pentium, Intel made an attempt to use superscalar
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explained subsequently.
ii. Multiple execution units: A typical commercial
superscalar machine today may support four parallel pipelines,
using four parallel execution units in both the integer and
floating-point portions of the processor. It is expected thatIA-
64 will be implemented on systems with eight or more parallel
units.
The register file is quite large compared with most RISC
and superscalar machines. Because we wish to make
parallelism explicit and relieve the processor of the burden of
register renaming and dependency analysis, we need a large
number of explicit registers.
Four types of execution unit are defined in the IA-64
architecture:
I-unit: For integer arithmetic, shift-and-add, logical,
compare, and integer multimedia instructions
M-unit: Load and store between register and memory
plus some integer ALU operations
B-unit: Branch instructions
Fig. 6. Predication as implemented in italium (Intel) F-unit: Floating-point instructions
techniques, allowing two CISC instructions to execute at the
B. IA-64 instruction format
same time. Then, the Pentium Pro and Pentium II through
IA-64 defines a 128-bit bundle that contains three
Pentium 4 included a mapping from CISC instructions to
instructions, called syllables, and a template field. The
RISC-like micro-ops and the use of superscalar techniques
processor can fetch instructions one or more bundles at a time;
enabling the effective use of a chip with millions of
each bundle fetch brings in three instructions. The template
transistors. We can increase the processing speed by dumping
field contains information that indicates which instructions can
those extra transistors into bigger on-chip caches, which can
be executed in parallel. The interpretation of the template field
increase performances but eventually reach a point of
is not confined to a single bundle. Rather, the processor can
diminishing return or increase the superscaling by adding
look at multiple bundles to determine which instructions may
more execution units but finally hit the complexity wall.
be executed in parallel. For example, the instruction stream
Branch prediction must be improved, out-of-order processing
may be such that eight instructions can be executed in parallel.
must be used, and longer pipelines must be employed. But
The compiler will reorder instructions so that these eight
with wide and deeper pipelines, there is a greater penalty for
instructions span contiguous bundles and set the template bits
branch misprediction. Out-of-order execution requires a large
so that the processor knows that these eight instructions are
number of renaming registers and complex interlock circuitry
independent, because of the flexibility of the template field,
to handle dependencies.
the compiler can mix independent and dependent instructions
To address these problems, Intel and HP came up with an
in the same bundle. Unlike some previous VLIW designs, IA-
overall design that enables the effective use of a processor
64 does not need to insert null-operation (NOP) instructions to
with many parallel execution units. The key concept of this
fill in the bundles.
new approach is the concept of explicit parallelism. With this
approach, the compiler statically schedules the instructions at
Each instruction has a fixed-length 41-bit format. This is
compile time, rather than having the processor dynamically
somewhat longer than the traditional 32-bit length found on
schedule them at run time. The compiler determines which
RISC and RISC superscalar machines. Two factors lead to the
instructions can execute in parallel and includes this
additional bits. First, IA 64 makes use of more registers than a
information with the machine instruction. The advantage of
typical RISC machine: 128 integers and 128 floating-point
this approach is that the EPIC processor does not need as
registers. Second, to accommodate the predicated execution
complex circuitry as an out-of-order superscalar processor.
technique, an IA-64 machine includes 64 predicate registers.
All instructions include a 4-bit major op code and a reference
A. General Organization
to a predicate register. Although the major op code field can
IA-64 can be implemented in a variety of organizations,
only discriminate among 16 possibilities, the interpretation of
with key features as:
the major op code field depends on the template value and the
i. Large number of registers: The IA-64 instruction format
location of the instruction within a bundle, thus affording
assumes the use of 256registers: 128 64-bit registers for
more possible op codes. Typical instructions also include three
integer, logical, and general-purpose use, and128 82-bit
fields to reference registers, leaving 10 bits for other
registers for floating-point and graphic use. There are also 64
information needed to fully specify the instruction.
1-bitpredicate registers used for predicated execution, as
BITS-Pilani K.K. Birla Goa Campus

L1: cmp c, 0
je L2
add k, 1 ; k = k + 1

jmp L3
L2: sub k, 1 ; k = k - 1
L3: add i, 1 ; i = i + 1

In the Pentium assembly language, a semicolon is used to

delimit a comment. Figure shows a flow diagram of this
assembly code. This diagram breaks the assembly language
program into separate blocks of code. For each block that
executes conditionally, the compiler can assign a predicate.
These predicates are indicated in Figure. Assuming that all of
these predicates have been initialized to false, the resulting IA-
Fig. 7. IA-64 predication and speculative loading (Intel) 64 assembly code is as follows:
Predicated Code:
C. Predicated Execution
(1) cmp.eq p1, p2 = 0, a ;;
Predication is a technique whereby the compiler determines
(2) (p2) cmp.eq p1, p3 = 0, b
which instructions mayexecute in parallel. In the process, the
(3) (p3) add j = 1, j
compiler eliminates branches from the program by using
(4) (p1) cmp.ne p4, p5 = 0, c
conditional execution. A typical example in a high-level
(5) (p4) add k = 1, k
language is an if-then-else instruction. A traditional compiler
(6) (p5) add k = -1, k
inserts a conditional branch at the if point of this construct. If
(7) add i = 1, i
the condition has one logical outcome, the branch is not taken
and the next block of instructions is executed, representing the
Instruction (1) compares the contents of symbolic register a
then path; at the end of this path is an unconditional branch
with 0; it sets the value of predicate register p1 to 1 (true) and
around the next block, representing the else path. If the
p2 to 0 (false) if the relation is true and will set the value of
condition has the other logical outcome, the branch is taken
predicate p1 to 0 and p2 to 1 if the relation is false. Instruction
around the then block of instructions and execution continues
(2) is to be executed only if the predicate p2 is true (i.e., if a is
at the else block of instructions. The two instruction streams
true, which is equivalent to The processor will fetch, decode,
join together after the end of the else block. An IA-64
and begin executing this instruction, but only make a decision
compiler instead does the following. As an example, consider
as to whether to commit the result after it determines whether
the following source code:
the value of predicate register p1 is 1 or 0. Note that
instruction (2) is a predicate-generating instruction and is itself
if(a&&b)
predicated. This instruction requires three predicate register
j= j + 1;
fields in its format. Returning to our Pentium program, the
else
first two conditional branches in the Pentium assembly code
if (c)
are translated into two IA-64 predicated compare instructions.
k = k + 1;
If instruction (1) sets p2 to false, the instruction (2) is not
else
executed. After instruction (2) in the IA-64 program, p3 is true
k = k - 1;
only if the outer if statement in the source code is true. That is,
i = i + 1;
predicate p3 is true only if the expression (a AND b) is true
(i.e., AND The then part of the outer if statement is predicated
Two if statements jointly select one of three possible
on p3 for this reason. Instruction (4) of the IA-64 code decides
execution paths. This can be compiled into the following code,
whether the addition or subtraction instruction in the outer else
using the Pentium assembly language.The program has three
part is performed. Finally, the increment of i is performed
conditional branches and one unconditional branch
unconditionally. Looking at the source code and then at the
instructions:
predicated code, we see that only one of instructions (3), (5),
and (6) is to be executed. In an ordinary superscalar processor,
cmp a, 0 ; compare a with 0
we would use branch prediction to guess which of the three is
je L1 ; branch to L1 if a = 0
to be executed and go down that path. If the processor guesses
cmp b, 0
wrong, the pipeline must be flushed. An IA-64processor can
je L1
begin execution of all three of these instructions and, once the
add j, 1 ; j = j + 1
values of the predicate registers are known, commit only the
Assembly Code:
results of the valid instruction. Thus, we make use of
jmp L3
additional parallel execution units to avoid the delays due to
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Let us look at a simple example, taken from[INTE00a,Volume

1]. Here is the original program:

(p1) brsome_label // Cycle 0

ld8 r1 = [r5] ;; // Cycle 1
add r2 = r1, r3 // Cycle 3

The compiler can rewrite this code using a control speculative

load and a check:

ld8.s r1 = [r5] ;; // Cycle -2

// Other instructions
(p1) brsome_label // Cycle 0
chk.s r1, recovery // Cycle 0
add r2 = r1, r3 // Cycle 0
Fig. 8. Software pipelining in VLIW (Intel)
The speculative load doesnt immediately signal an exception
pipeline flushing. when detected; it just records that fact by setting the NaT bit
for the target register (in this case, r1). The speculative load
D. Control Speculation now executes unconditionally at least two cycles prior to
Another key innovation in IA-64 is control speculation, also thebranch. The chk.s instruction then checks to see if the NaT
known as speculative loading. This enables the processor to bit is set on r1. If not, execution simply falls through to the
load data from memory before the program needs it, to avoid next instruction.
memory latency delays. Also, the processor postpones the
reporting of exceptions until it becomes necessary to report the E. Data Speculation
exception. The term hoist is used to refer to the movement of a In data speculation, a load is moved before a store
load instruction to a point earlier in the instruction stream. instruction that might alter the memory location that is the
Since, load latency is crucial to improve performance; the source of the load. A subsequent check is made to assure that
delays in obtaining data from memory become a bottleneck. the load receives the proper memory value. Consider the
To minimize this, we would like to rearrange the code so that following program fragment:
loads are done as early as possible.
You cannot unconditionally move the load above a branch st8 [r4] = r12 // Cycle 0
because the load may not actually occur. We could move the ld8 r6 = [r8] ;; // Cycle 0
load conditionally, using predicates, so that the data could be add r5 = r6, r7 ;; // Cycle 2
retrieved from memory but not committed to an architectural st8 [r18] = r5 // Cycle 3
register until the outcome of the predicate is known; or we can
use branch prediction techniques. If an exception occurs due As written, the code requires four instruction cycles to
to invalid address or a page fault could be generated. If this execute. If registers r4 and r8 do not contain the same memory
happens, the processor would have to deal with the exception address, then the store through r4 cannot affect the value at the
or fault, causing a delay. address contained in r8; under this circumstance, it is safe to
reorder the load and store to more quickly bring the value into
r6, which is needed subsequently. However, because the
A load instruction in the originalprogram is replaced by two addresses in r4 and r8 may be the same or overlap, such a
instructions: swap is not safe. IA-64 overcomes this problem with the use
A speculative load (ld.s) executes the memory fetch, of a technique known as advanced load.
performs exception detection, but does not deliver the
exception (call the OS routine that handles the exception).This ld8.a r6 = [r8] ;; // Cycle -2 or earlier;
ld.s instruction is hoisted to an appropriate point earlier in the advanced load
program. // other instructions
A checking instruction (chk.s) remains in the place of the st8 [r4] = r12 // Cycle 0
original load and delivers exceptions. This chk.s instruction ld8.c r6 = [r8] // Cycle 0; check load
may be predicated so that it will only execute if the predicate add r5 = r6, r7 ;; // Cycle 0
is true. st8 [r18] = r5 // Cycle 1

If the ld.s detects an exception, it sets a token bit associated
with the target register, known as the Not a Thing (NaT) bit. If
the corresponding chk.s instruction is executed, and if the NaT
bit is set, the chk.s instruction branches to an exception
handling routine.
Here we have moved the ld instruction earlier and converted
it into an advanced load. In addition to performing the
specified load, the ld8.a instruction writes its source address
(address contained in r8) to a hardware data structure known
as the Advanced Load Address Table (ALAT). Each IA-64
store instruction checks the ALAT for entries that overlap with
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its target address; if a match is found, the ALAT entry is
removed. When the original ld8 is converted to an ld8.a
instruction and moved, the original position of that instruction
is replaced with a check load instruction, ld8.c. When the
check load is executed, it checks the ALAT for a matching
address. If one is found, no store instruction between the
advanced load and the check load has altered the source
address of the load, and no action is taken. However, if the
check load instruction does not find a matching ALAT entry,
then the load operation is performed again to assure the
correct result.
We may also want to speculatively execute instructions that
are data dependent on a load instruction, together with the load
itself. Starting with the same original program, suppose we
move up both the load and the subsequent add instruction:
ld8.a r6 = [r8] ; ;
// Cycle -3 or earlier; advanced load
// other instructions
add r5 = r6, r7 // Cycle -1; add that uses r6
// other instructions
st8 [r4] = r12 // Cycle 0
chk.a r6, recover // Cycle 0; check
// return point from jump to recover
back:
st8 [r18] = r5 // Cycle 0
Here we use a chk.a instruction rather than an ld8.c
instruction to validate the advanced load. If the chk.a
instruction determines that the load has failed, it cannot simply
re-execute the load; instead, it branches to a recovery routine
to clean up:
Recover:
ld8 r6 = [r8] ;; // reload r6 from [r8]
add r5 = r6, r7 ;; // re-execute the add
br back // jump back to main code
This technique is effective only if the loads and stores
involved has little chance of overlapping.
F. Software Pipelining
Software Pipelining (SWP) is the term for overlapping the
execution of consecutive loop iterations. SWP is a
performance technique that can be done in just about every
computer architecture.SWP is closely related to loop
unrolling.
Here is a conceptual block diagram of a software pipeline.
The loop code is separated into four pipeline stages. Six
iterations of the loop are shown (i = 1 to 6). Notice how the
pipeline stages overlap. The second iteration (i=2) can begin
while the first iteration (i=1) begins the second stage. This
overlap of iterations increases the amount of parallel
operations that can be executed in the processor. More parallel
operations helps increase performance. Many, but not all,
loops may be software pipelined.
G. Modulo Loop Scheduling
Modulo Loop Scheduling is just one software pipelining
technique. There is direct support in the IA 64 architecture for
modulo loop scheduling: rotating registers, predicates, special
branch instructions, and loop count registers. The architectural
support makes it easy to create SWP loops. The resulting code
has high performance and is compact. It involves developing a
schedule for one loop iteration such that when the schedule is
repeated at regular intervals, no intra- or inter-iteration
dependency is violated, and no resource usage conflict arises.
The Initiation Interval (ii) is essentially the length of one
pipeline stage -the number of clock cycles it takes to execute
one pass through the loop instructions or the number of clock
cycles between starting iteration i and starting iteration i+1.
When comparing SWP loops, compare the ii and the number
of stages. For high loop counts, ii is more important than the
number of stages. With high loop counts, more time is spent in
the loops kernel rather than the prolog and epilog. The kernel
time is determined by the number of iterations and the ii.
The key features that support software pipelining are:
Automatic register renaming: A fixed-sized area of the
predicate and floating-point register files (p16 to p63; fr32 to
fr127) and a programmable-sized area of the general register
file (maximum range of r32 to r127) are capable of rotation.
This means that during each iteration of a software pipeline
loop, register references within these ranges are automatically
incremented. Thus, if a loop makes use of general register r32
on the first iteration, it automatically makes use of r33 on the
second iteration, and so on.
Predication: Each instruction in the loop is predicated on a
rotating predicate register. The purpose of this is to determine
whether the pipeline is in prolog, kernel, or epilog phase, as
explained subsequently.
Special loop terminating instructions: These are branch
instructions that cause the registers to rotate and the loop
count to decrement.
VI. CONCLUSION
VLIW has found enormous success in DSP and signal
processing applications over years, although their use is
limited in general purpose computing (IA-32 is one example).
The earlier VLIW architectures didnt stand the test of time,
partly due to the due to the technology they were built on, and
partly due to better architectures combined with lower cost of
silicon real estate.
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