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DATA SHEET
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74HC/HCT373
Octal D-type transparent latch;
3-state
Product specification September 1993
File under Integrated Circuits, IC06
Philips Semiconductors Product specification
FEATURES input and an output enable (OE) input are common to all
latches.
• 3-state non-inverting outputs for bus oriented
applications The “373” consists of eight D-type transparent latches with
• Common 3-state output enable input 3-state true outputs. When LE is HIGH, data at the Dn
inputs enters the latches. In this condition the latches are
• Functionally identical to the “563”, “573” and “533” transparent, i.e. a latch output will change state each time
• Output capability: bus driver its corresponding D-input changes.
• ICC category: MSI When LE is LOW the latches store the information that was
present at the D-inputs a set-up time preceding the
GENERAL DESCRIPTION HIGH-to-LOW transition of LE. When OE is LOW, the
contents of the 8 latches are available at the outputs.
The 74HC/HCT373 are high-speed Si-gate CMOS devices When OE is HIGH, the outputs go to the high impedance
and are pin compatible with low power Schottky TTL OFF-state. Operation of the OE input does not affect the
(LSTTL). They are specified in compliance with JEDEC state of the latches.
standard no. 7A.
The “373” is functionally identical to the “533”, “563” and
The 74HC/HCT373 are octal D-type transparent latches “573”, but the “563” and “533” have inverted outputs and
featuring separate D-type inputs for each latch and 3-state the “563” and “573” have a different pin arrangement.
outputs for bus oriented applications. A latch enable (LE)
TYPICAL
SYMBOL PARAMETER CONDITIONS UNIT
HC HCT
tPHL/ tPLH propagation delay CL = 15 pF; VCC = 5 V
Dn to Qn 12 14 ns
LE to Qn 15 13 ns
CI input capacitance 3.5 3.5 pF
CPD power dissipation capacitance per latch notes 1 and 2 45 41 pF
Notes
1. CPD is used to determine the dynamic power dissipation (PD in µW):
PD = CPD × VCC2 × fi + ∑ (CL × VCC2 × fo) where:
fi = input frequency in MHz
fo = output frequency in MHz
∑ (CL × VCC2 × fo) = sum of outputs
CL = output load capacitance in pF
VCC = supply voltage in V
2. For HC the condition is VI = GND to VCC. For HCT the condition is VI = GND to VCC − 1.5 V
ORDERING INFORMATION
See “74HC/HCT/HCU/HCMOS Logic Package Information”.
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Philips Semiconductors Product specification
PIN DESCRIPTION
Fig.1 Pin configuration. Fig.2 Logic symbol. Fig.3 IEC logic symbol.
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Philips Semiconductors Product specification
FUNCTION TABLE
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Philips Semiconductors Product specification
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Philips Semiconductors Product specification
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Philips Semiconductors Product specification
AC WAVEFORMS
Fig.10 Waveforms showing the data set-up and hold times for Dn input to LE input.
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Philips Semiconductors Product specification
PACKAGE OUTLINES
See “74HC/HCT/HCU/HCMOS Logic Package Outlines”.
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