IJSTE - International Journal of Science Technology & Engineering | Volume 3 | Issue 09 | March 2017

ISSN (online): 2349-784X

Physical Design Implementation of Area

Optimized, High Performance SRAM Cell
Miss. Ankita Taiwade Miss. Aishwarya Gode
Student Student
Department of Electronics Engineering Department of Electronics Engineering
DBACER College of Engineering Nagpur, India DBACER College of Engineering Nagpur, India

Miss. Shreya Bujade Miss. Shipra Sambhare

Student Student
Department of Electronics Engineering Department of Electronics Engineering
DBACER College of Engineering Nagpur, India DBACER College of Engineering Nagpur, India

Miss. Preeti M. Dixit

Assistant Professor
Department of Electronics Engineering
DBACER College of Engineering Nagpur, India

Abstract
In the recent years, on chip memory complexities has been increased with the increase in the logic of the processor designed. So
the basic element of the memory design is SRAM cell. This paper presents the idea of an 8T CMOS SRAM cell. It also implements
the development and design of CMOS based SRAM cell which improves the performance, reduces the power & area requirement.
This cell design is basically proposed for the power reduction during write operation. The performance of the proposed cell
structure is compared with conventional 6T design in 32nm, 45nm, 65nm CMOS technologies by using Micro wind 3.5 EDA tool.
Keywords: SRAM Cell, Read/Write Operation, Microwind EDA
________________________________________________________________________________________________________

I. INTRODUCTION

In VLSI design, the integration of the chip is being continuously increasing day by day so that more and more functions are get
added while designing a chip.
To drive the integration with more efficiently, we need to improve the memory allocation of the design too. The improvement
is in the form of the basic parameters such as speed, area and power consumption. The most important consideration is the power
consumption of the design. The power consumption gets increased as due to the high integration and the speed of processor.
The basic and conventional SRAM cell consists of 6 transistors in it and hence called as convention 6T RAM cell. The basic
cell for static memory design is based on 6 transistors with two pass gates instead of one. The corresponding schematic diagram is
given in Figure below. The circuit consists again of the 2 cross-coupled inverters, but uses two pass transistors instead of one. The
cell has been designed to be duplicated in X and Y in order to create a large array of cells. Usual sizes for Megabit SRAM memories
are 256 column x 256 rows or higher. The selection lines WL concern all the cells of one row. The bit lines BL and ~BL concern
all the cells of one column.

II. DESIGN IMPLEMENTATION

Conventional 6t RAM
The basic cell for static memory design is based on 6 transistors with two pass gates instead of one. The corresponding schematic
diagram is given in Figure below. The circuit consists again of the 2 cross-coupled inverters, but uses two pass transistors instead
of one. The cell has been designed to be duplicated in X and Y in order to create a large array of cells. Usual sizes for Megabit
SRAM memories are 256 column x 256 rows or higher. The selection lines WL concern all the cells of one row. The bit lines BL
and ~BL concern all the cells of one column.

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 Physical Design Implementation of Area Optimized, High Performance SRAM Cell
(IJSTE/ Volume 3 / Issue 09 / 108)

Fig. 1: Logic Circuit- 6T RAM Fig. 2: Circuit Layout for 6T Cell

SRAM uses bistable latching circuitry to store each bit. Each bit is stored in two cross-coupled inverters, formed by four
transistors. This storage cell has two stable states which are used to denote 0 and 1. Two additional access transistor control the
access to the storage cell during read and write operations.

Fig. 3: Physical design of 6T RAM

Proposed 8T RAM Cell

In the proposed design, we are improving the power and speed, which contains two extra tail transistors in the pull down paths of
the respective inverters to avoid charging of the bitlines. During write or read mode at least one of the tail transistors will be turned
off to disconnect the driving path of respective inverters.
Microwind 3.5 EDA tool is used for the physical design and DSCH 3.5 is used for the schematic design. The Microwind tool is
used to analyse the performance of the proposed structure with 32 m Technology.
The schematic of the proposed 8T SRAM cell is shown in Fig 4.

Fig. 4: Proposed 8 T RAM design

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 Physical Design Implementation of Area Optimized, High Performance SRAM Cell
(IJSTE/ Volume 3 / Issue 09 / 108)

The physical design of the proposed 8T SRAM cell is shown in Fig.5.

Fig. 5: Physical design of 8T RAM cell

III. RESULT AND DISCUSSION

For Write Cycle

Values 1 or 0 must be placed on Bit Line, and the data inverted value on ~Bit Line. Then the selection Word Line goes to 1. The
two-inverter latch takes the Bit Line value. When the selection Word Line returns to 0, the RAM is in a memory state.

For Read Cycle

The selection signal Word Line must be asserted, but no information should be imposed on the bit lines.
In that case, the stored data value propagates to Bit Line, and its inverted value ~Data propagates to ~Bit Line.

Simulation
The simulation parameters correspond to the read and write cycle in the RAM. The simulation steps proposed in figure below
consist in writing a 0, a 1, and then reading the 1. In a second phase, we write a 1, a 0, and read the 0. The Bit Line and ~Bit Line
signals are controlled by pulses. The floating state is obtained by inserting the letter "x" instead of 1 or 0 in the description of the
signal.

Fig. 6: Simulation result of 6T RAM cell

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 Physical Design Implementation of Area Optimized, High Performance SRAM Cell
(IJSTE/ Volume 3 / Issue 09 / 108)

Fig. 7: Simulation result of proposed 8T RAM cell

Table 1
The power utilization of the Ram cell.
Power Dissipation in conventional 6T Power Dissipation in the proposed 8T cell
0.67 uW 0.58 uW
Table 2
The area utilization of the Ram cell.
Area for conventional 6T Area for proposed 8T cell
1.8m2 2.8m2

IV. CONCLUSION

This paper presents a new design of SRAM cell to reduce the power dissipation during write operation by introducing two tail
transistors and another transistor to control these two in the pull down path. The design parameters like area and power are
optimized by working on physical layout design.

REFERENCES
[1] Etienne SICARD, CHEN Xi, A PC- based educational tool for CMOS Integrated Circuit Design, INSA, and Department of Electrical & Computer
Engineering Av de Rangueil.
[2] A. Tripathi and S. Biswas, A 44 SRAM Cell Array for Low Power Applications,2nd International Conference on Nanotechnology- Innovative Materials,
Processes, Products and Applications, 2012.
[3] A. Aoki, J. Etoh, K. Itoh, S. I. Kimura and Y. KAwamoto, A 1.5-V DRAM for Battery-Based Applications, IEEE Journal of Solid-State Circuits, vol. 24,
(5), pp.1206-1212, 1989.
[4] P. Pleshko and L. M. Terman, An Investigation of the potential of MOS transistor memories, IEEE Trans. Electronic Computers, vol. EC-15, pp. 423-427,
1966, conference on wireless and optical communications 2013.
[5] A. Hussein, H. Saleh, B. Mohammad, and E. John, Optimum organization of SRAM based memory for leakage power reduction, [51st Midwest Symposium
on Circuits and System (MWSCAS 2008), pp. 775-778, August 2008].

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