Phase Aware and Configuration aware

Assertions in UVM
Surinder SOOD
SANDISK INDIA
Motivation

Wanted to have a consistent mechanism for protocol checking.

Wanted to have automated SVA checks
Wanted to have concurrent protocol checks in UVM.
Wanted to have adaptive SVA checks.
Motivation

Types of Checks in UVC:

Timing and Control checks. These are typically signal level. These checks
are required to be done at the interface level.

Transaction checks and compare. These are typically packet level. This is
done inside monitor and scoreboard
How we enable assertions

Assertions in UVC are enabled and configured:

Using Control knobs ( for example, you want to
enable checks)
E.G. class my_monitor ;
If(checks_on) check_crc() Class test;
Uvm_config_db#(my_config)::set(this,*,cfgcfg)
Config fields (eg. Class monitor ; Uvm_config_db#(bit)::set (this,*,check_on,0)
Trans.check_multi_commands(cfg.full_eblocks)
Object fields can be configured
During build_phase and must be constantly Class monitor;
allocated. If(some condition)
Cfg.multiblocks = 1
Can be re-configured during run phase.
 SVA methodology in UVM
Sequence fast_trfr;
Req ##1 !Req[*1:7] ##0 Gnt;
Endsequence
Sequence slow_trfr;
Req ##1 !Req[*1:7] ##0 Gnt;
Endsequence

Property ip_trfr;
@(posedge clk)
Disable iff(!checks_on)
Req |-> if(cfg_speed_level ==FAST)
Fast_trfr;
Else
Slow_trfr;
Endproperty

Transfer_Assert:assert property (ip_trfr)

Else $error(ILLEGAL SPEED)
SVA Integration into UVC

Config_db
Config_
db::get
VIF Config_
db::set

Mon Drv I/F

VIF VIF DUT

SVA

AGENT TB Module
Place for SVA

Encapsulated in interface.
SVA code is verbose and complex
Majority of the lines of code comprised of SVA checks in physical
interface.
 Method 1: call SVA interface from main
interface
interface my_interface;
interface assertion_chkr(
// local signals
// signal ports
logic CLK;
input logic CLK,
logic REQ;
input logic REQ,
logic GNT;
input logic ACK,
logic [7:0] DATA;
input logic [7:0] DATA
logic OTHER;
); // support code
... // modports,
etc. // properties //
assertions
...
endinterface
// protocol checker

assertion_ chkr
sva_checker(.*);
endinterface
SVA Configuration [Method 1]

interface assertion_chkr(...);
// control points
bit checks_enable = 1;
// config object Interface is not a
phased component in this case.
my_config cfg;
Configuration class is built during the build
// local variables for SVA phase
speed_level cfg_speed_level;
int unsigned cfg_max_value;
bit cfg_data_on;

// properties and assertions...

// update local vars from cfg...
endinterface
 Interface API used for sva checker call set_* methods
configuration via virtual interface
after build and
connect, can be Start
class my_monitor extends uvm_monitor;
interface assertion_chkr(...); ... of Sim also..
...
function void end_of_elaboration_phase(...);
function void set_config ...
// set interface config after build
(my_config cfg);
vif.set_mode(cfg);
cfg_speed_level =cfg.speed_level; vif.set_checks_on(checks_enable);
cfg_max_value = cfg.max_value; endfunction
...
cfg_data_en = cfg.data_en; endclass
endfunction
interface my_interface;
function void set_checks_enable ...

function void set_mode(my_config cfg);

(bit en); sva_checker.set_config(cfg);
checks_enable = en; endfunction
function void set_checks_on(bit en);
endfunction sva_checker.set_checks_on(en);
user API via VIF methods
...
endfunction ...
endinterface endinterface
 Phase-Aware Interface

Here we create a new phase which works parallel to UVM phases.

interface assertion_checker(...);
// declare local variables (cfg, checks_enabled, etc.)
...
class my_phase extends uvm_component;
// use local variables (cfg, checks_enabled, etc.)
// use UVM phases (build, connect, run, etc.)
endclass
// construct unique instance of phaser class
// (at the top-level under uvm_top)
my_phase m_phase = new($psprintf("%m.m_phase"));
endinterface
 Static configuration: During End of
elaboration phase
class my_phase extends uvm_component;
...
function void end_of_elaboration_phase(...);
...
if (!uvm_config_db#(my_config)::get(this,","cfg,cfg))
`uvm_fatal(CFGERR,no my_config cfg in db)

void'(uvm_config_db#(bit)::get
(this,","checks_enable,checks_enable));

cfg_speed_level= cfg.speed_mode;
copy required cfg fields to
cfg_max_value = cfg.max_value;
local variables for use in SVA
cfg_data_en = cfg.data_en;
endfunction
Dynamic Configuration: Use Run_Phase

class _my_phase ...; use run_phase to check for

...
dynamic cfg changes
task run_phase(...);
...
forever begin
@(cfg.speed_level or cfg.data_en) begin
cfg_speed_level = cfg.speed_level;
cfg_data_en = cfg.data_en;
end
`uvm_info(CFG,cfg updated,UVM_LOW)
end
endtask
endclass
Conclusion

Successfully used this approach in one of the memory projects

Here , we demonstrated how to encapsulate SVA using either of the two
approaches.
Configuration aware SVA can have
API configured by UVC
Phase-aware checker with class in interface

Thanks to Mark Litterick for this motivational work.

References:
http://www.verilab.com/files/litterick_sva_encapsulation.pdf