IJRET: International Journal of Research in Engineering and Technology eISSN: 2319-1163 | pISSN: 2321-7308

DESIGN & SIMULATION OF A 32-BIT RISC BASED MIPS

PROCESSOR USING VERILOG

Priyavrat Bhardwaj1, Siddharth Murugesan2

1
Department of Electrical & Electronics Engineering, Guru Tegh Bahadur Institute of Technology, New Delhi, India
2
Department of Electrical & Electronics Engineering, Guru Tegh Bahadur Institute of Technology, New Delhi, India

Abstract
This research paper presents design & simulation of a high performance five stage pipelined 32-bit Microprocessor without
Interlocked Pipeline Stages (MIPS),which is a Reduced Instruction Set Computing (RISC) architecture based processor. The
purpose of RISC microprocessor is to execute a minuscule batch of instructions, with the intention of proliferating the celerity of
the processor. This processor was designed with5 phases of pipeline in particular Instruction Fetch (IF), Instruction Decode&
Register Fetch (ID), Execution& Address Calculation (EX), Memory Access (MEM) and Write Back (WB) modules. The designing
process was done using a myriad of modules which are the ALU, Control Unit, Program Counter, MUX, Instruction Memory,
Data Memory, CPU, Register File, Sign Extension. The designing of this processor is developed using the Hardware Description
Language (HDL) - Verilog in ModelSim simulator. The supreme aim of this paper is to develop the RTL logic design using Xilinx
tool.

Keywords- MIPS, RISC, CISC, Verilog, RTL, ModelSim, Xilinx

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1. INRODUCTION instruction set to load data from the memory and store
instruction set to Write Back (WB) the data into memory
Microprocessors & Microcontrollers are generally designed without any instructions [1].
in the vicinity of two main computer architectures: Complex
Instruction Set Computing i.e. CISC architecture and
2. MIPS INSTRUCTION SET ARCHITECTURE
Reduced Instruction Set Computing i.e. RISC architecture.
The concept of CISC is based on Instruction Set The instruction set can be categorized under three
Architecture (ISA) design that redoubles performing further classifications in the MIPS ISA, these are: Register type (R),
with several instructions utilizing changeable number of Immediate type (I) and Jump type (J). Each instruction starts
operands and an out spread variation of addressing modes in with a 6-Bit Opcode. Alongside these opcode, Register type
disparate locations in its Instruction Set. Thus causing them (R)define 3 (three) registers, Immediate ype (I) instructions
to have varying execution time and lengths thereby define2 (two)registers and a 16Bitevaluation; Jump type (J)
authoritatively mandating an intricate Control Unit, which instructions have an opcode of 26Bit[1].
inhabits an immensely existent region on the chip.
Compared with their CISC analogue, RISC processors The following table demonstrates the three formats used for
typically support a minuscule set of instructions. A display the MIPS core instruction set architecture:
that juxtaposes RISC processor with CISC processor, the
number of instructions in a RISC Processor is low while the Table 1
number of general purpose registers, addressing modes,
fixed instruction length and load-store architecture is more
this in turn facilitates the execution of instructions to be
carried out in a short time thus achieving higher overall
performance [1].

Currently, the efficacy of the RISC processors is generally

accepted to be greater than that of their CISC counterparts.
Before their execution the instructions are translated into
RISC instructions in even the most popular CISC
processors. The attributes mentioned above accentuate the
design strength of RISC in the market for embedded systems
known as "system-on-a-chip (SoC)"[12]. The premier micro
processors exhibiting reduced instruction set are SPARC,
ARM, MIPS and IBM's PowerPC. RISC processor typically
has load store architecture. This denotes there are two
instructions for accessing memory which are a load
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2.1 Register (R) Type Instructions:

Fig. 1. Register-Type Instructions
Fig. 2 illustrates Register (R) type Instructions Data path
[1]. Its main usage is in performing mathematical operations
such as addition and subtraction. E.g. add Rd, Rs, Rt. In this
the value received by Rd is the signed addition of Rs and Rt
i.e. Rs plus (+) Rt.

The instruction format illustrated in Fig. 1.is that of Register
(R) Type. In it the Opcode is represented by the last 6 bits.
The 3 register types on which the operations are executed
are Rs, Rt and Rd which are represented in the above
illustration by 15-bits that follow the Opcode. The starting
or the source registers are Rs andRt while the ending or
target register is Rd. Succeeding 5-bits are the shift sum
which betokens the number of bits that are to be moved. The
final 6-bits represent the function field points to the function
which are to be executed on the registers.
2.2 Immediate (I) Type Instructions:
Fig. 3. Immediate Type Instructions
Immediate (I) type instructions are demonstrated in Fig.3.
The four fields portrayed in this type of arrangement
represent - the Opcode, which is of 6-bitthat is utilized to
select the Instruction type, storing of data is done in the
Source Register and Target Registers which are Rs and Rt
respectively. Each are of 5-Bit. The final 16-bit
Address/Immediate Valuefield wielding prompt data.

Fig. 2. Register Type Instructions Data Path

Fig. 4. Data Path for Immediate (I) type instructions

Fig. 4 delineates the data path for Immediate (I) type 2.3 Jump (J) type Instructions (Branch Format)
instruction [1]. It demonstrates the dichotomy of Rt register
which can be used both as a source and a destination. The
immediate value received by sign extend is represented by
the last 16-bits which is then sent to the Arithmetic and Fig. 5. Jump Type Instructions
Logical Unit for playing out the desired function.

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The instruction format shown in Fig. 5. is that of Branch

Type [1]. The two fields illustrated in this arrangement type
are the Opcode which is of 6-bit, utilized to choose the kind
of instruction organization and Ending or Target address of
26-bit, utilized to determine where the address has to be
branched.

Fig. 6. Data Path for Jump Type Instructions Fig. 7. Basic MIPS Architecture

The data path for Jump (J) type instruction is illustrated in
Fig. 6.[1]. The figure demonstrates that a 32-bit jump (J)
address is obtained when the last 4 bits of PC + 4 are
attached to the shift left by 2 values of a 26-bit instruction
captured out from MEM. In addition, it jumps to the
destination by omitting any alternate instruction.
3. MIPS ARCHITECTURE
The accompanying outline demonstrates the fundamental
architecture of a MIPS-based framework:
Microprocessor without Interlocked Pipeline Stages (MIPS)
is a RISC (Reduced Instruction Set Computing) architecture.
Pipelined MIPS has five stages which are IF, ID, EX, MEM
and WB. Pipelining means several operations in single data
path at the same instant. Pipelining is used to enhance the
capabilities of the RISC processor which is the reason for its
utilization in this type of computer architecture. A
multicycle CPU comprises of countless tasks. So if one task
occurs, rather than waiting for the process to finish, at the
same time another task is initiated in the same data path
simultaneously without interfering with the previous task.
The processes is thus divided into different pipelined stages.
Following every clock a new operation is instigated in the
pipeline stage to which the process is being fed to. The
triggering is done without causing any interruptions to the
past process. This makes simultaneous utilization of all
stages in the data path possible. This thusly can increment
the throughput of MIPS.

Fig. 8. 5-Stage Pipelined MIPS

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IJRET: International Journal of Research in Engineering and Technology
MIPS processor has been executed utilizing five pipeline
stages, which are Instruction Fetch (IF), Instruction Decode
(ID), Execution (EX), Memory access (MEM) and Write
Back (WB).The isolation of these stages is achieved by
special registers known as pipeline registers. The aim of
these registers is to isolate the stages of the instructions so
that there is no inadmissible information because of various
directions being executed all the while. They are named in
the middle of each of these: IF/ID Register, EX/MEM
Register and MEM/WB Register. The data path
demonstrated in Fig. 8. is that of the MIPS pipelined
processor.
3.1 Instruction Fetch (IF)
The command relayed to the Program Counter (PC) to fetch
the instruction from the cache memory is what instigates the
primary pipelining operation of the IF stage. The storage of
PC and Instruction for the successive clock cycle is done in
the IF/ID pipelined register as RAM (Random Access
Memory)
Fig. 9. IF Stage representation
IF stage for the most part relies on upon PCs represent
value. On the basis of the PC value the processor gets the
instructions from the cache and followed by which the
Program Counter value is incremented by 1. Thus, the IF/ID
register receives this information followed by which the
information is relayed to the decoder unit. The Instruction
Fetch (IF) stage operation has been represented in Fig. 9
[22].
3.2 Instruction Decoder (ID)
Fig. 10. ID Stage representation
The Opcode is relayed to the decoder unit at the instant
when the instruction is obtained from the IF stage.
Instruction Decoder ID stage directs the controlling
command to the various units of the MIPS processor
examining the Opcode of the instructions. Thus the
procurement of data from the MIPS registers is carried out
by the Read register. The Branch unit is likewise
incorporated into Instruction Decoder (ID) stage. The Input
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eISSN: 2319-1163 | pISSN: 2321-7308
data of ID stage is received from IF stage as shown in Fig.
8.This decoding stage includes four different instructions:
Register (R) type, Immediate (I)type, Jump (J) type and
Input/Output (I/O) type instructions. Depending upon these
instructions the function will be performed utilizing above
mentioned formats. Fig. 10. indicates Instruction Decode
(ID) stage operation [22].
3.3 Execute (EX)
Fig. 11. Execution Stage (EX) representation
Following the Instruction Decoder(ID), the instructions are
sent to execute stage(EXE or EX). Execute (EX) stage
performs Arithmetic and Logical Unit (ALU) processes.
Execution of operations is the fundamental aspect of
Execute (EX) stage, for instance arithmetic operations such
as addition and difference and OR & AND. In particular,
EX/MEM pipelined register receives the result upon the
execution of specific instructions (i.e. FP ALU). Execute
stage representation is shown in Fig. 11. [22].
3.4 Memory Access &Input/Output (MEM)
Fig. 12. Memory Access representation
The storing and loading of values along with inputting and
outputting data from the processor is the primary function of
the memory access (MEM) stage. The outcome will be
dispatched to the WB stage in a scenario where the
instruction is neither memory nor IO instruction. After the
result is figured the primary function is to store the data
values in the destination register. The Memory Access
(MEM) stage operation is demonstrated in Figure 12 [22].
3.5 Write Back (WB)
Fig. 13. Write Back representation
As per Fig. 13., the Write-Back (WB) operation is the final
stage of the RISC based MIPS architecture which composes
the result, store information and input data from and to the
register file [22]. Writing the data that has been fetched from
the MIPS register to the target register is the main aim of
this stage.
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4. RESULT
4.1 RTL Design

Fig. 14. RTL Design view of RISC based MIPS Processor

As per the design, the Write-Back (WB) operation writes
back the result, stores the information and inputs the
information to the Register file and vice-versa. For instance,
the result is given by ADD Rd, Rs, Rt instructions. It is
analogous to the Feedback operation in various engineering
systems. The Register Transfer Logic as illustrated in Fig.
14. is that of 32-Bit RISC based MIPS Processor [2]. It
contains Instruction decoder (ID) unit, Instruction Fetch (IF)
unit, memory unit (MEM) and execution unit (EX). In this
process, the program counter (PC) is utilized while fetching
the Opcode from Instruction Fetch (IF) stage and sending
the code to Instruction Decode (ID) stage. Instruction Fetch
(IF) stage receives the Opcode from the ID unit which is
then sent for execution in the EX stage. The instruction
configuration chosen is dependent on the Opcode. The
execution of the instruction in the EX stage occurs in
accordance with the assigned Opcode. Storage of Opcode to
the memory and fetching it from the memory is the primary
task of the memory unit.
4.2 Simulation Result
The Resulting output waves of 5-staged pipelined MIPS
RISC processor is shown below:

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IJRET: International Journal of Research in Engineering and Technology
Fig. 15 (a). Output Wave Simulation
Fig. 15 (b). Output Wave Simulation
Fig. 15 (c). Output Wave Simulation
As illustrated in the waveforms, Fig. 15 (a), (b) and (c)
demonstrates simulation result for R-type, I-type & J-type
instruction formats.
5. CONCLUSION
This research paper outlines a 32-bit Microprocessor without
Interlocked Pipeline Stages (MIPS) based RISC processor is
executed effectively with pipelining. In a five stage
pipelining system the execution of each direction occurs in a
single clock cycle. This design demonstrates the usage of
MIPS based CPU equipped for taking care of different
Register type, Jump type and Immediate type of instructions
and each of these classifications has a diverse configuration.
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