THE DESIGN AND ANALYSIS OF SIGMA-DELTA ADC FOR HIGH-

SPEED DATA CONVERSION AT DEEP SUBMICRON TECHNOLOGY

NODE
PADMINI Y.N
R.F Communication, Center for emerging technologies, Jain University
Bangalore, Karnataka, India

K.V KUMARA SWAMY

Research Scholar, VTU, BIT , Bangalore, Karnataka, India

ABSTRACT: This paper aims at the design of Continuous time Sigma-Delta converter. Sigma -
Delta converters are implemented as sub-ADC in Time-Interleaved converters to achieve high
speed and high accuracy. As the technology scales, power supply and threshold voltage keeps
reducing to satisfy high performance and low power requirements. The converter provides the
advantage of relaxed anti-alias filter as they employ oversampling principle. The ADC has been
implemented in Virtuoso environment with BSIM 4.3 device models. Many application areas such
as bio-medical instrumentation, defense equipment, portable communication equipment and so on
require ultra-low power dissipation.

KEYWORDS: Sigma-Delta ADC; Time-Interleaved; Oversampling; Anti-alias filter;

INTRODUCTION

As Gordon Moore (co-founder of Intel) predicted in early 1970s, the number of transistors per
chip has continued to double approximately every one and a half years[1].The channel length of the
FET dropped from 180nm to about 40nm, resulting in very high speed integrated circuits. As a
result, the supply voltage and the power consumption too decrease. The short channel effects leads
to the variation in device parameters at deep submicron nodes. Subsequently, low voltage and
decreased threshold voltage (Vth) imposes major challenges in the design of analog circuits. e.g.,
that of ADC.

Data converters are most important component of the todays design, as they interface between
analog and digital world. The Sigma-Delta ADC is one of the superior methods of implementing
converter with high accuracy, high linearity and good dynamic range. Converters with high
resolution and sampling rate find application in Wireless Transceiver, Medical Imaging, Video
Signal Processing, Data Acquisition and Instrumentation. The primary task of this paper is to
propose a Sigma-Delta converter, which is suitable for Low-Voltage applications. Secondly, use
this as a Sub-ADC in Time-Interleaved or Parallel architecture for very High-Speed applications.

SIGMA-DELTA TRANSFORMATION TECHNIQUE

An ADC is characterised by its bandwidth and its signal to noise ratio. The sampling rate
fs,ny=2fmax is called the Nyquist rate, where fmax is the highest frequency contained in the analog
signal. Sigma-Delta converters are also called non-Nyquist converters. They apply Oversampling
and Noise shaping techniques.
Oversampling is the method in which the sample rate fs is increased beyond the Nyquist rate fs,ny.
fs fs
OSR = (1)
f s ,ny 2 fb

is called Over Sampling Ratio. In converters, the quantization energy is uniformly distributed in
2
the frequency band up to fs/2. The quantization noise power Q in non-Nyquist converters is
given by
2
VLSB 1
Q2 = (2)
12 OSR
Hence, the quantization noise level depends on the sampling frequency. Therefore, in Sigma-Delta
converters the use of high sampling frequency enables low quantization noise. Fig.1 shows the
power spectral density for different sampling frequency [2].
Power Spectral Density

fs,ny
Frequency in Hz

fs,ny fs = 4fs,ny

Fig. 1. Power spectral density for different sampling frequency

Oversampling results in increased spacing between the alias band and the base band, which in turn
relaxes anti-alias filter. Thus, the area and power of the digital filter shrinks.
Advantage of Short-channel transistors is that, it allows high frequencies which are suitable for
oversampling. The additional band is used in Noise shaping and is used to quantize the analog
signals to the digital world. This technique shifts the quantization energy out of the desired band.
The total noise power in Noise shaper from 0 to fb is
2 2
VLSB
3 (3)
12 3OSR

The oversampling mechanism contributes one OSR; the remaining OSR2 term comes from the
noise shaping circuit. As the OSR increases the noise power decreases, thus increasing the
resolution of the ADC.
Fig.2. Shows the Block diagram of the Sigma-Delta ADC

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 X(z) Y(z)
modulator Quantizer Digital Filter

N(z)

Fig. 2. Sigma-Delta ADC structure

CIRCUIT IMPLEMENTATION

Time-Interleaved Adc
In this section, Sigma-Delta ADC is used as sub-ADC. The operating speed of the Time-
Interleaved ADC can grow linearly by increasing the number of parallel ADC channels, but the
parameters such as offset, gain, timing and bandwidth of sub ADCs must match. The various
types of mismatches among different channels create modulation tones which degrade the
performance of the Time-Interleaved ADC [3]. This circuit is implemented in deep sub-micron
technology node.

Time-Interleaved Architecture

S/H 1 Sub-ADC 1
Analog Digital
MULTIPLXER

input output

S/H 2 Sub-ADC 2

S/H N Sub-ADC N

Fig.3. Time-interleaved architecture

Fig. 3 shows the block diagram of the TI-ADC that is constructed by 8-TI channels.

Phase frequency detector implementation

Fig. 4 The implementation of the PFD

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Here clk and dclk are the two inputs. If clk leads dclk, then Vout remains at logic one as the
D flipflop continues to sample the high level of A and vice versa[4].

Delay lock loop implementation

Fig. 5 Implementation of the Delay locked loop

In the circuit, the phase difference between the Clocks is sensed by a phase detector and a
proportional average voltage, Vout is generated. Using this voltage, the delay of the stages is
adjusted via negative feedback and the technique is termed Voltage Controlled Delay Loop
(VCDL). This topology is called a Delay Locked Loop. (DLL) which is used in ADC to
generate clock phase.

Fig. 6. Implementation of the Sigma-Delta ADC in Time-Interleaved Converter

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SIMULATION RESULTS

Simulation results of Phase Frequency Detector are shown in fig.s 7 and 8. It can be observed that
clk leads dclk by 180.This circuit is tested at 1 kHz and with a biasing voltage of 1.2 V.

Fig.7. Simulated waveform of the PFD Fig.8. Simulated waveform of the PFD

Fig.8. shows the response of the Phase frequency detector, as can be seen frequency of clk is
100Hz and dclk is 90Hz.

Fig.9. Simulated waveform of the Delay lock loop

The simulation result is shown in Fig. 9. It is observed that the average duty cycle error is less than
1%. This paper describes a non-overlapping clock generator for a high-speed, high-resolution
pipelined ADC. The circuit has been verified in a Virtuoso environment by adopting the
differential structure charge pump, a phase frequency detector and a VCDL. The simulation results
indicate that clock generator has a high performance.
Table1 shows the comparision proposed by different authors.

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 Table 1
Author And Technology Work Power
time node ( m) voltage consumption
Traft[5]2004 0.18 1.8V 774mW

Chang[6]2005 0.18 0.9V 12mW

Liu [7] 2007 0.18 1.0V 500W

Rachit[8]2013 0.18 1.5V 9.7nW

This Work Lower 1.2V 85mW

technology
node

CONCLUSION

Based on the study of Sigma-Delta sub ADCs speed and accuracy, this work presents
implementation of Time-interleaved architecture with non-overlapping clock. The converter has
been implemented in Virtuoso environment with BSIM 4.3 device models. The measurement
results have shown that the ADC operates with good consistency with the computed results.

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