ANALYSIS OF LOW POWER SAR ANALOG TO DIGITAL

CONVERTERS
S.B.RASHMI
Department of ECE Don Bosco Institute of Technology,Bangalore
Rashmi_akshay@yahoo.co.in

DR.SIVA S.YELLAMPALLI
UTL Technologies ,Bangalore

SOUMYA S.KENGANAL
Department of ECE Don Bosco Institute of Technology,Banglore
kenganalsoumya@gmail.com

ABSTRACT: In this paper different low power Successive Approximation Register Analog to
Digital converters are analyzed. In analog to digital converters an important block is constructed
by using capacitive DAC. Analysis is performed on different capacitive DAC switching methods
such as monotonic switching method, merged switching method,VCM switching method and VR/2
switching method .Finally comparison is done on different DAC switching methods .

KEYWORDS: DAC, ADC, SAR, monotonic switching method, merged switching method ,VCM
switching method and VR/2 switching method.

INTRODUCTION

A basic analog receiver circuit consist of LNA filters, variable gain amplifier and analog to digital
converters. An ADC is an important component in this design. Varieties of ADCs are available
such as Flash ADC, Dual slope ADC, Integrating ADC,Cyclic ADC,SAR ADC. Flash ADCs and
Dual slope ADCs are working with highest speed with least accuracy,where as SAR ADC are
having good accuracy and achieves low power with minimum speed since it requires several
cycles to complete one cycle. Therefore it is suitable for low speed and low power application.
With the advancement in CMOS technology power dissipation and conversion time can be
reduced.

In this paper different SAR ADCs are discussed. DAC presented in each ADC are constructed by
using different capacitor DAC switching methods such as monotonic switching method merged
switching method and VCM switching method and VR/2 switching method.

BASIC BLOCK DIAGRAM OF SAR ADC

The block diagram of SAR ADC is depicted in figure.1. The important blocks in SAR ADC are
capacitor array DAC, Comparator and control logic.Initially analog inputs are sampled and
compared with the DAC output. Comparator outputs are stored in SAR. SAR outputs are again
converted and compared in comparator till (EOC) End of conversion is reached. The advantage of
SAR ADC is that it designed without an amplifier. The capacitor used in the SAR ADC with
capacitor array works with following phases they are charging, discharging charge redistribution
and sample. In SAR ADCs, the sources of power dissipation are the control circuit that is digital
logic, comparator and capacitive reference DAC network. Dynamic power dissipation is reduced
with the advancement in technology. Speed of the converters are also improved with technology
scaling. The power dissipation of the comparator and capacitor array DAC is limited by mismatch.

Figure.1.Block diagram of SAR ADC

DIFFERENT SAR ADCS

Vcm based switching method

The block diagram of Vcm based switching method for 10-bit fully differential SAR ADCs is as
depicted in figure2. It has two sets of DAC, for better linearity both the DACs uses a binary-
weighted capacitor array rather than a C-2C capacitor array. The fundamental building blocks of
this architecture are the comparator, sample-and-hold (S/H) circuit, capacitor network, and
successive approximation registers.

Figure.2. Block diagram of VCM based switching method

The capacitor charge redistribution DAC behaves as S/H and DAC. Therefore in this architecture
separate S/H circuits can be avoided. Here there are two DACs and operation of both the DACs is
complimentary in nature so the operation of top DAC is explained is as follows. When conversion
started during sampling phase the bottom plate of top ADC is connected to Vip and bottom plate of
the capacitor is connected to VCM The largest capacitor C1 is switched to Vref and all other
capacitors are switched to ground. Then comparator performs the first comparision. If Vip is
greater than Vin then B1=1 or else B1=0.If B1=1 terminal is connected to Vref else it is connected
to ground.

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 Figure.3. Waveform of VCM based switching method

This procedure is continued till the LSB is reached or EOC is reached. This is a trial and error
method it is not the energy efficient method because most of its unsuccessful trials may go waste.
The waveform of Vcm based switching method is as depicted in figure 3. According to the figure
3 if Vip is greater than Vin bit output is 1 else bit output is 0.

Monotonic Switching Method

The monotonic switching block diagram is shown in figure 4 which consists of an ADC, 2 DACs,
a comparator and array of capacitor. The input signals are sampled by ADC via boot-strapping
switches and fed to the top plate of capacitor array. On other hand bottom plate are reset to Vref
.once the bootstrapped switches are turned off by ADC the comparator starts its first comparison
without switching any capacitor. Depending upon the comparator output highest value capacitor
(C1) present in higher voltage potential side is switched to ground and lower one will remain
unchanged.ADC repeat these steps until final LSB value is obtained. In every bit conversion only
single capacitor will be switched which will reduce both charge transfer and transitions.

For an n-bit ADC ,the number of capacitor in a array is 2n-1 i.e monotonic switching method
requires half number of capacitor as of normal ADC. Due to this 50% of capacitor area is reduced
.Since every bit conversion switch only one capacitor power consumption is reduced by 81%.

The Flow chart of monotonic switching method is shown in figure 5. Steps involved in conversion
are listed below:

1. Initialization of V+ and V- value to V+ =Vip and V-=Vin and also Consider i is the
number of iteration and initially i=1.
2. N is number of bits to be converted.
3. Comparison between two sampled inputs is done: If V+ > V- then first bit B1=1 and the V+
value will be updated with respect to Vref ,i.e V+=V+- Vref/2.If V+< V-,then first bit will
remain unchanged B1=0 and again V+ will be updated as above.
4. Now i value is compared with bit number if equal it will stop next comparison ,if not
equal it will now increment the value of i to i+1 and the procedure repeats.

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 Figure 4 Block diagram of monotonic switching method

Figure.5. Flow chart of monotonic switching method

For an n-bit ADC ,the number of capacitor in a array is 2n-1 i.e monotonice switching method
requires half number of capacitor as of normal ADC.Due to this 50% of capacitor area is reduced
.since every bit conversion switch only one capacitor power consumption is reduced by 81%..
According to the figure.6. if V ip is greater than Vin bit output is 1 else bit output is 0. Also observe
Vip and Vin are not dependent on Vcm.

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 Figure.6. Waveform of monotonic switching method

VR/2 Switching Method

Figure .7. Schematics of VR/2 switching method

This switching method uses VR/2 as the reference voltage rather than VR , hence the name which is
shown in figure.7 .This method is designed in order to digitize the input signals within range of [0,
VR ].The digitizing voltages are [2-1, 2-1, 2-1 2-N ] VR are generated by DAC. The largest
digitizing voltage VR/2 is used to generate the MSB. VR /2 design consists of 2 DACs namely
DAC1 and DAC2 .Comparators positive input is connected to DAC1 and negative is connected to
DAC2.Here DAC1 is a dummy capacitor array, of same size as of DAC2.The DAC2 samples the
input signals and DAC1 is used to avoid the error caused in voltage level due to the parasitic
capacitor at DAC2s top plate. The voltage across the capacitor in DAC21 is zero Switching of
DAC2 decide the MSB bit and remaining bitsN-1 are generated by switching of capacitors in
DAC2.The size of the DAC2 is 2N-1 unit capacitors.

The bottom plates of DAC1 and DAC2 are connected to VR/2 to generate the MSB. Voltage
Comparison is done between DAC1 and DAC2 top plates, VR /2 and VR-Vin respectively .If the
Vin> VR /2, DAC1 bottom plates are switched to ground, else it remain at VR /2 only. When the
MSB is generated it charge the parasitic capacitor during which very less power is consumed .the
rest bits are generated similarly to the conventional method ,the only difference is capacitor will
switch between VR /2 and GND. The common mode voltage of this method is (3VR /2- Vin)/2 at the

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MSB. If Vin< VR/2 , common mode voltage is nearly equal to VR/2 at LSB; for Vin > VR/2 ,CM
close to GND at LSB.

Merged Switching Method

Merged capacitor switching technique improves the signal processing speed and resolution of
ADC by reducing the required number of circuit capacitor by half in comparison. This technique
merges two unit capacitors into one capacitor without degrading the performance of other circuit
of ADC .50% of capacitor number can be reduced is a major advantage of this method which in
turn reduce the area of capacitor array.

Figure. 8. MDAC during amplification based on (a) conventional and (b) proposed MCS
techniques.

Figure .8. depicts the merged DAC block diagram of (a)Conventional and (b) proposed MCS
technique. In the Figure.8.(a) have 16 capacitors array and (b)has8 capacitors. The MCS technique
reduce the number of Merged DAC capacitors to the half by merging mechanism of eight pairs of
capacitor (C1&C2,C3&C4,.C15&C16) into 8 new unit capacitor(C1,C2,C3C8) .When two
different references(+VREF and -VREF) applied to the two unit capacitors because of which ground
is required. In figure.8(a) C1 &C2 two pair capacitors are directly mapped to the C1 shown in
figure.8.(b).The 4-b MDAC implementation based on the MCS technique is represented in
figure.11.This consists of 8 unit capacitors whose terminals are connected to the +VREF ,GND, and
VREF .Connection of each unit capacitor bottom plate is done using 4 bit code from the flash ADC
during the amplification.

Fig. 9. The 4-b MDAC implementation based on the proposed MCS technique.

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RESULTS

Table .II.Comparison between various switching techniques.

Monotonic switching VCM based VR/2 based Merged
method method method switching
method
No of unit 128 128 256 64
capacitors
Volt.ref VR,GND VR,VCM,GND VR /2,GND +VR, -VR,GND
DNL (VR o)/24.5C0 (VR o)/24.5C0 (VR o)/24.5C0

CONCLUSION

In this paper study of different SAR ADCs are carried out.The important block of SAR ADC is
digital to analog converter. Different approaches of implementing DACs like monotonic switching
method ,Vcm switching method ,VR/2 switching method ,and merged switching is analysised and
comparison is shown in table.I.

REFERENCES

Chun-Cheng Liu, Soon-Jyh Chang, Guan-Ying Huang and Ying-Zu Lin(2010) A 10-bit 50-
MS/s SAR ADC With a Monotonic Capacitor Switching Procedure.
Weibo Hu, Yen-Ting Liu, Tam Nguyen, DonaldY. C. Lie and Brian P. Ginsburg,(2013), An 8-
Bit Single-Ended Ultra-Low-Power SAR ADC With a Novel DAC Switching Method and a
Counter-Based Digital Control Circuitry.
Sang-Min Yoo,Jong-Bum Park,Seung-Hoon Lee and Un-Ku Moon,(2004), A 2.5-V 10b 120-
MSamples/s CMOS Pipelined ADC Based on Merged Capacitor Switching.
Ying-Zu Lin ,Chun-Cheng Liu, Guan-Ying Huang, Ya-Ting Shyu,Yen-Ting Liu, and Soon-Jyh
Chang,(2013) A 9-Bit 150-MS/s Subrange ADC Based on SAR Architecture in 90-nm CMOS.
Alan Walsh,(2013), Voltage Reference Design for Precision Successive-Approximation
ADCs.
Zhangming Zhu Yu Xiao Weitie Wang Qiyu Wang Yintang Yang(2013), A 0.6 V 100
KS/s 810 b resolution configurable SAR ADC in 0.18 lm CMOS.

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