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  • University of San Carlos Inverter Layout Extraction Lab Report

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    Brendan PG Arcenal Ambayan
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    This document describes a laboratory exercise on designing an inverter layout and extraction. It includes the inverter schematic diagram, component design, layout, and simulation results comparing the schematic and layout. The voltage transfer curve from both the schematic and layout simulations match, with a trip voltage of 799.163mV.

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    ECE512 Exercise 5 final report

    Original Title

    Ambayan Ece512al Exer5 FINALREPORT

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    This document describes a laboratory exercise on designing an inverter layout and extraction. It includes the inverter schematic diagram, component design, layout, and simulation results comparing the schematic and layout. The voltage transfer curve from both the schematic and layout simulations match, with a trip voltage of 799.163mV.

    Copyright:

    © All Rights Reserved
    Download as DOCX, PDF, TXT or read online from Scribd
    Flag for inappropriate content
    21 views4 pages

    University of San Carlos Inverter Layout Extraction Lab Report

    Uploaded by

    Brendan PG Arcenal Ambayan
    This document describes a laboratory exercise on designing an inverter layout and extraction. It includes the inverter schematic diagram, component design, layout, and simulation results comparing the schematic and layout. The voltage transfer curve from both the schematic and layout simulations match, with a trip voltage of 799.163mV.

    Copyright:

    © All Rights Reserved
    Download as DOCX, PDF, TXT or read online from Scribd
    Flag for inappropriate content
    of 4

    University of San Carlos Technological Center

    Microelectronics and IT Laboratory


    ECE512AL

    NAME: Ambayan, Brendan PG A. DATE PERFORMED: September 25, 2017


    SCHEDULE: M 10:30- 1:30 PM INSTRS SIG. Engr. Ellen Agnes M. Zafra

    LABORATORY EXERCISE #5
    Inverter Layout and Extraction
    I. Schematic

    Fig 1. Inverter Schematic Diagram

    II. Component Design

    Fig 2. Inverter Component Design


    III. Layout

    Fig 3. Inverter Layout


    IV. Simulation

    Schematic
    Waveform:

    Fig 4. Inverter VTC Curve using Schematic

    VM= 799.163mV

    Spice Codes:

    Layout
    Waveform:

    Fig 5. Inverter VTC Curve using Layout

    VM= 799.163 mV
    Spice Codes:

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