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A Three-Phase Four-Wire Inverter Control


Technique for a Single Distributed Generation
Unit in Island Mode

Article in IEEE Transactions on Power Electronics February 2008


DOI: 10.1109/TPEL.2007.911816 Source: IEEE Xplore

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322 IEEE TRANSACTIONS ON POWER ELECTRONICS, VOL. 23, NO. 1, JANUARY 2008

A Three-Phase Four-Wire Inverter Control Technique


for a Single Distributed Generation
Unit in Island Mode
Min Dai, Member, IEEE, Mohammad Nanda Marwali, Member, IEEE, Jin-Woo Jung, Member, IEEE, and
Ali Keyhani, Fellow, IEEE

AbstractA control technique is developed for a three-phase There are generally two types of four-wire inverter topolo-
four-wire split dc bus inverter of a single distributed generation giesthree-leg with split dc bus and four-leg. A three-phase
unit working in island mode. The control technique combines three-leg inverter with split dc bus is one topology to implement
an inner discrete-time sliding mode controlled (DSMC) current
loop and an outer robust servomechanism controlled voltage
three-phase four-wire system with a neutral point seen by the
loop. The control algorithms are developed under stationary 0 load. Compared to a three-phase three-wire system, it does not
(Clarkes) reference frame and a modified space vector pulsewidth have the isolation transformer and provides three-dimensional
modulation (MSVPWM) is proposed to implement the algorithm control. Compared to a three-phase four-leg topology, it saves
under Clarkes reference frame. The proposed technique achieves two power switches and reduces control complexity. Therefore
voltage regulation with low steady state error and low total har- the control issues of the three-phase three-leg inverter with
monic distortion and fast transient response under various load
disturbances. Meanwhile the usage of MSVPWM in a stationary
split dc bus warrants detailed research for its best possible
0 reference frame yields better transient performance under performance.
limited dc bus voltage compared to conventional uniformly sam- Although a three-phase three-leg inverter with split dc bus
pled sine wave modulation in reference frame. In this paper, topology is a combination of three half bridge single-phase
besides the development and description of the algorithms, a series inverters and control techniques designed for single-phase
of discussions, analysis and studies are performed on the proposed inverters still work in the three-phase systems, new control
control technique, including the filter design issue, frequency
domain closed-current-loop and closed-voltage-loop responses, problems emerge after the three phases are combined together
and time domain simulations and experiments under various in that the reference frame issue and the PWM issue become
load conditions. All the analysis, simulations, and experiments problems. In this paper, a control technique to be performed
demonstrate the effectiveness of the proposed control solution. in stationary 0 reference frame is suggested together with a
Index TermsCurrent control, inverters, optimal control, power new modified space vector PWM scheme. Besides, the common
conversion, pulsewidth modulation (PWM), robustness, stability, control problems shared by both the three-phase system and
variable structure systems, voltage control. the single-phase half bridge topology will also be addressed by
presenting a new control solution with detailed analysis of its
performances.
I. INTRODUCTION Before being operated in grid-connected mode, a DG unit
N three-phase inverter interfaced distributed generation needs to work in island mode at the first place as a voltage source
I (DG) systems, the inverter can be interfaced with load,
which is typically a four-wire system where the neutral is
supplying local load with quality power. Many researches have
been conducted in this area, which can be categorized based on
grounded, in two different waysa three-wire inverter with a the control techniques usedPID control, model based linear
connected isolation transformer or a four-wire inverter control, robust control, sliding mode control, internal model
without the isolation transformer. Since the isolation trans- principle based control, and intelligent control.
former is bulky, heavy, and costly, it is not desired in many Conventional PI controls have been used in [1][4]. Due to
applications, especially mobile generations. In these cases, the inherent property of PI controls, steady state error cannot
the four-wire transformerless inverters are more preferable. be eliminated for non-dc signals, which limits the performance
of the technique, especially in harmonic load applications. Mul-
tiple rotating reference frames [5], [6] can solve the problem but
increase the complexity in the meantime.
Manuscript received December 2, 2006; revised May 1, 2007. This work was
supported in part by the National Science Foundation under Grants NSF ECS Some researchers use standard linear control theory to de-
0501349 and ECS 0105320. Recommended for publication by Associate Editor velop their controllers, such as [7][9], while the reported re-
P.-T. Cheng. sults were not satisfactory.
M. Dai and M. N. Marwali are with Liebert AC Power Systems, Emerson
Network Power, Delaware, OH 43015 USA. Lee et al. [10] have applied design procedure onto a
J.-W. Jung is with Samsung SDI Co., Ltd., Seoul, Korea. single-phase inverter to improve robust stability under model
A. Keyhani is with The Ohio State University, Columbus, OH 43210 USA uncertainty and load disturbance. However, the control perfor-
(e-mail: keyhani.1@osu.edu).
Color versions of one or more of the figures in this paper are available online
mance under nonlinear load is not satisfactory.
at http://ieeexplore.ieee.org. Discrete-time sliding mode control technique has also been
Digital Object Identifier 10.1109/TPEL.2007.911816 used in inverter control due to its robustness and overshoot-free
0885-8993/$25.00 2007 IEEE
DAI et al.: THREE-PHASE FOUR-WIRE INVERTER CONTROL TECHNIQUE 323

fast tracking capability, such as in [11][13]. However, its de-


pendence on knowledge of the control plant limits its applica-
tion as an outer loop controller in multi-loop feedback systems.
Internal model principle states that asymptotic tracking of
controlled variables toward the corresponding references in the
presence of disturbances (zero steady state tracking error) can
be achieved if the models that generate these references and dis-
turbances are included in the stable closed loop systems [14].
Repetitive control is a specific implementation of internal
model principle in a single reference frame, which eliminates
periodical tracking error or disturbance whose frequency is less
than half sampling frequency, and has been applied to inverter
control as shown in [15][22]. The general problem with repeti- Fig. 1. Three-phase four-wire inverter with a split dc bus.
tive control is its inherent slow response and lacking of system-
atical method of stabilizing.
Different from repetitive control, internal model principle can
be used only to eliminate periodical tracking error and distur-
bance with specified frequencies, which is generally enough for
inverter control for DG applications since total harmonic dis-
tortion (THD) is mainly caused by low order harmonics. All
works in this area take advantage of the concept of generalized
integrator [23] and resonant regulator [24][33]. This concept
solves the mode tracking and rejecting problem but still lacks
systematical method of stabilizing. Fig. 2. Per-unit one dimensional equivalent model of the inverter system.
In this paper, a new control technique combining robust ser-
vomechanism control and discrete-time sliding mode control
will be proposed. This technique yields fast current tracking three-phase load voltages, , , and , are the
and moreover exhibits zero steady state error for fundamental same as the filter capacitor voltages. The three-phase load
voltage and strong rejecting capability for harmonic distur- currents are , , and .
bances. Given the filter series resistance , inductance and ca-
Although uniformly sampled sine-wave PWM is typically pacitance , after converting the quantities from refer-
used in a three-phase four-wire system where there are three ence frame into Clarkes stationary 0 reference frame, ap-
independent degrees of freedom, a modified space vector PWM plying symmetry of the three dimensions, and conducting per-
technique is proposed in this application due to its advantage unit transformation, the system model can be reduced into a
under low dc bus voltage. This PWM scheme has been seen in single-phase per-unit equivalent circuit as depicted in Fig. 2 and
[34], [35] but only used for minimizing 0-axis leakage current represented by
in motor drives and never used in applications with large 0-axis
current. (1)
In this paper, the control plant modeling is presented in where the state variable , the control input
Section II, the control algorithm development is described in , the disturbance input , and the coefficients
Section III, and Section IV includes performance analysis,
simulation, and experimental results. and

II. CONTROL PLANT MODELING and


The three-phase four-wire DG unit studied in this dissertation
has a topology shown in Fig. 1. The inverter has a three-phase
three-leg plus split dc bus topology, where the top and bottom
halves of the dc bus are assumed to be evenly distributed and
supplied by ideal dc voltage sources which can be implemented where 2 2 60 120 rad/s is the fun-
practically by a dc voltage regulated front end energized by any damental angular frequency, with the base values defined by
distributed sources, such as fuel cells, photovoltaic devices, and 1/3 , , , and
wind turbines. The inverter outputs are connected to a three- .
phase second order filter and the filter output voltage is
supplied to the load. III. CONTROL SYSTEM DEVELOPMENT
The circuit defined in Fig. 1 uses the following quanti- Given the above per-unit plant model, a dual loop control
ties to describe its behavior. The three-phase inverter output structure is proposed in this research. The inner loop is for in-
line-to-neutral PWM voltages are , , and . verter current control. A discrete-time sliding mode controller
The three-phase inverter output currents, which also flow (DSMC) is applied. The outer loop is for the load voltage con-
through the filter inductor, are , , and . The trol. A discrete-time robust servomechanism controller (RSC)
324 IEEE TRANSACTIONS ON POWER ELECTRONICS, VOL. 23, NO. 1, JANUARY 2008

i.e., the tracking error, such that when the discrete-time sliding
mode exists, the output tends to the reference . Dis-
crete-time sliding mode can be reached if the control input u(k)
is designed to be the solution of

(3)
Fig. 3. Proposed control system block diagram. The control law satisfies (3) is called equivalent control [36] and
is given by

is used as the voltage controller. The entire closed-loop system (4)


can be illustrated by Fig. 3. and .
In Fig. 3, MSVPWM is a modified space vector pulse width The actual control voltage applied to the filter stage is
modulation inverter, is the reference load voltage, is the inverter output PWM voltage , which is limited by
the desired inverter current command, is the true inverter the available top and bottom half dc bus voltages. The control
current command, is the PWM voltage command, and force limitation caused by the dc bus voltage will be discussed
is the true modulated inverter output voltage. A current
in Sections III-C and IV-D.
limiter is added between the two loops for over-current protec-
tion. The detailed development of each module will be described B. Design of the Robust Servomechanism Voltage Controller
in the following subsections.
The goal of designing a realistic multivariable controller to
solve the robust servomechanism problem [37] is to achieve
A. Design of the Discrete-Time Sliding Mode Current closed-loop stability and asymptotic regulation, as well as other
Controller desirable propertiesfast response, robustness, etc. The solu-
tion, so called the RSC, combines both the internal model prin-
A DSMC is an implementation of the sliding mode control ciple and optimal control. The internal model principle says
theory in discrete-time. Unlike its continuous-time counterpart, that a regulator synthesis is structurally stable only if the con-
which is known for having a discontinuous control law due to a troller utilizes feedback of the regulated variable, and incorpo-
sign function, the discrete-time sliding mode is achieved with rates in the feedback path a suitably reduplicated model of the
a continuous control law. Direct implant of continuous-time dynamic structure of the exogenous signals which the regulator
sliding mode control law into discrete-time causes chattering is required to process [14]. Using the internal model principle
problem due to the sampling effects. However, the DSMC to a linear time-invariant (LTI) plant, asymptotic tracking of
does not have the problem and achieves one-step tracking for controlled variables toward the corresponding references in the
any reference input with a bandwidth lower than half of the presence of disturbances (zero steady state tracking error) can be
sampling frequency given unlimited control force. If the control achieved if the models that generate these references and distur-
force is limited, the sliding mode manifold can be reached bances are included in the stable closed loop systems. A simple
in finite number of steps [36]. Since the control law of the form of optimal control techniquelinear quadratic controller
DSMC is continuous from discrete-time point of view, it can is used to obtain the feedback gain satisfying a certainly defined
be implemented in practice using pulse width modulation with optimization criterion. By minimizing this criterion, the eigen-
a fixed switching frequency. Continuous-time sliding mode values of the state space model will be automatically placed and
control on an inverter typically results in varying switching the feedback gains will be uniquely selected. The optimization
frequency which may cause more harmonics. With known plant criterion chosen is a functional of quadratic forms in the space
parameters and enough control force, the DSMC control law is of the state vector and the input of the system [38].
equivalent to deadbeat control in formula. The most attractive In the outer loop, the reference input is the desired DG unit
property of the DSMC is its overshoot free fast response. output voltage which is a 60 Hz sinusoidal signal, the distur-
For the control plant given in (1), the discrete-time sliding bance is the load current, which may contain harmonic fre-
mode control law can be derived as follows. quency components besides the fundamental. In practice, all
Given a sampling period of and assuming zero order hold, high frequency harmonics have already been suppressed by the
the plant for inverter current control can be discretized as filter and the major components that may affect the system
control performance are low harmonics, typically third, fifth,
(2) and seventh order harmonics, etc. The higher the order of the
harmonic, the less effect it can cause to the performance. There-
fore, the dynamics of the tracking or rejecting signals are known,
where , , which are governed by poles at , , , and ,
, and . To let the current output etc., where 2 60 rad/s, 3 , 5 , and
of next step track the reference input , a 7 , etc.
discrete-time sliding mode manifold can be chosen in the form The control plant of the RSC is the entire inner loop. Since
of the DSMC serves as the controller for in the inner loop, its dy-
namics has to be included together with the original plant to
form the control plant for the RSC. Given the plant as shown in
DAI et al.: THREE-PHASE FOUR-WIRE INVERTER CONTROL TECHNIQUE 325

(1) and a sampling period of , assuming zero order hold and


half sampling period input delay, the discretized plant is

(5)
where , ,
, , and .
Due to the existence of , it is reasonable to convert the
plant model in (5) into standard state space format as

(6)

where ,

Fig. 4. Block diagram of the servo compensator.

and .
After the dynamics of the DSMC shown in (4) is included, for 1, 3, 5, and 7.
the overall plant for the RSC becomes The transfer function representation of the servo compensator
is illustrated in Fig. 4, which shows that the servo compensator
consists of a series of resonant filters with their resonant fre-
(7) quencies equal to the specified tracking or rejecting frequencies.
The servo compensator needs to be discretized in practice.
where the new control signal is Given the same sampling period as above, the discrete-time
servo compensator is

(9)

and where and .


In existence of the servo compensator, the stabilizing com-
pensator can be generated.
An augmented system combining both the plant (7) and the
where servo-compensator (9) can be written as

(10)
Given the above plant, the RSC design includes two partsa
servo compensator and a stabilizing compensator. where the reference input is , the state vector
The servo compensator can be designed as follows. If the is , and the coefficient matrices are
tracking/disturbance poles to be considered are , ,
, and , the servo-compensator is

(8)

where , ,

and

and , and voltage regulation error

, where
The task of the stabilizing compensator is to stabilize the aug-
mented system in (10). To achieve this goal, the discrete-time
optimal control technique can be used, which guarantees
326 IEEE TRANSACTIONS ON POWER ELECTRONICS, VOL. 23, NO. 1, JANUARY 2008

Fig. 5. Block diagram of the RSC.

stability of the system while yields optimized performance by


minimizing a discrete-time linear quadratic performance index
Fig. 6. Base vectors of space vector PWM in 2-D space and the modulation:
(a) six base vectors and (b) modulation of a reference voltage in Sector I.
(11)

TABLE I
where is a symmetrical positive-definite matrix to be chosen OUTPUT VOLTAGE PATTERNS OF BASE VECTORS
IN THE FOUR-WIRE SPLIT DC BUS TOPOLOGY
and 0 is a small number to reduce the weight of the control
force in the optimization. In practice, is typically chosen as
diagonal where the weights on the servo states are significantly
greater than those on the plant states for the best performance.
Moreover, the selection of also affects the robustness of the
stability when the plant parameters have variation from their
nominal values [39].
Obtaining the state feedback gain minimizing requires
solving the algebraic Riccati equation

(12)

for the unique positive semidefinite solution , so that

(13) same plane rotating from one sector to another with a constant
speed. In each sector, the reference vector can be achieved by
Then the control input can be obtained as time-averaging the two boundary base vectors and two zero vec-
tors with proper weights, as illustrated in Fig. 6(b) showing the
(14) case of Sector I, where is half of the PWM period, is the
duration of Vector 1 and is the duration of Vector 2 in a half
PWM period. The remaining time is the dura-
The block diagram of the RSC is shown in Fig. 5. tion for the zero vectors. The values of and are calculated
In practice, the discrete-time algebraic Riccati equation can based on the values of and .
be solved using the Matlab function . Since the system In three-phase three-wire systems, the three phases are not
is linear time-invariant, the feedback gain is a constant value independent, i.e., there exist only two independent degrees
calculated in advance and does not change in operation. There- of freedom and the conventional SVPWM only provides
fore, online updating of is unnecessary. two-dimensional control. However, in a three-phase four-wire
system with split dc bus topology, the neutral of the load is
C. A Modified Space Vector PWM
grounded, which yields three independent phases and calls for
The SVPWM is a specially designed switching sequence for three-dimensional control. In this topology, Vectors 7 and 8
the power switches in a three-phase inverter using base space are no longer zero vectors in terms of line-to-neutral voltages.
vectors to generate three-phase 120 apart sinusoidal line-to- The output voltages of the split dc bus inverter are shown in
line output voltages. This technique treats the sinusoidal refer- Table I. From Table I, it can be observed that Vectors 7 and
ence voltage as a constant amplitude vector rotating at a certain 8 provide non-zero line-to-neutral voltages which is the third
frequency. There are eight base vectors, i.e., Vectors 1 to 8, cor- dimensionthe 0-axis quantity.
responding to eight possible switching patterns of the inverter. A modified space vector PWM technique (MSVPWM) has
Vectors 1 to 6 generate non-zero output voltages and Vectors 7 been developed to take advantage of the Vectors 7 and 8 to
and 8 generate zero output voltage by connecting all three out- achieve three-dimensional control in an 0 system.
puts to the upper or bottom rail of the dc bus. In conventional SVPWM, the durations of Vectors 7 (000)
The base vectors can be depicted geometrically as shown in and 8 (111) are equal in a half PWM period and there is no 0-axis
Fig. 6(a), where the consecutive non-zero vectors on a plane control capability. However, in MSVPWM, unequal durations
form six 60 sectors representing a full sinusoidal period. A si- of Vectors 7 and 8 cause uneven 0-axis average voltage in a
nusoidal reference signal can be represented by a vector on the PWM period and allow 0-axis current to flow, which enables
DAI et al.: THREE-PHASE FOUR-WIRE INVERTER CONTROL TECHNIQUE 327

the durations of Vectors 7 and 8 are

for
for (20)
for

and

for
for , (21)
for .

The benefit of this MSVPWM is that it provides three-dimen-


sional control for three-phase four-wire split dc bus topology in-
herently in the stationary reference frame, which performs
better than direct reference frame control when the dc bus
voltage is limited. Further analysis results verifying this state-
ment will be presented in Section IV-D. The trade-off of this
technique is that it has less dc bus voltage utilization in that
the maximum reference voltage in the conventional SVPWM is
and that in the MSVPWM is
.

Fig. 7. Sector I on-off sequence of modified space vector PWM. IV. PERFORMANCES AND ANALYSIS

A. Frequency Domain Analysis


the inverter to perform control in all , , and 0 axes. A Sector A 5-kVA DG unit with three-phase four-wire split dc bus
I illustration is shown in Fig. 7, where is the time duration of topology as shown in Fig. 1 is analyzed. The rectifier is as-
Vector , 1 8. sumed to supply dc voltages regulated at 270 V. The rated
Calculation of the vector durations in MSVPWM is shown rms line-to-neutral three-phase ac output voltage is 120 V. The
below, using Section I as an example. Given three dimensional discrete-time control frequency, as well as the PWM switching
reference voltage inputs, , , , and the PWM period , frequency, 1 is set to be 5.4 kHz.
the plane reference voltage is A three-phase filter is selected with 10.2 mH and
55 F. This filter has a natural frequency of 1335.1 rad/s
(15) and damping ratio of 0.0367, where a line/coil resistance of 1
is assumed. Greater values of and yield better filter perfor-
its phase angle is mance but large leads to high weight and volume and large
leads to high capacitor current at no load. Therefore the se-
(16) lection of and is usually a trade-off and the values can be
selected to yield a cut-off frequency lower than 10th harmonic
and the modulation index is frequency, which filters out high frequency components, leaves
lower frequency components for the control to handle, and keep
(17) the weight and volume within a reasonable range. In the split
bus topology, the filter input voltage, i.e., could never be
zero, which tends to cause high switching frequency current. In
As mentioned above, is the half PWM period. order to suppress this current, a higher is necessary especially
The Vector 1 duration is when the switching frequency is not high.
In order to analyze the close loop systems, a per-unit induc-
(18) tive load current 0.8 0.6 is assumed. When the current con-
trol loop is closed while the voltage loop remains open, the fre-
quency response of the current controlled system
and the Vector 2 duration is

(19)

is shown in Fig. 8. The responsiveness of the closed-loop control


The sum of the Vector 7 and 8 durations is .
can be measured by bandwidth which is the frequency where the
After defining
gain falls to 3 dB. In Fig. 8, it can be observed that the closed-
loop system has a bandwidth greater than 1 kHz, which explains
the fast response of the current control. Ideally, without the input
328 IEEE TRANSACTIONS ON POWER ELECTRONICS, VOL. 23, NO. 1, JANUARY 2008

TABLE II
SIMULATION RESULTS OF STEADY STATE PERFORMANCES
OF THE PROPOSED CONTROL TECHNIQUE

state and transient. A computer simulation software Matlab with


Simulink SimPowerSystems Blockset is used.
Fig. 8. Bode plot of the closed loop current controlled system. Steady state rms output voltages and THDs under different
types of load have been presented in Table II. The load types in-
clude 5 kVA balanced resistive load, unbalanced resistive load
with phase opened, 5 kVA inductive load with 0.8 power
factor, no load, and nonlinear load with crest factor 3:1, where
the crest factor is equal to the peak amplitude of a waveform
divided by the rms value. The nonlinear load in each phase can
be created by a single phase full-bridge diode rectifier loaded
by a 4000 F capacitor and a 50 resistor in parallel. It can be
observed from the table that the proposed control technique re-
sults nearly zero steady state error and THD lower than 1% for
all tested load types except the crest load.
The output waveforms of load voltages, load currents, in-
verter currents, rms load voltages, and ground current in the two-
phase unbalanced load and nonlinear load scenarios are shown
in Columns 1 and 2 of Fig. 10. In the balanced load scenarios, the
0-axis ground current, including the capacitor current, does not
Fig. 9. Bode plot of the closed loop voltage controlled system. have low frequency components besides switching frequency.
However, in the unbalanced load cases, the ground current has a
fundamental component and in the nonlinear load case, it con-
time delay caused by the microprocessor, the bandwidth of the tains load current of each phase plus filter currents of all three
DSMC could reach half of the sampling frequency. phases. The transient responses of the control have been demon-
The closed-loop voltage control system has a transfer func- strated in Columns 3 and 4 of Fig. 10, where a full resistive
tion load is instantaneously applied to or removed from the output
terminal. The plots show that the voltage waveforms are only
slightly affected by the load transients and restored to steady
state in very short period of time, i.e., the waveform dents last
for only 2 ms, the rms values show about 2 V deviations on each
transient, which last for about 20 ms.

C. Experimental Results
Experimental tests of the proposed control technique have
been performed on a 5 kVA prototype system with parameters
the same as above. The power converter uses SEMIKRON
SKM 50 GB 123D IGBT modules. A Texas Instruments
TMS320LF2407A digital signal processor (DSP) with a Spec-
with its frequency response shown in Fig. 9. It can be observed trum Digital evaluation module (EVM) has been used as the
that, with the existence of the RSC, all tracking/rejecting fre- digital controller.
quencies have unity gain and zero phase angle which are de- The steady state test results have been presented in Table III.
sired. It can be observed from the table that the three-phase output
voltages achieve satisfactory tracking accuracy and balancing
B. Time Domain Simulations
with THD lower than 1% for all types load except nonlinear.
Time domain simulations of the closed system have been The test waveforms have been shown in Fig. 11. It can be ob-
performed under various load scenarios, including both steady served from the plots that the experimental results resume their
DAI et al.: THREE-PHASE FOUR-WIRE INVERTER CONTROL TECHNIQUE 329

Fig. 10. Simulations under selected scenariosColumn 1: unbalanced resistive load; Column 2: nonlinear load with crest factor 3:1; Column 3: transient response,
load steps up from 0% to 100%; Column 4: transient response, load steps down from 100% to 0%; Trace 1: output voltages; Trace 2: load currents; Trace 3: inverter
currents; Trace 4: rms output voltages; Trace 5: ground current.

Fig. 11. Experimental results under selected scenariosColumn 1: unbalanced resistive load; Column 2: nonlinear load with crest factor 3:1; Column 3: transient
response, load steps up from 0% to 100%; Column 4: transient response, load steps down from 100% to 0%; Upper trace: output voltages, 43 V/div; Middle trace:
load currents, 5 A/div for Column 2 and 10 A/div for others; Lower trace: ground currents, 5 A/div for Column 2 and 20 A/div for others.

TABLE III
EXPERIMENTAL RESULTS OF STEADY STATE PERFORMANCES performance point of view. In other words, in linear modulation
OF THE PROPOSED CONTROL TECHNIQUE area, the control performances of the two modulation strategies
are comparable. If this statement is true again, it can be demon-
strated that the statement becomes untrue when the modulation
index approaches 1 due to the limited dc bus voltage or high
modulation references.
When the modulation index approaches 1, as shown by
the algorithm in Section III-C, approaches and the
space for 0-axis modulation tends to zero. This strategy implies
a higher priority for the modulation of axes than that of the
simulation counterparts respectively, so that the effectiveness of 0-axis when the dc bus voltage is limited. In other words, when
the proposed control technique has been further proved. the 0-axis modulation is saturated at , the modulation of
references can still be linear, which provides more linear control
D. Stationary 0 Reference Frame versus Reference on the fundamental and other non-zero axis harmonics. This is
Frame not the case in sine wave PWM, where the total modulation ref-
One simulation research has been performed comparing the erence is saturated as the modulation index approaches 1 given
performances of conducting the controls in stationary ref- the condition that over-modulation is not allowed due to its neg-
erence frame vs. reference frame. It is natural to use the ative impact on the modulation. The saturation affects all , ,
MSVPWM if the 0 reference frame is used and to use con- and 0 axis components since there is no priority among them.
ventional sine wave PWM if the reference is used. A simulation comparison has been conducted to demonstrate
As reported in [40], [41], mutual-transformable relation- that the above difference about the reference frames does matter
ship can be constructed between the conventional SVPWM in the control performance. In the simulations using two dif-
and USPWM, i.e., uniformly sampled sine wave PWM, in ferent reference frames, the same load, the same filter, the
three-phase three-wire system. It is imaginable that there exists same dc bus voltage 257.5 V, and the same controllers, are
a similar relationship between the MSVPWM and sine wave used for the comparison purpose. The comparison scenario is
PWM in three-phase four-wire system while the detailed proof nonlinear load walk-in transient where the output voltage in-
deserves further investigation. If this is true and the harmonic creases from 0 at time 0 with no load and reaches 100% at time
issues in the switching frequency and vicinity are ignored, 0.1 s and the nonlinear load current increases from 0 at time 0.1
conditional equivalence between the two modulation strategies s and its peak reaches full scale, i.e., 20 A, at time 0.2 s. Fig. 12
in linear modulation area can be conceivable in terms of control shows the transient output voltage THD performances of the two
330 IEEE TRANSACTIONS ON POWER ELECTRONICS, VOL. 23, NO. 1, JANUARY 2008

and closed-voltage-loop responses, and time domain simula-


tions and experiments under various load scenarios. All these
analysis, simulations, and experiments have demonstrated the
effectiveness of the proposed control solution.

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Appl. Power Electron. Conf. Expo (APEC05), Austin, TX, Mar. 2005, the M.S. degree in computer science from the Uni-
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decoupling with global asymptotic stability for nonlinear systems, Au- University, Columbus, in 2005.
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in stationary reference frame for d-statcom in unbalanced operation, B.S.E.E. degree from The Institut Teknologi Ban-
IEEE Trans. Ind. Electron., vol. 51, no. 2, pp. 401409, Apr. 2004. dung, Bandung, Indonesia, in 1993 and the M.S.E.E.
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48, no. 2, pp. 334343, Apr. 2001. He is now with Power R&D, Liebert AC Power
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for voltage-type PWM rectifiers to realize zero steady-state control His research interests are in the area of control of un-
error in input current, IEEE Trans. Ind. Appl., vol. 34, no. 3, pp. interruptible power supplies, distributed generation
480486, May/Jun. 1998. systems, electric motor drives, and power converters.
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proved transient and steady state voltage regulation for single and three
phase uninterruptible power supplies, in Proc. IEEE Power Electron.
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498503. Jin-Woo Jung (M06) received the B.S. and M.S.
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filters based on a sinusoidal internal model, IEEE Trans. Ind. Appl., University, Seoul, Korea, in 1991 and 1997, respec-
vol. 37, no. 3, pp. 888895, May/Jun. 2001. tively, and the Ph.D. degree from the Department
[31] D. N. Zmood, D. G. Holmes, and G. H. Bode, Frequency-domain anal- of Electrical and Computer Engineering, The Ohio
ysis of three-phase linear current regulators, IEEE Trans. Ind. Appl., State University, Columbus, in 2005.
vol. 37, no. 2, pp. 601610, Mar./Apr. 2001. From 1997 to 2000, he worked at Digital Ap-
[32] D. N. Zmood and D. G. Holmes, Stationary frame current regulation pliance Research Laboratory, LG Electronics Inc.,
of PWM inverters with zero steady-state error, IEEE Trans. Power Seoul, Korea. He is currently with Corporate R&D
Electron., vol. 18, no. 3, pp. 814822, May 2003. Center, Samsung SDI, Seoul, Korea. His research
[33] P. Mattavelli, Synchronous-frame harmonic control for high-perfor- interests are in the area of distributed generation sys-
mance ac power supplies, IEEE Trans. Ind. Appl., vol. 37, no. 3, pp. tems, fuel cell systems, electric machines, ac motor drives, power converters,
864872, May/Jun. 2001. and control.
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and triangle-comparison methods, IEEE Trans. Ind. Appl., vol. 33, no.
3, pp. 756764, May/Jun. 1997.
[35] D. C. Lee, A common mode voltage reduction in boost rectifier/in- Ali Keyhani (S72M76SM89F98) was with
verter system by shifting active voltage vector in a control period, Hewlett-Packard Company and TRW Control,
IEEE Trans. Power Electron., vol. 15, no. 6, pp. 10941101, Nov. 2000. from 1967 to 1972. Currently, he is a Professor of
[36] V. Utkin, J. Guldner, and J. Shi, Sliding Mode Control in Electro- electrical engineering at The Ohio State University
mechanical Systems. Philadelpha, PA: Taylor & Francis, 1999. (OSU), Columbus. He serves as the Director of
[37] E. J. Davison and B. Scherzinger, Perfect control of the robust servo- OSU Electromechanical and Mechatronic Systems
mechanism problem, IEEE Trans. Automat. Contr., vol. AC-32, no. 8, Laboratory. His research activities focus on the
pp. 689702, Aug. 1987. control of distributed energy systems, design and
[38] J. S. Bay, Fundamentals of Linear State Space Systems. New York: modeling of electric machine, control and design
WCB/McGraw-Hill, 1999. of power electronic systems, DSP-based virtual test
[39] M. N. Marwali, M. Dai, and A. Keyhani, Robust stability analysis of bed for design, control of power systems, automotive
voltage and current control for distributed generation systems, IEEE systems, modeling, parameter estimation, and failure detection systems.
Trans. Energy Convers., vol. 21, no. 2, pp. 516526, Jun. 2006. Dr. Keyhani received the OSU College of Engineering Research Award
[40] S. R. Bowes and Y. S. Lai, The relationship between space-vector in 1989, 1999, and 2003. He was an Editor for the IEEE TRANSACTIONS ON
modulation and regular-sampled PWM, IEEE Trans. Ind. Electron., ENERGY CONVERSION and past Chairman of the Electric Machinery Com-
vol. 44, no. 5, pp. 670679, Oct. 1997. mittee, IEEE Power Engineering Society.

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