IEEE TRANSACTIONS ON INDUSTRIAL ELECTRONICS, VOL. 62, NO.
6, JUNE 2015 3683
Control of DC-Fault-Resilient Voltage Source
Converter-Based HVDC Transmission System
Under DC Fault Operating Condition
Nima Yousefpoor, Student Member, IEEE, Ajit Narwal, and
Subhashish Bhattacharya, Senior Member, IEEE
AbstractVoltage source converter (VSC)-based high-
voltage direct current (HVDC) transmission systems have
attractive advantages compared to classical thyristor-
based HVDC transmission systems. However, VSC-based
HVDC transmission systems are vulnerable to dc side
fault, and expensive dc circuit breakers are required to
protect them against dc fault. This paper proposes a control
method of a dc fault-resilient VSC which can be protected
against dc fault without using expensive dc circuit break-
ers. In the VSC conguration, several H-bridge modules
are connected in cascade, so the voltage balancing control
of several oating dc capacitors is required. In this paper,
an appropriate control structure with the capacitor voltage
balancing controller is proposed. The appropriate control
algorithm for dc fault operation and recovery after dc fault
is also proposed. PSCAD simulation results are presented
to validate the proposed control structure under normal and
dc fault operating conditions. Real-time-digital-simulator
results are also presented to verify the control structure.
Index TermsCapacitor voltage balancing controller, dc
fault, high-voltage direct current (HVDC) transmission sys-
tems, recovery after dc fault, voltage source converter
(VSC).
I. I NTRODUCTION
V OLTAGE source converter (VSC)-based high-voltage di-
rect current (HVDC) transmission systems have attractive
features compared to classical thyristor-based HVDC transmis-
sion systems. Flexibility in bidirectional power flow control is
the main advantage of VSC-based HVDC transmission systems
[1], [2]. However, the VSC-based HVDC transmission system
is susceptible to dc side fault, and expensive dc circuit breakers
are necessary to protect the converter against dc fault [3], [4].
DC circuit breakers can be used to achieve dc fault clearance,
but the availability of dc circuit breakers with high-voltage and
large current is so limited [5]. Recently, several topologies with
dc fault ride through capability have been proposed. A full-
bridge modular multilevel converter [6] can clear dc-link fault
current. However, in this topology, the galvanic isolation is
not provided in the VSC configuration. In HVDC transmission
systems, the proposed structure should be able to provide
Manuscript received April 30, 2014; revised August 20, 2014 and
September 29, 2014; accepted October 24, 2014. Date of publication
November 20, 2014; date of current version May 8, 2015.
The authors are with North Carolina State University, Raleigh,
NC 27695 USA (e-mail: nyousef@ncsu.edu; anarwal@ncsu.edu;
sbhattacharya@ncsu.edu).
Color versions of one or more of the figures in this paper are available
online at http://ieeexplore.ieee.org.
Digital Object Identifier 10.1109/TIE.2014.2371431
0278-0046 2014 IEEE. Personal use is permitted, but republication/redistribution requires IEEE permission.
See http://www.ieee.org/publications_standards/publications/rights/index.html for more information.
the isolation between two different high-voltage sources. This
paper proposes a control method of a dc fault-resilient converter
with high-frequency isolation and ultrafast electronic isolation
capability following dc fault which can be protected against
dc fault without using expensive dc circuit breakers. In this
topology, the high-frequency isolation is also provided [7].
In the VSC configuration proposed in [7], several ac/dc mod-
ules in all three phases are connected in series, so the voltage
balancing control of multiple floating dc capacitors is required.
In this paper, the phase voltage balancing controller is pro-
posed to ensure that the sum of capacitor voltages of A-phase
is equal to the sum of capacitor voltages of B-phase and
C-phase. The common-mode point voltage is used to perform
phase voltage balancing control. The module voltage balancing
controller [8], [9] is also used to guarantee that the capacitor
voltage of each module in each phase is similar to the capacitor
voltage of other modules in that phase.
Both dc cables and overhead transmission lines can be used
for the HVDC transmission systems. Although dc cables are
mostly used, the application of dc cables in some mountainous
areas is limited. In these areas, dc overhead lines are used. In dc
overhead lines, dc-link short circuit is so common because of
insulation breakdown following lightning strikes [10], [11]. In
this paper, the detailed control algorithm is proposed to protect
the VSC-based HVDC transmission systems against dc faults
on dc overhead lines.
In the following, this paper is organized as follows. In
Section II, the VSC-based HVDC transmission system config-
uration is briefly explained. In Section III, the control structure
of the VSC configuration under normal operating condition
is proposed. In Section IV, the appropriate control algorithm
for dc fault operating condition and recovery after dc fault is
presented. Section V explores the dynamic performance of the
VSC-based HVDC system under dc fault operating condition
through PSCAD simulation. In Section VI, real-time digital
simulator (RTDS) simulation results are presented to verify the
proposed control algorithms. Finally, Section VII presents the
concluding remarks.
II. VSC-B ASED HVDC T RANSMISSION
S YSTEM C ONFIGURATION
In this section, the configuration of the VSC-based HVDC
transmission system is explained. The configuration of the
VSC-based HVDC transmission system is shown in Fig. 1.
Every power conversion module consists of two stages: the
3684 IEEE TRANSACTIONS ON INDUSTRIAL ELECTRONICS, VOL. 62, NO. 6, JUNE 2015
Fig. 1. VSC-based HVDC transmission system.
Fig. 2. Power conversion module with high-frequency link dc/dc
converter.
ac/dc converter and high-frequency link dc/dc converter as
shown in Fig. 2. As can be seen, the isolation is also provided
by the high-frequency transformer in the dc/dc converter.
III. C ONTROL S TRUCTURE OF VSC-B ASED HVDC
T RANSMISSION S YSTEM
In this section, the control scheme of the VSC-based HVDC
transmission system is presented. In this configuration, several
floating dc capacitors in all three phases are connected in
series. Therefore, the voltage balancing algorithm is required to
match the dc capacitor voltages in all power electronic building
blocks. The voltage balancing algorithm is implemented in
ac/dc submodule. The control scheme for the ac/dc submodule
has four layers, including the power flow controller, dc-bus volt-
age controller, phase voltage balancing controller, and module
voltage balancing controller. The detailed control scheme of
each layer is shown in Fig. 3. In the following, each part of
the proposed controller will be explained in detail.
A. Power Flow Controller
The power flow controller determines the reference value of
the dc-bus voltage of each terminal. For power flow control, the
dc overhead line can be simply modeled with the inductor and
resistor as shown in Fig. 4. The dc-bus voltage at the sending-
end and receiving-end terminals can be defined as (1) and (2),
respectively. The transferred power is defined as the average
power of the sending-end and the receiving-end power as
VdcT 1 = Vdcave + 0.5V (1)
VdcT 2 = Vdcave 0.5V (2)
VdcT 1 + VdcT 2
P = Vdcave Idc = Idc . (3)
2
The dc current can be determined with the dc grid resistance
and the voltage difference between two terminals as (4). There-
fore, the transferred power can be rewritten with the dc grid
resistance and the voltage difference between two terminals as
(5). The power flow controller can be implemented as shown
in Fig. 3(a). As can be seen, the reference values of the dc-bus
voltage for both terminals can be determined according to the
reference value of active power flow
V
Idc = (4)
Rdc
V VdcT 1 + VdcT 2 V
P = Vdcave = . (5)
Rdc 2 Rdc
B. Terminal DC-Bus Voltage Controller
The terminal dc-bus voltage controller generates the dq-axis
current references in the synchronous reference frame. Fig. 3(b)
shows the terminal dc-bus voltage controller with the ac current
controller in detail.
C. Phase Voltage Balancing Controller
If each phase has N power conversion modules, the sum
of N capacitor voltages of A-phase should be balanced with
the sum of N capacitor voltages of phase-B and phase-C. The
phase voltage balancing can be achieved by controlling the
common-mode voltage. Each phase power can be calculated by
the multiplication of phase voltage and phase current as (6).
Based on (6), the phase power can be written as (7)(9). When
the common-mode voltage is considered as (10), the phase
power can be expressed as (11)(13). Each phase power has
an average value and a second-order harmonic component. The
average value of each phase power can be written as (14)(16).
The average value of each phase power with the common-mode
voltage can be written in the stationary reference frame as (17).
va = Vm cos(t); ia = Im cos(t + i )
vb = Vm cos(t 2/3); ib = Im cos(t + i 2/3) (6)
vc = Vm cos(t + 2/3); ic = Im cos(t + i + 2/3)
Pa = va ia = 0.5Vm Im cos(i ) + 0.5Vm Im cos(2t + i ) (7)
Pb = vb ib = 0.5Vm Im cos(i )
+ 0.5Vm Im cos(2t + i + 2/3) (8)
Pc = vc ic = 0.5Vm Im cos(i )
+ 0.5Vm Im cos(2t + i 2/3). (9)
The energy balance in the capacitors for all three phases can
be written as (18). This three-phase energy can be expressed
in the stationary reference frame as (19). This dq-axis energy
variation can be compensated with the common-mode voltage.
These energy variations are fed to the proportionalintegral
(PI) controller. The outputs of the PI controller should be the
added power reference to compensate the energy variation as
(20). Using (17), the dq-axis power references are transformed
YOUSEFPOOR et al.: CONTROL OF HVDC TRANSMISSION SYSTEM UNDER DC FAULT OPERATING CONDITION 3685

Fig. 3. Detailed proposed control scheme of VSC-based HVDC transmission system. (a) Power flow controller. (b) Terminal dc-bus voltage
controller. (c) Phase voltage balancing controller. (d) Module voltage balancing controller. (e) Control scheme of dc/dc submodule.
3686 IEEE TRANSACTIONS ON INDUSTRIAL ELECTRONICS, VOL. 62, NO. 6, JUNE 2015

Fig. 4. Two-terminal HVDC transmission system with dc overhead line.

to the stationary common-mode voltage as (21). Fig. 3(c)

shows the phase voltage balancing controller in detail.

Vpb = Vcm cos(t + ) (10)

Pa = Pa + 0.5Vcm Im cos( i )
+ 0.5Vcm Im cos(2t + i + ) (11)
Pb = Pb + 0.5Vcm Im cos( i + 2/3
+ 0.5Vcm Im cos(2t + i + 2/3) (12)
Pc = Pc + 0.5Vcm Im cos( i 2/3)
+ 0.5Vcm Im cos(2t + i + + 2/3) (13)

Paavg = 0.5Vm Im cos(i )
+ 0.5Vcm Im cos( i ) (14)
 Fig. 5. Control algorithm of VSC-based HVDC transmission system
Pbavg = 0.5Vm Im cos(i )
under dc fault operating condition.
+ 0.5Vcm Im cos( i + 2/3) (15)

Pcavg = 0.5Vm Im cos(i ) IV. C ONTROL A LGORITHM OF VSC-B ASED HVDC
T RANSMISSION S YSTEM U NDER DC FAULT O PERATING
+ 0.5Vcm Im cos( i 2/3) (16) C ONDITION AND R ECOVERY A FTER DC FAULT
 
  
1
Pdavg cos( i )
= Vcm Im (17) Generally, the VSC-based HVDC transmission system is
Pqavg
2 sin( i )
vulnerable to dc side fault, but the VSC-based HVDC system
Eaavg Vaavg configuration considered in this paper has the feature to be
Ebavg = Cdc Vpavg Vbavg (18) protected against dc fault with the appropriate control algorithm
Ecavg Vcavg without using dc circuit breakers. In fact, this advantage allows

   1  Eaavg
us to use ac circuit breakers instead of dc circuit breakers for dc
Edavg 2 1 2
1

2 Ebavg fault protection.
= (19)
Eqavg 3 0 2
3
23 Ecavg The proposed control algorithm of the VSC-based HVDC
    transmission system for dc fault operation is shown in Fig. 5.
Pdpavg Kp + Ki s Edavg According to the control scheme for dc fault operation, dc fault
= (20)
Pqpavg s Eqavg is detected when the measured value of the dc side current is
cos (t + i ) Pdpavg

sin (t + i ) Pqpavg
twice the rated value of the dc side current. Once dc fault is
Vpb = . detected at time t0 , the reference value of active power flow
0.5Im
is changed to zero. Also, once fault is detected, all switches of
(21)
dc/dc converters are turned off. As a result, the total energy of
all dc capacitor voltages is discharged in the dc side inductor
D. Module Voltage Balancing Controller (L) and dc overhead line resistance (R) as can be shown in
Fig. 6. The inductor current has an initial value iL (t0 ) = I0 ,
Fig. 3(d) shows the module voltage balancing controller. The
and each capacitor voltage has an initial value Vcm (t0 ) = Vc0 .
module voltage balancing can be accomplished by dividing the
Therefore, the total initial value of capacitor voltage for all n
phase voltage references into the module voltage references [8],
[9] as can be seen in Fig. 3(d).
modules is V0 = n Vc0 . The dc side current can be expressed
as (22) if R < 2 L/C. The dc bus voltage is also written as (23)


t
E. Control Scheme of DC/DC Submodule idc (t) = I0 e cos 0 t
2 2

The control scheme of the dc/dc submodule is similar to the  



V0
control structure used in [12] shown in Fig. 3(e). As can be seen, + I0 02 2 et sin 02 2 t
the notch filter is used to remove the 120-Hz oscillation of the L
measured value of the dc/dc converter capacitor voltage. (22)
YOUSEFPOOR et al.: CONTROL OF HVDC TRANSMISSION SYSTEM UNDER DC FAULT OPERATING CONDITION 3687

Fig. 6. Equivalent circuit of VSC-based HVDC transmission system

when dc fault is detected (capacitor discharging mode).

Fig. 7. Equivalent circuit of VSC-based HVDC transmission system

when dc-bus voltage becomes zero (inductor discharging mode).


Fig. 8. Control algorithm of VSC-based HVDC transmission system for
t
Vc (t) = V0 e cos 02 2 t recovery after dc fault.

 


I0
+ V0 02 2 et sin 02 2 t
C
(23)

where = R/2L;0 = 1/ LC;C = Cm /n . The time when
the capacitor voltage becomes zero can be computed by
 
V C 2 2
arctan 0I0 V00C
t1 = t0 +  . (24)
02 2

When the dc-bus voltage becomes zero at time t1 , the total

energy of the dc side inductor is discharged in the dc overhead
line resistance and antiparallel diodes as can be shown in Fig. 7.
At time t1 , the inductor current has an initial value of iL (t1 ) =
I1 . Therefore, the dc side current can be written as
R L
idc (t) = I1 e L t ; T = .
R U NDER DC FAULT O PERATING C ONDITION
According to (25), the dc current is reduced, and the time
when the inductor current becomes zero is obtained by
5L
t2 = t1 + . (26)
R
When the magnitude of dc current becomes zero, circuit
breakers are opened to disconnect terminal 1 from terminal 2.
The control strategy for recovery after dc fault is shown in
Fig. 8. When dc fault is cleared, all switching signals of dc/dc
converters are enabled to charge dc/dc capacitor voltages. Once
the dc-bus voltage is regulated at its reference value, terminal 1
is connected to terminal 2, and the reference active power flow
is ramped up from zero to the rated value.
Fig. 9. VSC-based HVDC system under dc fault operating condition.
V. DYNAMIC P ERFORMANCE E VALUATION OF
VSC-B ASED HVDC T RANSMISSION S YSTEM
(25)
AND R ECOVERY A FTER DC FAULT
In this section, the dynamic performance of the VSC-based
HVDC transmission system under dc fault operating condition
is evaluated through PSCAD simulation. For dc fault simula-
tion, the positive dc line is connected into the ground as shown
in Fig. 9, and the system parameters are summarized in Table I.
DC fault happens at t = 0.9 s, and it is cleared at t = 1 s.
An overhead line with the length of 480 (km) is used in the
simulation.
Fig. 10 shows the dynamic performance of the VSC-based
HVDC system under dc fault operating condition. Initially, the
switching signals of ac/dc and dc/dc converters are off, and they
are enabled at t = 0.1 s. Therefore, the terminal dc-bus voltage
is adjusted at 320 kV at this time. The reference value of active
3688 IEEE TRANSACTIONS ON INDUSTRIAL ELECTRONICS, VOL. 62, NO. 6, JUNE 2015

TABLE I.
VSC-BASED HVDC S YSTEM PARAMETERS

Fig. 11. Terminal 1 ac/dc capacitor voltage variationPSCAD result.

Fig. 10. Dynamic performance of VSC-based HVDC system under dc

faultPSCAD result.

power is also ramped up from 0 at t = 0.4 s to 320 MW at

t = 0.7 s. DC fault happens at t = 0.9 s when the rated power
is transferred from terminal 1 to terminal 2 as shown in Fig. 10. Fig. 12. Terminal 2 ac/dc capacitor voltage variationPSCAD result.
When dc fault is detected, the reference value of active power
is reduced from 320 to 0 MW, and all the switching signals
of dc/dc converter switches will be turned off. As a result, the
total energy of all dc capacitor voltages is discharged in the dc
side inductor and dc overhead line resistance as explained in the
previous section. When dc-bus voltage becomes zero, the total
energy of the dc side inductor is discharged, and as a result, the
magnitude of the dc current is reduced as can be seen in Fig. 10.
When the magnitude of the dc current becomes zero, the circuit
breaker will be opened to disconnect terminal 1 from terminal 2.
Three-phase ac current in both terminals is also shown in
Fig. 10. DC fault is cleared at t = 1 s, and the control algorithm
for recovery after dc fault is implemented. First, the switching
signals of dc/dc converters are enabled at t = 1 s. At this time,
the dc-bus voltage is regulated at 320 kV. At t = 1.15 s, terminal
1 is connected to terminal 2. Then, the reference value of
active power is increased from zero at t = 1.2 s to 320 MW at
t = 1.5 s. Fig. 13. Terminal 1 dc/dc capacitor voltage variationPSCAD result.
During fault duration, the ac/dc converters are controlled
to regulate capacitor dc voltages of each ac/dc module at in Figs. 13 and 14, respectively. When dc fault is detected at
106.67 kV as shown in Figs. 11 and 12. Capacitor dc-bus volt- t = 0.9 s, the switching signals of dc/dc converters are disabled.
ages of dc/dc converters for terminals 1 and 2 are also shown Therefore, the capacitor voltages of dc/dc converters become
YOUSEFPOOR et al.: CONTROL OF HVDC TRANSMISSION SYSTEM UNDER DC FAULT OPERATING CONDITION 3689

Fig. 16. Zero crossing time with respect to fault location and
Ldc PSCAD simulation results.

Fig. 14. Terminal 2 dc/dc capacitor voltage variationPSCAD result.

Fig. 17. RTDS setup.

Fig. 15. Zero crossing time with respect to fault location and
Ldc theoretical results.

zero. When dc fault is cleared at t = 1 s, the switching signals

of dc/dc converters are enabled, and the capacitor voltages of
dc/dc converters are regulated at 106.67 kV again.
Fig. 15 shows the zero crossing time of dc current versus
fault location and dc side inductor based on the theoretical
results obtained by (26). As can be seen, dc current zero
crossing time increases as dc side inductor increases. Also, as
the fault location increases, the R value increases, and as a
result, zero crossing time decreases. Fig. 16 also shows the zero
crossing time of dc current versus fault location and dc side
inductor based on the obtained simulation results. Comparison
of simulation and theoretical results shows that (26) is accurate
enough to find the zero crossing time of dc current.

Fig. 18. Dynamic performance of VSC-based HVDC systemRTDS

VI. R EAL -T IME D IGITAL S IMULATION O F VSC-B ASED
HVDC S YSTEM U NDER DC FAULT
O PERATING C ONDITION
This section presents the dynamic performance of the VSC-
based HVDC transmission system through RTDS simulation.
The hardware-in-the-loop implementation of the VSC-based
HVDC transmission system is performed by RTDS, shown in
Fig. 17, and the system parameters are the same as the param-
result.
eters tabulated in Table I. The VSC-based HVDC transmission
system is simulated by the RTDS. The Concerto control board
is used as the main controller.
Fig. 18 shows the RTDS results for dc fault operating con-
dition. At t = 13 s, the reference value of active power is
changed to 320 MW. DC fault happens at t = 30 s. When
dc fault is detected, the reference value of active power is
3690
Fig. 19. Terminal 1 dc/dc capacitor voltage variationRTDS result.
Fig. 20. Terminal 2 dc/dc capacitor voltage variationRTDS result.
reduced to zero, and all the switching signals of dc/dc converter
switches will be turned off. As a result, the total energy of
all dc capacitor voltages is discharged. When dc-bus voltage
becomes zero, the magnitude of dc current is reduced. When
the magnitude of dc current becomes zero, the circuit breaker
will be opened to disconnect terminal 1 from terminal 2. Three-
phase ac current in both terminals is also shown in Fig. 18.
DC fault is cleared at t = 33 s, and the control algorithm for
recovery after dc fault is implemented. First, the switching
signals of dc/dc converters are enabled at t = 33 s. At this time,
dc-bus voltage is regulated at 320 kV. At t = 38 s, terminal 1
is connected to terminal 2. Then, the reference value of active
power is increased to 320 MW at t = 40 s.
Capacitor dc-bus voltages of dc/dc converters for terminals 1
and 2 are shown in Figs. 19 and 20, respectively. When dc
fault is detected at t = 30 s, the switching signals of dc/dc
converters are disabled. Therefore, the capacitor voltages of
dc/dc converters become zero. When dc fault is cleared at
t = 33 s, the switching signals of dc/dc converters are enabled,
and the capacitor voltages of dc/dc converters are regulated at
106.67 kV.
IEEE TRANSACTIONS ON INDUSTRIAL ELECTRONICS, VOL. 62, NO. 6, JUNE 2015
VII. C ONCLUSION
This paper has proposed a control method of a dc fault-
resilient converter which can be protected against dc fault
without using expensive dc circuit breakers. In this paper, an ap-
propriate control structure with the capacitor voltage balancing
controller was proposed. The proposed control scheme consists
of four layers to control the power flow and terminal dc-bus
voltage as well as the dc capacitor voltages of each module.
The control algorithm for dc fault operation and recovery
after dc fault was proposed. The performance of the converter
was thoroughly analyzed under dc fault operating condition,
and PSCAD simulation results were presented to validate the
control structures. The feasibility of the VSC-based HVDC
transmission system operation via controller hardware-in-the-
loop simulation with RTDS was demonstrated, and RTDS
simulation results verified the controller performance under dc
fault operating conditions.
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Authors photographies and biographies not available at the time of
publication.