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INTRODUCTION

Modulation is very important technique in communication system to transfer the data, without loss
through the channel and to reduce size of antenna in case of wireless communication. Wireless
communication is one of the most vibrant areas in communication field today. This is due to the increase
in communication connectivity driven mainly in cellular telephony and wireless data applications.
Wireless communication systems require high data rate for efficient transmission of information [8].

Modulation techniques are introduced to increase the efficiency in data transmitting and receiving rate
within the same bandwidth. The most common modulation method is used in communication system is
Quadrature Phase Shift Keying (QPSK), which is one of the form of Phase Shift Keying (PSK)
modulation scheme. The digital methodology was chosen because the advantages of digital solution are
apparent. The main advantages of the digital solution are repeatability, cost and the simpler
reconfiguration compared to analog solutions. In PSK modulation, the phase changes according to the
baseband data while the frequency and amplitude remains unchanged [7].

OBJECTIVE

Design of QPSK modulator in VHDL


Simulation of design
Determination of area, power, timing results of QPSK modulator design

BLOCK DIAGRAM

HARDWARE AND SOFTWARE TOOLS AND COMPONENTS

The hardware used was Nexys 4 FPGA kit with onboard ADC. The software used was Vivado.
WORKING THEORY

In QPSK modulation, the carrier phase acquires four discrete states that are used to represent a group of
two input data bits as shown in Table 1. Each group takes one form of QPSK states i.e. 45 and 135.

Where the first bit represents In-phase(I) and the second bit represent the Quadrature-phase(Q). QPSK
modulation is a pair of binary PSK [BPSK], but the data transmission in QPSK is twice when compared
to BPSK. The Bit Error Rate (BER) over Signal-to- Noise ratio (SNR) for both the modulation schemes
are same[8]. The two BPSK waves are added to produce the desired QPSK wave. Since two bit
information is transmitted in an interval T, the symbol period for QPSK is two times the bit period i.e.
T=2Tb, while for BPSK the symbol period is same as bit period T=Tb[7][8]. The QPSK signal requires
half the bandwidth of the corresponding BPSK wave which consumes low throughput with complexity
in hardware implementation. Hence to generate high throughput QPSK modulator and to verify above
statement hardware implementation is needed.

CODE

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
-- entity declaration
entity qpsk_mod_n is
Port(
clk : in std_logic; -- global clock
valid_in : in std_logic; -- when high din is valid
data_in : in std_logic_vector(1 downto 0); -- data in
reset : in std_logic; -- asynchronous active high reset
valid_out : out std_logic; -- when high real and imag is valid
dout_real, dout_imag : out std_logic_vector(15 downto 0) -- real and
imag out
);
end qpsk_mod_n;
-- architecture declaration
architecture Behavioral of qpsk_mod_n is
signal sig_valid_out : std_logic;
signal valid_out1 : std_logic;
signal sig_valid_out1 : std_logic;
begin
-- process to map QPSK costellation
process(clk, reset)
begin
if(reset = '1') then
dout_real <= x"0000";
dout_imag <= x"0000";
valid_out1 <= '0';
sig_valid_out <= '0';
sig_valid_out1 <= '0';
elsif(clk = '1' and clk'event) then
valid_out1 <= '1';
sig_valid_out <= valid_out1;
sig_valid_out1 <= sig_valid_out;
if valid_in = '1' then
case data_in is
when "00" => dout_imag <= x"2d41";
dout_real <= x"2d41";
valid_out1 <= '1'; -- Based on the input data assign
when "01" => dout_imag <= x"D2BF"; -- values to the output ports
dout_real <= x"2d41";
valid_out1 <= '1';
when "10" => dout_imag <= x"2d41";
dout_real <= x"D2BF";
valid_out1 <= '1';
when "11" => dout_imag <= x"D2BF";
dout_real <= x"D2BF";
valid_out1 <= '1';
when others => dout_imag <= x"D2BF";
dout_real <= x"D2BF";
valid_out1 <= '1';
end case;
else
dout_imag <= x"0000";
dout_real <= x"0000";
valid_out1 <= '0';
end if;
end if;
end process;
valid_out <= valid_out1;

end Behavioral;

TESTBENCH

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
-- entity declaration

entity qpsk_mod_n_test is
end qpsk_mod_n_test;

architecture test of qpsk_mod_n_test is


signal clk, valid_in, reset, valid_out: std_logic := '0';
signal data_in: std_logic_vector(1 downto 0) := (others => '0');
signal dout_real, dout_imag: std_logic_vector(15 downto 0) :=
(others => '0');

component qpsk_mod_n
Port(
clk : in std_logic; -- global clock
valid_in : in std_logic; -- when high din is valid
data_in : in std_logic_vector(1 downto 0); -- data in
reset : in std_logic; -- asynchronous active high reset
valid_out : out std_logic; -- when high real and imag is valid
dout_real, dout_imag : out std_logic_vector(15 downto 0) -- real and
imag out
);
end component;

begin

UUT: qpsk_mod_n port map (clk, valid_in, data_in, reset, valid_out,


dout_real, dout_imag);
reset <= '1', '0' after 30 ns;

process begin
for i in 0 to 3 loop
valid_in <= '1';
data_in <= conv_std_logic_vector(i, 2);
wait for 40 ns;
end loop;
end process;
process
begin
clk <= '1';
wait for 10 ns;
clk <= '0';
wait for 10 ns;
end process;

end test;

CONSTRAINT FILE

create_clock period 10.000 name sysClk waveform {0.000 5.000} [get_ports {sysClk}]
set_property IOSTANDARD LVCMOS33 [get_ports led]
set_property IOSTANDARD LVCMOS25 [get_ports switch]
set_property PACKAGE_PIN T22 [get_ports led]
set_property PACKAGE_PIN F22 [get_ports switch]

SIMULATION
POWER

UTILISATION
TIMING

CONCLUSION

QPSK Modulator has been designed in VHDL. The simulation is performed using VIVADO. The design
is implemented on Nexys 4 FPGA. Area, power, and timing results are obtained.
FUTURE WORK

Different architectures for digital mixers can be explored to improve the design of the QPSK modulator.

REFERENCES

[1] Xilinx, Nexys 4 FPGA starter kit Board User Guide, Internet: http://
www.xilinx.com/support/documentation/boards_and_kits/ug230.pdf/, 20 Jan, 2016

[2] Simon Haykin Communication Sytems, Fourth Edition, John Wiley, 2008.

[3] Samir Palnitkar, Verilog HDL: A Guide to Digital Design and Synthesis, 2nd
Edition, Prentice Hall, 2003.

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