Finite State Machine Design

Dr DC Hendry

March 9, 2006

1 State Diagrams

The first stage in the design of a finite state machine is to specify the machine.
This requires that all control inputs and outputs are identified, that all states
needed are listed, and that the state transitions are tabulated. A graphical
approach may be used at this stage for simpler FSMs.

State diagrams provide a graphical approach to the design of an FSM, both

Moore and Mealy. The basic element of a state diagram is the state bubble. For
a Moore machine the state bubble takes the form:

Reset
00

1. Each state is identified by a unique name within the state bubble - in this
case Reset.
2. The output bits, in this case there are assumed to be two output bits, are
then given below the state name (usually separated by a horizontal line).
3. Since we are assuming a Moore machine, the outputs are entirely deter-
mined by the current state.

In addition to state bubbles, transition arcs are used to denote the next state
of each current state. Since the next state depends upon the current state and
the inputs, this can be denoted with an arc from the current state to the next
state labelled with the inputs causing this transition.

Consider the modulo 4 up/down counter of the previous lecture:

 FSM Design

1
1 00 1

0
4 0 2
11 01
0 0

1 3 1
10

1. Each transition is labelled with the value of the input signal up/down that
causes that transition to be taken.
2. With multiple input signals, each transition will be labelled with a number
of bits.
3. All possible values of the input signals should appear on the arcs leaving
a state.
01,10
A B
4. One arc may be labelled with multiple input values.
5. An arc may leave and return to the same state.
6. The dont care symbol - may be used.

Assume the machine has two inputs, r and s, and a single output z:

0-

a
-- 1-
0
10
d 00 0- b
1 0

01,10 11
c
0

11

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Giving the unassigned state table as:

Curr. rs z
State 00 01 11 10
a a a b b 0
b a a c b 0
c a d c d 0
d a a a a 1

2 State Assignment Problem

The next stage in the design process is to convert the unassigned state table
(whether derived from a state diagram or otherwise) into an assigned state table.
In effect we need to replace names such as a, b, c and d with binary codes (the
state codes. The first decision is to determine the number of bits needed in the
binary codes. If we have n bits available then there are 2n distinct bit patterns,
so for a state table with m states, we need dlog2 (m)e bits (where de is the ceiling
operator, and returns the integer greater than or equal to its argument).

Having determined the number of bits required to represent each state, we can
then choose bit patterns for each state. Any choice of unique bit pattern for
each state will give a working design, but, different choices of state assignment
give rise to more or less costly implementations of the next state and output
logic.

Since there are a very large number of permutations of even designs with a
small number of bits in the state codes, trying to exhaustively find the mini-
mum is impossible, even with computer programs. A number of heuristics have
therefore been developed for this problem. Historically, we would now study
such heuristics with a view to finding a manual solution to the state assignment
problem. Since this course is biased towards VHDL based solutions, we will not
study these heuristics, rather, we will rely on the logic synthesis tool to do the
work for us.

For the design above, here is a sample state assignment. Since we have only
four states, two bits are needed for each state code. So a possible coding is:

State Code
a 00
b 01
c 11
d 10

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3 Example Design

With the above state assignment, we can now construct the assigned state table
for the design. That table is then:

Current rs z
State 00 01 11 10
Q1 Q0 D1 D0 D1 D0 D1 D0 D1 D0
00 00 00 01 01 0
01 00 00 11 01 0
11 00 10 11 10 0
10 00 00 00 00 1

From this table K-Maps may be derived for D1 , D0 and for the output signal z.
Note that the equation for z is rather simpler, since, as this is a Moore machine,
there is no dependency on the input signals. Clearly in fact z = Q1 Q0 . The
K-Maps for D1 and D0 are then:

D1 Q1 Q0 D0 Q1 Q0
00 01 11 10 00 01 11 10
00 0 0 0 0 00 0 0 0 0

01 0 0 1 0 01 0 0 0 0
rs   rs   
11 0

1 1 0

11 1

1 1 0
10 0 0 1 0

1 1 
10  0 0
D1 = Q1 Q0 s + Q0 rs + Q1 Q0 r D0 = Q1 r + Q0 rs

4 Sequence Detectors

As a further example of a Moore machine we will design a sequence detector,

such circuits detect the presence of a pre-defined pattern of 1s and 0s on the
input line. They are primarily of value as pedagogic examples. In this example
we shall look for a machine which detects the sequence 1011 on the input line,
and for one clock cycle after the last 1, raises an output line to 1. Also
assume that instances of 1011 may not overlap. The resulting state diagram
for a Moore machine is as follows:

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Start
0

0 1

1011 1xxx
1
1 1 0
0
1 0

101x 1 10xx
0 0
0

From the state diagram the unassigned state table may then be derived (the
input signal is called a, and the output x):

Current Next State x

State a=0 a=1
Start Start 1xxx 0
1xxx 10xx 1xxx 0
10xx Start 101x 0
101x 10xx 1011 0
1011 Start 1xxx 1

The unassigned state table may be converted to an assigned state table given a
state assignment. So with the state assignment:

State Code
Start 000
1xxx 001
10xx 011
101x 010
1011 100

Giving an assigned state table of:

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Current Next State x

State a=0 a=1
000 000 001 0
001 011 001 0
011 000 010 0
010 011 100 0
100 000 001 1

From which Boolean equations for D2 , D1 and D0 may be derived.

5 Mealy Machines

In a Mealy machine the next state, as in a Moore machine, is determined by the

current state and the control inputs. Unlike the Moore machine, the outputs of
the machine are determined by both the current state and the control inputs.
The state bubble for a Mealy machine does not in itself determine the output
of the machine, and so for a Mealy machine state bubble only the name of the
state is included within the state bubble. Since each transition arc starts from
a state bubble, and is labeled with the control inputs causing that arc to be
followed, it is useful to display the output values on the transition arc, as in the
following example:

00/10
A B

This transition arc indicates that when in current state A, and the control inputs
are 00, then the arc should be followed and the outputs set to 10.

The state table for a Mealy machine also needs to show the dependence of
output values on the inputs. For small machines this can be shown in the
following manner:

Current Next State Output Z

State a=0 a=1 a=0 a=1
A A B 0 0
B C D 0 1
C C D 1 1
D A C 1 0

To complete the logic design of the above machine we first need a state assign-
ment. As for the Moore machine this is a difficult task if the global minimum

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is required, but again, any unique state assignment will work. We shall use the
following state assignment:

State Assignment
A 00
B 01
C 11
D 10

This gives an assigned state table of:

Current Next State Output Z

State a=0 a=1 a=0 a=1
Q1 Q0 D1 D0 D1 D0
00 00 01 0 0
01 11 10 0 1
11 11 10 1 1
10 00 11 1 0

From the next state portion of the assigned state table the equations for D1 and
D0 may be derived, using D1 as an example:

D1 Q1 Q0
00 01 11 10

0 0 1 1 0
a  
1 0 1

1  1

D1 = Q0 + Q1 a

The output of the machine is the signal Z. The assigned state table again
provides the necessary information for the construction of a K-Map.

Z Q1 Q0
00 01 11 10
 
0 0 0
1 1
a  
1 0
1 1 0

Z = Q1 a + Q0 a

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