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TOPSwitch-JX
™
Family
Integrated Off-Line Switcher with EcoSmart™ Technology
for Highly Efficient Power Supplies
Product Highlights
+
EcoSmart – Energy Efficient
• Ideal for applications from 10 W to 245 W -
• Energy efficient over entire load range
• No-load consumption below 100 mW at 265 VAC
• Up to 750 mW standby output power for 1 W input at 230 VAC
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Rev. E 08/12 www.powerint.com
TOP264-271
0 DRAIN (D)
VC
CONTROL (C) INTERNAL
ZC 1 SUPPLY
-
SHUNT REGULATOR/ +
ERROR AMPLIFIER +
SOFT START
5.8 V
4.8 V -
-
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www.powerint.com Rev. E 08/12
TOP264-271
PI-5579-111210
+ VUV = IUV × RLS + VV (IV = IUV) Auto-Restart
VOV = IOV × RLS + VV (IV = IOV)
78
For RLS = 4 MΩ
RLS 4 MΩ Slope = PWM Gain
100
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TOP264-271
hysteretic output overvoltage protection (OVP). The pin can MOSFET off and puts the control circuitry in a low current
also be used as a remote-ON/OFF using the IUV threshold. standby mode. The high-voltage current source turns on and
charges the external capacitance again. A hysteretic internal
The EXTERNAL CURRENT LIMIT (X) pin can be used to reduce supply undervoltage comparator keeps VC within a window of
the current limit externally to a value close to the operating peak typically 4.8 V to 5.8 V by turning the high-voltage current
current, by connecting the pin to SOURCE through a resistor. source on and off as shown in Figure 8. The auto-restart circuit
This pin can also be used as a remote-ON/OFF input. has a divide-by-sixteen counter, which prevents the output
MOSFET from turning on again until sixteen discharge/charge
The FREQUENCY (F) pin sets the switching frequency in the full cycles have elapsed. This is accomplished by enabling the
frequency PWM mode to the default value of 132 kHz when output MOSFET only when the divide-by-sixteen counter
connected to SOURCE pin. A half frequency option of 66 kHz reaches the full count (S15). The counter effectively limits
can be chosen by connecting this pin to the CONTROL pin TOP264-271 power dissipation by reducing the auto-restart
instead. Leaving this pin open is not recommended. duty cycle to typically 2%. Auto-restart mode continues until
output voltage regulation is again achieved through closure of
CONTROL (C) Pin Operation the feedback loop.
The CONTROL pin is a low impedance node that is capable of
receiving a combined supply and feedback current. During Oscillator and Switching Frequency
normal operation, a shunt regulator is used to separate the The internal oscillator linearly charges and discharges an
feedback signal from the supply current. CONTROL pin voltage internal capacitance between two voltage levels to create a
VC is the supply voltage for the control circuitry including the triangular waveform for the timing of the pulse width modulator.
MOSFET gate driver. An external bypass capacitor closely This oscillator sets the pulse width modulator/current limit latch
connected between the CONTROL and SOURCE pins is at the beginning of each cycle.
required to supply the instantaneous gate drive current. The
total amount of capacitance connected to this pin also sets the The nominal full switching frequency of 132 kHz was chosen to
auto-restart timing as well as control loop compensation. minimize transformer size while keeping the fundamental EMI
When rectified DC high-voltage is applied to the DRAIN pin frequency below 150 kHz. The FREQUENCY pin, when shorted
during start-up, the MOSFET is initially off, and the CONTROL to the CONTROL pin, lowers the full switching frequency to
pin capacitor is charged through a switched high-voltage 66 kHz (half frequency), which may be preferable in some cases
current source connected internally between the DRAIN and such as noise sensitive video applications or a high efficiency
CONTROL pins. When the CONTROL pin voltage VC reaches standby mode. Otherwise, the FREQUENCY pin should be
approximately 5.8 V, the control circuitry is activated and the connected to the SOURCE pin for the default 132 kHz.
soft-start begins. The soft-start circuit gradually increases the
drain peak current and switching frequency from a low starting To further reduce the EMI level, the switching frequency in the
value to the maximum drain peak current at the full frequency full frequency PWM mode is jittered (frequency modulated) by
over approximately 17 ms. If no external feedback/supply approximately ±2.5 kHz for 66 kHz operation or ±5 kHz for
current is fed into the CONTROL pin by the end of the soft-start, 132 kHz operation at a 250 Hz (typical) rate as shown in Figure 7.
the high-voltage current source is turned off and the CONTROL The jitter is turned off gradually as the system is entering the
pin will start discharging in response to the supply current variable frequency mode with a fixed peak drain current.
drawn by the control circuitry. If the power supply is designed
properly, and no fault condition such as open-loop or shorted Pulse Width Modulator
output exists, the feedback loop will close, providing external The pulse width modulator implements multi-mode control by
CONTROL pin current, before the CONTROL pin voltage has driving the output MOSFET with a duty cycle inversely
had a chance to discharge to the lower threshold voltage of proportional to the current into the CONTROL pin that is in
approximately 4.8 V (internal supply undervoltage lockout excess of the internal supply current of the chip (see Figure 6).
threshold). When the externally fed current charges the CONTROL The feedback error signal, in the form of the excess current, is
pin to the shunt regulator voltage of 5.8 V, current in excess of filtered by an RC network with a typical corner frequency of
the consumption of the chip is shunted to SOURCE through an 7 kHz to reduce the effect of switching noise in the chip supply
NMOS current mirror as shown in Figure 3. The output current current generated by the MOSFET gate driver.
of that NMOS current mirror controls the duty cycle of the
power MOSFET to provide closed loop regulation. The shunt To optimize power supply efficiency, four different control
regulator has a finite low output impedance ZC that sets the gain modes are implemented. At maximum load, the modulator
of the error amplifier when used in a primary feedback operates in full frequency PWM mode; as load decreases, the
configuration. The dynamic impedance ZC of the CONTROL pin modulator automatically transitions, first to variable frequency
together with the external CONTROL pin capacitance sets the PWM mode, then to low frequency PWM mode. At light load,
dominant pole for the control loop. the control operation switches from PWM control to multi-cycle-
modulation control, and the modulator operates in multi-cycle-
When a fault condition such as an open-loop or shorted output modulation mode. Although different modes operate differently
prevents the flow of an external current into the CONTROL pin, to make transitions between modes smooth, the simple
the capacitor on the CONTROL pin discharges towards 4.8 V. relationship between duty cycle and excess CONTROL pin
At 4.8 V, auto-restart is activated, which turns the output current shown in Figure 6 is maintained through all three PWM
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TOP264-271
PI-4530-041107
fOSC + The maximum duty cycle, DCMAX, is set at a default maximum
Switching value of 78% (typical). However, by connecting the VOLTAGE-
Frequency MONITOR to the rectified DC high-voltage bus through a resistor
fOSC -
with appropriate value (4 MW typical), the maximum duty cycle
can be made to decrease from 78% to 40% (typical) when input
4 ms line voltage increases from 88 V to 380 V, with dual gain slopes.
Error Amplifier
VDRAIN The shunt regulator can also perform the function of an error
amplifier in primary-side feedback applications. The shunt
Time regulator voltage is accurately derived from a temperature-
compensated bandgap reference. The CONTROL pin dynamic
Figure 7. Switching Frequency Jitter (Idealized VDRAIN Waveforms). impedance ZC sets the gain of the error amplifier. The CONTROL
pin clamps external circuit signals to the VC voltage level. The
modes. Please see the following sections for the details of the CONTROL pin current in excess of the supply current is
operation of each mode and the transitions between modes. separated by the shunt regulator and becomes the feedback
current IFB for the pulse width modulator.
Full Frequency PWM mode: The PWM modulator enters full
frequency PWM mode when the CONTROL pin current (IC) On-Chip Current Limit with External Programmability
reaches IB. In this mode, the average switching frequency is The cycle-by-cycle peak drain current limit circuit uses the
kept constant at fOSC (pin selectable 132 kHz or 66 kHz). Duty output MOSFET ON-resistance as a sense resistor. A current
cycle is reduced from DCMAX through the reduction of the on-time limit comparator compares the output MOSFET ON-state drain
when IC is increased beyond IB. This operation is identical to the to source voltage VDS(ON) with a threshold voltage. High drain
PWM control of all other TOPSwitch families. TOP264-271 only current causes VDS(ON) to exceed the threshold voltage and turns
operates in this mode if the cycle-by-cycle peak drain current the output MOSFET off until the start of the next clock cycle.
stays above kPS(UPPER) × ILIMIT(set), where kPS(UPPER) is 55% (typical) The current limit comparator threshold voltage is temperature
and ILIMIT(set) is the current limit externally set via the EXTERNAL compensated to minimize the variation of the current limit due
CURRENT LIMIT (X) pin. to temperature related changes in RDS(ON) of the output MOSFET.
The default current limit of TOP264-271 is preset internally.
Variable Frequency PWM mode: When peak drain current is However, with a resistor connected between EXTERNAL
lowered to kPS(UPPER) × ILIMIT(set) as a result of power supply load CURRENT LIMIT (X) pin and SOURCE pin, current limit can be
reduction, the PWM modulator initiates the transition to variable programmed externally to a lower level between 30% and 100%
frequency PWM mode, and gradually turns off frequency jitter. of the default current limit. By setting current limit low, a larger
In this mode, peak drain current is held constant at kPS(UPPER) × TOP264-271 than necessary for the power required can be used
ILIMIT(set) while switching frequency drops from the initial full to take advantage of the lower RDS(ON) for higher efficiency/
frequency of fOSC (132 kHz or 66 kHz) towards the minimum smaller heat sinking requirements. With a second resistor
frequency of fMCM(MIN) (30 kHz typical). Duty cycle reduction is connected between the EXTERNAL CURRENT LIMIT (X) pin
accomplished by extending the off-time. and the rectified DC high-voltage bus, the current limit is
reduced with increasing line voltage, allowing a true power
Low Frequency PWM mode: When switching frequency limiting operation against line variation to be implemented. When
reaches fMCM(MIN) (30 kHz typical), the PWM modulator starts to using an RCD clamp, this power limiting technique reduces
transition to low frequency mode. In this mode, switching maximum clamp voltage at high-line. This allows for higher
frequency is held constant at fMCM(MIN) and duty cycle is reduced, reflected voltage designs as well as reducing clamp dissipation.
similar to the full frequency PWM mode, through the reduction
of the on-time. Peak drain current decreases from the initial The leading edge blanking circuit inhibits the current limit
value of kPS(UPPER) × ILIMIT(set) towards the minimum value of comparator for a short time after the output MOSFET is turned
kPS(LOWER) × ILIMIT(set), where kPS(LOWER) is 25% (typical) and ILIMIT(set) on. The leading edge blanking time has been set so that, if a
is the current limit externally set via the X pin. power supply is designed properly, current spikes caused by
primary-side capacitances and secondary-side rectifier reverse
Multi-Cycle-Modulation mode: When peak drain current is recovery time should not cause premature termination of the
lowered to kPS(LOWER) × ILIMIT(set), the modulator transitions to switching pulse. The current limit is lower for a short period
multi-cycle-modulation mode. In this mode, at each turn-on, after the leading edge blanking time. This is due to dynamic
the modulator enables output switching for a period of TMCM(MIN) characteristics of the MOSFET. During start-up and fault
at the switching frequency of fMCM(MIN) (4 or 5 consecutive pulses conditions the controller prevents excessive drain currents by
at 30 kHz) with the peak drain current of kPS(LOWER) × ILIMIT(set), reducing the switching frequency.
and stays off until the CONTROL pin current falls below IC(OFF).
This mode of operation not only keeps peak drain current low Line Undervoltage Detection (UV)
but also minimizes harmonic frequencies between 6 kHz and At power-up, UV keeps TOP264-271 off until the input line
30 kHz. By avoiding transformer resonant frequency this way, voltage reaches the undervoltage threshold. At power-down,
all potential transformer audible noises are greatly suppressed.
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TOP264-271
~
~
~
~
VUV
~
~
~
~
~
~
VLINE
0V
S15 S14 S13 S12 S0 S15 S14 S13 S12 S0 S15 S14 S13 S12 S0 S15 S15 5.8 V
~
~
~
~
~
~
VC 4.8 V
0V
~
~
~
~
VDRAIN
~
~
0V
VOUT
0V
~
~
~
~
~
~
1 2 3 2 4
Note: S0 through S15 are the output states of the auto-restart counter PI-4531-121206
Figure 8. Typical Waveforms for (1) Power-Up (2) Normal Operation (3) Auto-Restart (4) Power-Down.
UV prevents auto-restart attempts after the output goes out of In order to reduce the no-load input power of TOP264-271
regulation. This eliminates power-down glitches caused by designs, the V pin operates at very low currents. This requires
slow discharge of the large input storage capacitor present in careful layout considerations when designing the PCB to avoid
applications such as standby supplies. A single resistor noise coupling. Traces and components connected to the V pin
connected from the VOLTAGE-MONITOR pin to the rectified DC should not be adjacent to any traces carrying switching currents.
high-voltage bus sets UV threshold during power-up. Once the These include the drain, clamp network, bias winding return or
power supply is successfully turned on, the UV threshold is power traces from other converters. If the line sensing features
lowered to 44% of the initial UV threshold to allow extended are used, then the sense resistors must be placed within 10 mm
input voltage operating range (UV low threshold). If the UV low of the V pin to minimize the V pin node area. The DC bus
threshold is reached during operation without the power supply should then be routed to the line-sense resistors. Note that
losing regulation, the device will turn off and stay off until UV external capacitance must not be connected to the V pin as this
(high threshold) has been reached again. If the power supply may cause misoperation of the V pin related functions.
loses regulation before reaching the UV low threshold, the
device will enter auto-restart. At the end of each auto-restart Hysteretic or Latching Output Overvoltage Protection (OVP)
cycle (S15), the UV comparator is enabled. If the UV high The detection of the hysteretic or latching output overvoltage
threshold is not exceeded, the MOSFET will be disabled during protection (OVP) is through the trigger of the line overvoltage
the next cycle (see Figure 8). The UV feature can be disabled threshold. The V pin voltage will drop by 0.5 V, and the
independent of the OV feature. controller measures the external attached impedance immediately
after this voltage drops. If IV exceeds IOV(LS) (336 mA typical)
Line Overvoltage Shutdown (OV) longer than 100 ms, TOP264-271 will latch into a permanent
The same resistor used for UV also sets an overvoltage off-state for the latching OVP. It only can be reset if IX exceeds
threshold, which, once exceeded, will force TOP264-271 to IX(TH) = -27 mA (typ) or VC goes below the power-up reset
stop switching instantaneously (after completion of the current threshold (VC(RESET)) and then back to normal. If IV does not
switching cycle). If this condition lasts for at least 100 ms, the exceed IOV(LS) or exceeds no longer than 100 ms, TOP264-271
TOP264-271 output will be forced into off state. When the line will initiate the line overvoltage and the hysteretic OVP. Their
voltage is back to normal with a small amount of hysteresis behavior will be identical to the line overvoltage shutdown (OV)
provided on the OV threshold to prevent noise triggering, the that has been described in detail in the previous section.
state machine sets to S13 and forces TOP264-271 to go During a fault condition resulting from loss of feedback, output
through the entire auto-restart sequence before attempting to voltage will rapidly rise above the nominal voltage. The increase
switch again. The ratio of OV and UV thresholds is preset at in output voltage will also result in an increase in the voltage at
4.5, as can be seen in Figure 9. When the MOSFET is off, the the output of the bias winding. A voltage at the output of the
rectified DC high-voltage surge capability is increased to the bias winding that exceeds of the sum of the voltage rating of the
voltage rating of the MOSFET (725 V), due to the absence of the Zener diode connected from the bias winding output to the V
reflected voltage and leakage spikes on the drain. The OV pin and V pin voltage, will cause a current in excess of IV to be
feature can be disabled independent of the UV feature. injected into the V pin, which will trigger the OVP feature.
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TOP264-271
If the power supply is operating under heavy load or low input Remote-ON/OFF
line conditions when an open-loop occurs, the output voltage TOP264-271 can be turned on or off by controlling the current into
may not rise significantly. Under these conditions, a latching the VOLTAGE-MONITOR pin or out from the EXTERNAL CURRENT
shutdown will not occur until load or line conditions change. LIMIT pin. In addition, the VOLTAGE-MONITOR pin has a 1 V
Nevertheless, the operation provides the desired protection by threshold comparator connected at its input. This voltage
preventing significant rise in the output voltage when the line or threshold can also be used to perform remote-ON/OFF control.
load conditions do change. Primary-side OVP protection with
the TOP264-271 in a typical application will prevent a nominal When a signal is received at the VOLTAGE-MONITOR pin or the
12 V output from rising above approximately 20 V under open- EXTERNAL CURRENT LIMIT pin to disable the output through
loop conditions. If greater accuracy is required, a secondary any of the pin functions such as OV, UV and remote-ON/OFF,
sensed OVP circuit is recommended. TOP264-271 always completes its current switching cycle before
the output is forced off.
Line Feed-Forward with DCMAX Reduction
The same resistor used for UV and OV also implements line voltage As seen above, the remote-ON/OFF feature can also be used
feed-forward, which minimizes output line ripple and reduces as a standby or power switch to turn off the TOP264-271 and
power supply output sensitivity to line transients. Note that for the keep it in a very low power consumption state for indefinitely long
same CONTROL pin current, higher line voltage results in smaller periods. If the TOP264-271 is held in remote-off state for long
operating duty cycle. As an added feature, the maximum duty enough time to allow the CONTROL pin to discharge to the
cycle DCMAX is also reduced from 78% (typical) at a voltage slightly internal supply undervoltage threshold of 4.8 V (approximately
lower than the UV threshold to 36% (typical) at the OV threshold. 32 ms for a 47 µF CONTROL pin capacitance), the CONTROL
DCMAX of 36% at high-line was chosen to ensure that the power pin goes into the hysteretic mode of regulation. In this mode,
capability of the TOP264-271 is not restricted by this feature under the CONTROL pin goes through alternate charge and discharge
normal operation. TOP264-271 provides a better fit to the ideal cycles between 4.8 V and 5.8 V (see CONTROL pin operation
feed-forward by using two reduction slopes: -1% per mA for all bus section above) and runs entirely off the high-voltage DC input,
voltage less than 195 V (typical for 4 MW line impedance) and but with very low power consumption (<100 mW typical at
-0.25% per mA for all bus voltage more than 195 V. 230 VAC with X pin open). When the TOP264-271 is remotely
Table 2. VOLTAGE MONITOR (V) Pin and EXTERNAL CURRENT LIMIT (X) Pin Configuration Options.
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Rev. E 08/12 www.powerint.com
TOP264-271
X Pin V Pin
Current
Limit
DCMAX (78%)
Maximum
Duty Cycle
VBG
Pin Voltage
I
-250 -200 -150 -100 -50 0 25 50 75 100 125 336
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TOP264-271
the clamp circuit and the output rectifier during start-up. This mode, and a 4.8 V to 5.8 V (typical) triangular waveform is
feature also helps minimize output overshoot and prevents present on the CONTROL pin while in thermal shutdown.
saturation of the transformer during start-up.
Bandgap Reference
Shutdown/Auto-Restart (for OCP, SCP, OPP) All critical TOP264-271 internal voltages are derived from a
To minimize TOP264-271 power dissipation under fault temperature-compensated bandgap reference. This voltage
conditions such as over current (OC), short-circuit (SC) or over reference is used to generate all other internal current references,
power (OP), the shutdown/auto-restart circuit turns the power which are trimmed to accurately set the switching frequency,
supply on and off at an auto-restart duty cycle of typically 2% if MOSFET gate drive current, current limit, and the line OV/UV/
an out of regulation condition persists. Loss of regulation OVP thresholds. TOP264-271 has improved circuitry to
interrupts the external current into the CONTROL pin. VC maintain all of the above critical parameters within very tight
regulation changes from shunt mode to the hysteretic auto- absolute and temperature tolerances.
restart mode as described in CONTROL pin operation section.
When the fault condition is removed, the power supply output High-Voltage Bias Current Source
becomes regulated, VC regulation returns to shunt mode, and This high-voltage current source biases TOP264-271 from the
normal operation of the power supply resumes. DRAIN pin and charges the CONTROL pin external capacitance
during start-up or hysteretic operation. Hysteretic operation
Hysteretic Over-Temperature Protection (OTP) occurs during auto-restart, remote-off and over-temperature
Temperature protection is provided by a precision analog circuit shutdown. In this mode of operation, the current source is
that turns the output MOSFET off when the junction temperature switched on and off, with an effective duty cycle of approxi-
exceeds the thermal shutdown temperature (142 °C typical). mately 35%. This duty cycle is determined by the ratio of
When the junction temperature cools to below the lower CONTROL pin charge (IC) and discharge currents (ICD1 and ICD2).
hysteretic temperature point, normal operation resumes, thus This current source is turned off during normal operation when
providing automatic recovery. A large hysteresis of 75 °C the output MOSFET is switching. The effect of the current
(typical) is provided to prevent overheating of the PC board due source switching will be seen on the DRAIN voltage waveform
to a continuous fault condition. VC is regulated in hysteretic as small disturbances and is normal.
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TOP264-271
CONTROL (C)
200 µA
400 µA
PI-5567-030910
Figure 10. VOLTAGE MONITOR (V) and EXTERNAL CURRENT LIMIT (X) Pin Input Simplified Schematic.
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TOP264-271
+ +
DC D DC D
Input Input
Voltage CONTROL Voltage CONTROL
C C
S F S F
- -
PI-2654-071700 PI-2655-071700
Figure 11. Full Frequency Operation (132 kHz). Figure 12. Half Frequency Operation (66 kHz).
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TOP264-271
Typical Uses of VOLTAGE MONITOR (V) and EXTERNAL CURRENT LIMIT (X) Pins
V Package (eDIP-12)
+ E Package S 12 1V + VUV = IUV × RLS + VV (IV = IUV)
(eSIP-7C) S 11 2X VOV = IOV × RLS + VV (IV = IOV)
S 10 3C
S9 4F
For RLS = 4 MΩ
S8
RLS 4 MΩ VUV = 102.8 VDC
S7 6D
VXC FS D VOV = 451 VDC
DC S DC
D C DCMAX@100 VDC = 76%
Input Input
Voltage K Package (eSOP-12) Voltage DCMAX@375 VDC = 41%
C S D
D V 1V S 12 D V
2X S 11
CONTROL 3C S 10 CONTROL
C C
4F S9
S8
6D S7
S X F
- S - S
C D
PI-6119-061011 PI-4717-120307
Figure 13. Three Terminal Operation (VOLTAGE MONITOR and EXTERNAL Figure 14. Line-Sensing for Undervoltage, Overvoltage and Line Feed-Forward.
CURRENT LIMIT Features Disabled. FREQUENCY Pin Tied to
SOURCE or CONTROL Pin.)
S S
- -
PI-4719-120307 PI-4720-120307
Figure 15. Line-Sensing for Undervoltage, Overvoltage, Line Feed-Forward and Figure 16. Line-Sensing for Undervoltage Only (Overvoltage Disabled).
Hysteretic Output Overvoltage Protection.
+ + For RIL = 12 kΩ
VOV = IOV × RLS + VV (IV = IOV)
ILIMIT = 61%
4 MΩ
For Values Shown
VOV = 457.2 VDC For RIL = 19 kΩ
RLS ILIMIT = 37%
RIL
S
- -
PI-4721-120307 PI-5580-111210
Figure 17. Line-Sensing for Overvoltage Only (Undervoltage Disabled). Maximum Figure 18. External Set Current Limit.
Duty Cycle Reduced at Low-Line and Further Reduction with
Increasing Line Voltage.
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TOP264-271
Typical Uses of VOLTAGE MONITOR (V) and EXTERNAL CURRENT LIMIT (X) Pins (cont.)
DC DC
Input D Input D
Voltage CONTROL Voltage CONTROL
C C
S X S X
RIL QR ON/OFF
6 kΩ 47 KΩ
- -
PI-5465-061009 PI-5466-061009
Figure 19. Current Limit Reduction with Line Voltage. Figure 20. Active-On (Fail Safe) Remote-ON/OFF, and Latch Reset.
Figure 21. Active-On Remote-ON/OFF with Externally Set Current Limit, Figure 22. Active-On Remote-ON/OFF with Line-Sense and External
and Latch Reset Current Limit, and Latch Reset.
PI-5565-111210
Figure 23. Line Sensing and Externally Set Current Limit. Figure 24. Externally Set Current Limit, Fast AC Latch Reset and Brown-Out.
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TOP264-271
Application Example
PI-5667-030810
Figure 25. Schematic of High Efficiency 19 V, 65 W, Universal Input Flyback Supply with Low No-load.
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TOP264-271
TOPSwitch-JX MOSFET. This arrangement was selected over To minimize the dissipation from the bias winding under no-load
a standard RCD clamp to improve light load efficiency and no-load conditions the number of bias winding turns and value of C10
input power. was adjusted to give a minimum voltage across C10 of ~9 V.
This is the minimum required to keep the optocoupler biased.
In a standard RCD clamp C4 would be discharged by a parallel To minimize the dissipation of the secondary-side feedback
resistor rather than a resistor and series Zener. In an RCD clamp circuit Q2 was added to form a Darlington connection with U3B.
the resistor value is selected to limit the peak drain voltage This reduced the feedback current on the secondary to ~1 mA.
under full load and overload conditions. However under light or The increased loop gain (due to the hFE of the transistor) was
no-load conditions this resistor value now causes the capacitor compensated by increasing the value of R16 and the addition of
voltage to discharge significantly as both the leakage inductance R25. A standard 2.5 V TL431 voltage reference was replaced
energy and switching frequency are lower. As the capacitor has with the 1.24 V LMV431 to reduce the supply current requirement
to be recharged to above the reflected output voltage each from 1 mA to 100 µA.
switching cycle the lower capacitor voltage represents wasted
energy. It has the effect of making the clamp dissipation Output Rectifier Choice
appear as a significant load just as if it were connected to the • Higher current rating, low VF Schottky rectifier diode selected
output of the power supply. for output rectifier.
The RZCD arrangement solves this problem by preventing the A dual 15 A, 100 V Schottky rectifier diode with a VF of 0.455 V
voltage across the capacitor discharging below a minimum at 5 A was selected for D5. This is a higher current rating than
value (defined by the voltage rating of VR2) and therefore required to reduce resistive and forward voltage losses to improve
minimizing clamp dissipation under light and no-load conditions. both full load and average efficiency. The use of a 100 V Schottky
was possible due to the high transformer primary to secondary
Resistors R6 and R28 provide damping of high frequency turns ratio (VOR = 110 V) which was in turn possible due to the
ringing to reduce EMI. Due to the resistance in series with VR2, high-voltage rating of the TOPSwitch-JX internal MOSFET.
limiting the peak current, standard power Zeners vs a TVS type
may be used for lower cost (although a TVS type was selected Increased Output Overvoltage Shutdown Sensitivity
due to availability of a SMD version). Diode D2 was selected to • Transistor Q1 and VR1 added to improve the output over-
have an 800 V vs the typical 600 V rating due to its longer voltage shutdown sensitivity.
reverse recovery time of 500 ns. This allows some recovery of
the clamp energy during the reverse recovery time of the diode During an open-loop condition the output and therefore bias
improving efficiency. Multiple resistors were used in parallel to winding voltage will rise. When this exceeds the voltage of VR1
share dissipation as SMD components were used. plus a VBE voltage drop Q1 turns on and current is fed into the
VOLTAGE MONITOR pin. The addition of Q1 ensures that the
Feedback Configuration current into the VOLTAGE MONITOR pin is sufficient to exceed
• A Darlington connection formed together with optocoupler the latching shutdown threshold even when the output is fully
transistor to reduce secondary-side feedback current and loaded while the supply is operating at low-line as under this
therefore no-load input power. condition the output voltage overshoot is relatively small
• Low voltage, low current voltage reference IC used on
secondary-side to reduce secondary-side feedback current Output overload power limitation is provided via the current limit
and therefore no-load input power. programming feature of the X pin and R7, R8 and R9. Resistors
• Bias winding voltage tuned to ~9 V at no-load, high-line to R8 and R9 reduce the device current limit as a function of
reduce no-load input power. increasing line voltage to provide a roughly flat overload power
characteristic, below the 100 VA limited power source (LPS)
Typically the feedback current into the CONTROL pin at requirement. In order to still meet this under a single fault
high-line is ~3 mA. This current is both sourced from the bias condition (such as open circuit of R8) the rise in the bias voltage
winding (voltage across C10) and directly from the output. Both that occurs during an overload condition is also used to trigger
of these represent a load on the output of the power supply. a latching shutdown.
16
Rev. E 08/12 www.powerint.com
TOP264-271
Very Low No-Load, High Efficiency, 30 W, Universal The size of the magnetic core is a function of the switching
Input, Open Frame, Power Supply frequency. The choice of the higher switching frequency of
132 kHz allowed for the use of a smaller core size. The higher
The circuit shown in Figure 26 below shows an 85 VAC to switching frequency does not negatively impact the efficiency in
265 VAC input, 12 V, 2.5 A output power supply. The goals of TOPSwitch-JX designs due its small drain to source capacitance
the design were highest full load efficiency, average efficiency (COSS) as compared to that of discrete MOSFETs.
(average of 25%, 50%, 75% and 100% load points), very low no-
load consumption. Additional requirements included latching Line-Sense Resistor Values
output overvoltage shutdown and compliance to safety agency • Increasing line-sensing resistance from 4 MΩ to 10.2 MΩ to
limited power source (LPS) limits. Actual efficiency and no-load reduce no-load input power dissipation by 16 mW.
performance is summarized in the table shown in the schematic
which easily exceed current energy efficiency requirements. Line-sensing is provided by resistors R1 and R2 and sets the
line undervoltage and overvoltage thresholds. The combined
In order to meet these design goals the following key design value of these resistors was increased from the standard 4 MW
decisions were made. to 10.2 MW. This reduces the current into the VOLTAGE
MONITOR pin, and therefore contribution to no-load input power,
PI Part Selection from ~26 mW to ~10 mW. To compensate the resultant change in
• Ambient of 40 °C allowed one device size smaller than the UV threshold resistor R12 was added between the CONTROL
indicated by the power table and VOLTAGE-MONITOR pins. This adds a DC current equal to
~16 mA into the VOLTAGE MONITOR pin, requiring only 9 mA to
The device selected for this design was based on the 85-265 VAC, be provided via R1 and R2 to reach the VOLTAGE MONITOR
Open Frame, PCB heat sinking column of power table (Table 1). pin UV threshold current of 25 mA and setting the UV threshold
One device size smaller was selected (TOP266V vs TOP267V) to approximately 95 VDC.
due to the ambient specification of 40 °C (vs the 50°C assumed
in the power table) and the optimum PCB area and layout for This technique does effectively disable the line OV feature as
the device heat sink. The subsequent thermal and efficiency the resultant OV threshold is raised from ~450 VDC to ~980 VDC.
data confirmed this choice. The maximum device temperature However in this design there was no impact as the value of
was 107 °C at full load, 40 °C, 85 VAC, 47 Hz (worst-case input capacitance (C3) was sufficient to allow the design to
conditions) and average efficiency exceeded 83% ENERGY withstand differential line surges greater than 1 kV without the
STAR and EuP Tier 2 requirements. peak drain voltage reaching the BVDSS rating of U1.
Transformer Core Selection Specific guidelines and detailed calculations for the value of R12
• 132 kHz switching frequency allowed the selection of smaller
may be found in the TOPSwitch-JX Application Note.
core for lower cost.
C4 D8,9
4.7 nF SB560
11,12
R5 1 kV
10 kΩ C7 RTN
D1 D2 1/2 W 47 µF
1N4007 1N4007 4 25 V
1
R1 R3 NC NC
5.1 MΩ 10 MΩ D5 D7
FR107 BAV21WS-
2 7-F
T1 R9
EF25 10 Ω R18
110 Ω
R19
C3 VR3 470 Ω
82 µF R2 R4
5.1 MΩ 10 MΩ ZMM5245B-7 C18
400 V 47 nF
D6 50 V R21
BAV19WS D10 86.6 kΩ
LL4148 1%
U2B
L1 LTV817D
R12
14 mH 191 kΩ U2A
D3 D4 1% LTV817D
1N4007 1N4007
D V
C1 TOPSwitch-JX CONTROL
100 nF U1 C
F1 275 VAC TOP266VG
3.15 A R16 C20
S X F 6.8 Ω 33 nF
L C9 1/8 W 50 V
R15 100 nF
85 - 264 50 V C10 U3
14.3 kΩ 47 µF
VAC 1% LMV431A R23
25 V 1% 10 kΩ
N 1%
PI-5775-030810
Figure 26. Schematic of High Efficiency 12 V, 30 W, Universal Input Flyback Supply with Very Low No-load.
17
www.powerint.com Rev. E 08/12
TOP264-271
Clamp Configuration – RZCD vs RCD 1.24 V LMV431 to reduce the supply current requirement of this
• An RZCD (Zener bleed) was selected over RCD to give higher component from 1 mA to 100 mA.
light load efficiency and lower no-load consumption.
Output Rectifier Choice
The clamp network is formed by VR1, C4, R5 and D5. It limits • Use of high VOR allows the use of a 60 V Schottky diode for
the peak drain voltage spike caused by leakage inductance to high efficiency and lower cost.
below the BVDSS rating of the internal TOPSwitch-JX MOSFET.
This arrangement was selected over a standard RCD clamp to The higher BVDSS rating of the TOPSwitch-JX of 725 V
improve light load efficiency and no-load input power. (compared to 600 V or 650 V rating of typical power MOSFETs)
allowed a higher transformer primary to secondary turns ratio
In a standard RCD clamp C4 would be discharged by a parallel (reflected output voltage or VOR). This reduced the output diode
resistor rather than a resistor and series Zener. In an RCD voltage stress and allowed the use of cheaper and more efficient
clamp the resistor value of R5 is selected to limit the peak drain 60 V (vs 80 V or 100 V) Schottky diodes. The efficiency
voltage under full load and overload conditions. However under improvement occurs due the lower forward voltage drop of the
light or no-load conditions this resistor value now causes the lower voltage diodes. Two parallel connected axial 5 A, 60 V
capacitor voltage to discharge significantly as both the leakage Schottky rectifier diodes were selected for both low-cost and
inductance energy and switching frequency are lower. As the high efficiency. This allowed PCB heat sinking of the diode for
capacitor has to be recharged to above the reflected output low cost while maintaining efficiency compared to a single
voltage each switching cycle the lower capacitor voltage higher current TO-220 packaged diode mounted on a heat sink.
represents wasted energy. It has the effect of making the For this configuration the recommendation is that each diode is
clamp dissipation appear as a significant load just as if it were rated at twice the output current and that the diodes share a
connected to the output of the power supply. common cathode PCB area for heat sinking so that their
temperatures track. In practice the diodes current share quite
The RZCD arrangement solves this problem by preventing the effectively as can be demonstrated by monitoring their
voltage across the capacitor discharging below a minimum individual temperatures.
value (defined by the voltage rating of VR1) and therefore
minimizing clamp dissipation under light and no-load conditions. Output Inductor Post Filter Soft-Finish
• Inductor L2 used to provide an output soft-finish and eliminate
Zener VR1 is shown as a high peak dissipation capable TVS
however a standard lower cost Zener may also be used due to a capacitor.
the low peak current that component experiences.
To prevent output overshoot during start-up the voltage
In many designs a resistor value of less than 50 W may be used appearing across L2 is used to provide a soft-finish function.
in series with C4 to damp out high frequency ringing and When the voltage across L2 exceeds the forward drop of U2A
improve EMI but this was not necessary in this case. and D10 current flows though the optocoupler LED and
provides feedback to the primary. This arrangement acts to
Feedback Configuration limit the rate of rise of the output voltage until it reaches
• A high CTR optocoupler was used to reduce secondary bias regulation and eliminates the capacitor that is typically placed
currents and no-load input power. across U3 to provide the same function.
• Low voltage, low current voltage reference IC used on
secondary-side to reduce secondary-side feedback current Key Application Considerations
and no-load input power.
TOPSwitch-JX vs. TOPSwitch-HX
• Bias winding voltage tuned to ~9 V at no-load, high-line to
reduce no-load input power.
Table 3 compares the features and performance differences
between TOPSwitch-JX and TOPSwitch-HX. Many of the new
Typically the feedback current into the CONTROL pin at
features eliminate the need for additional discrete components.
high-line is ~3 mA. This current is both sourced from the bias
Other features increase the robustness of design, allowing cost
winding (voltage across C10) and directly from the output. Both
savings in the transformer and other power components.
of these represent a load on the output of the power supply.
TOP264-271 Design Considerations
To minimize the dissipation from the bias winding under no-load
conditions the number of bias winding turns and value of C7 Power Table
was adjusted to give a minimum voltage across C7 of ~9 V. The data sheet power table (Table 1) represents the maximum
This is the minimum required to keep the optocoupler biased practical continuous output power based on the following
and the output in regulation. conditions:
1. 12 V output.
To minimize the dissipation of the secondary-side feedback 2. Schottky or high efficiency output diode.
circuit a high CTR (CTR of 300 – 600%) optocoupler type was 3. 135 V reflected voltage (VOR) and efficiency estimates.
used. This reduces the secondary-side opto-led current from 4. A 100 VDC minimum DC bus for 85-265 VAC and 250 VDC
~3 mA to <~1 mA and therefore the effective load on the output. minimum for 230 VAC.
A standard 2.5 V TL431 voltage reference was replaced with the 5. Sufficient heat sinking to keep device temperature ≤110 °C.
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Rev. E 08/12 www.powerint.com
TOP264-271
CONTROL current IC(OFF) at IC(OFF) = IB + 3.4 mA IC(OFF) = IB + 1.6 mA • Reduced CONTROL current
0% duty cycle (TOP256-258) (TOP266-268) • Better no-load performance (<0.1 W)
IB = External bias current • Better standby performance
eDIP-12 / eSOP-12 Not available Available • 66/132 kHz frequency option for DIP style heat sink
packages less designs
• Better thermal performance for increased power
capability over DIP-8 / SMD-8 packages
Breakdown voltage BVDSS Min. 700 V at TJ = 25 °C Min. 725 V at TJ = 25 °C • Simplifies meeting customer derating requirements
(e.g. 80%)
• Extended line surge withstand
Fast AC reset 3 external transistor circuits 1 external transistor circuit • Saves 5 components
using the V pin using the X pin
6. Power levels shown in the power table for the V package dissipation can be minimized by reducing the external current
device assume 6.45 cm2 of 610 g/m2 copper heat sink area limit as a function of input line voltage (see Figure 19). The RCD
in an enclosed adapter, or 19.4 cm2 in an open frame. clamp is more cost effective than the Zener clamp but requires
more careful design (see Quick Design Checklist).
The provided peak power depends on the current limit for the
respective device. Output Diode
The output diode is selected for peak inverse voltage, output
TOP264-271 Selection current, and thermal conditions in the application (including heat
Selecting the optimum TOP264-271 depends upon required sinking, air circulation, etc.). The higher DCMAX of TOP264-271,
maximum output power, efficiency, heat sinking constraints, along with an appropriate transformer turns ratio, can allow the
system requirements and cost goals. With the option to use of a 80 V Schottky diode for higher efficiency on output
externally reduce current limit, TOP264-271 may be used for voltages as high as 15 V.
lower power applications where higher efficiency is needed or
minimal heat sinking is available. Bias Winding Capacitor
Due to the low frequency operation at no-load, a bias winding
Input Capacitor capacitance of 10 mF minimum is recommended. Ensure a
The input capacitor must be chosen to provide the minimum minimum bias winding voltage of >9 V at zero load for correct
DC voltage required for the TOP264-271 converter to maintain operation and output voltage regulation.
regulation at the lowest specified input voltage and maximum
output power. Since TOP264-271 has a high DCMAX limit and an Soft-Start
optimized dual slope line feed forward for ripple rejection, it is Generally, a power supply experiences maximum stress at
possible to use a smaller input capacitor. For TOP264-271, a start-up before the feedback loop achieves regulation. For a
capacitance of 2 mF per watt is possible for universal input with period of 17 ms, the on-chip soft-start linearly increases the
an appropriately designed transformer. drain peak current and switching frequency from their low
starting values to their respective maximum values. This
Primary Clamp and Output Reflected Voltage VOR causes the output voltage to rise in an orderly manner, allowing
A primary clamp is necessary to limit the peak TOP264-271 drain time for the feedback loop to take control of the duty cycle.
to source voltage. A Zener clamp requires few parts and takes This reduces the stress on the TOP264-271 MOSFET, clamp
up little board space. For good efficiency, the clamp Zener circuit and output diode(s), and helps prevent transformer
should be selected to be at least 1.5 times the output reflected saturation during start-up. Also, soft-start limits the amount of
voltage VOR, as this keeps the leakage spike conduction time output voltage overshoot and, in many applications, eliminates
short. When using a Zener clamp in a universal input application, the need for a soft-finish capacitor. Note that as soon as the
a VOR of less than 135 V is recommended to allow for the absolute loop closes the soft-start function ceases even if this is prior to
tolerances and temperature variations of the Zener. This will the end of the 17 ms soft-start period.
ensure efficient operation of the clamp circuit and will also keep
the maximum drain voltage below the rated breakdown voltage EMI
of the TOP264-271 MOSFET. A high VOR is required to take full The frequency jitter feature modulates the switching frequency
advantage of the wider DCMAX of TOP264-271. An RCD (or over a narrow band as a means to reduce conducted EMI peaks
RCDZ) clamp provides tighter clamp voltage tolerance than a associated with the harmonics of the fundamental switching
Zener clamp and allows a VOR as high as 150 V. RCD clamp frequency. This is particularly beneficial for average detection
19
www.powerint.com Rev. E 08/12
TOP264-271
mode. As can be seen in Figures 27 and 28, the benefits of jitter closely between their respective pin and SOURCE. Once again,
increase with the order of the switching harmonic due to an the SOURCE connection trace of these components should not
increase in frequency deviation. The FREQUENCY pin offers a be shared by the main MOSFET switching currents. It is very
switching frequency option of 132 kHz or 66 kHz. In applications critical that SOURCE pin switching currents are returned to the
that require heavy snubber on the drain node for reducing high input capacitor negative terminal through a separate trace that is
frequency radiated noise (for example, video noise sensitive not shared by the components connected to CONTROL,
applications such as VCRs, DVDs, monitors, TVs, etc.), operating VOLTAGE MONITOR or EXTERNAL CURRENT LIMIT pins. This
at 66 kHz will reduce snubber loss, resulting in better efficiency. is because the SOURCE pin is also the controller ground
Also, in applications where transformer size is not a concern, use reference pin. Any traces to the VOLTAGE MONITOR,
of the 66 kHz option will provide lower EMI and higher efficiency. EXTERNAL CURRENT LIMIT or CONTROL pins should be kept
Note that the second harmonic of 66 kHz is still below 150 kHz, as short as possible and away from the DRAIN trace to prevent
above which the conducted EMI specifications get much tighter. noise coupling. Voltage monitor resistors (RLS in Figures 14, 15,
For 10 W or below, it is possible to use a simple inductor in place 19, 22, 23, 26, 30) and primary-side OVP circuit components
of a more costly AC input common mode choke to meet V ZOV/ROV in Figures (29, 30) should be located close to the
worldwide conducted EMI limits. VOLTAGE MONITOR pin to minimize the trace length on the
VOLTAGE MONITOR pin side. Resistors connected to the
Transformer Design VOLTAGE MONITOR or EXTERNAL CURRENT LIMIT pin should
It is recommended that the transformer be designed for be connected as close to the bulk capacitor positive terminal as
maximum operating flux density of 3000 Gauss and a peak flux possible while routing these connections away from the power
density of 4200 Gauss at maximum current limit. The turns ratio switching circuitry. In addition to the 47 μF CONTROL pin
should be chosen for a reflected voltage (VOR) no greater than
135 V when using a Zener clamp or 150 V (max) when using an 80
PI-2576-010600
RCD clamp with current limit reduction with line voltage (overload 70
protection). For designs where operating current is significantly
lower than the default current limit, it is recommended to use an 60
Amplitude (dBµV)
PI-5583-090309
70 TOPSwitch-JX (with jitter)
TOP264-271 Layout Considerations
60
Amplitude (dBµV)
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Rev. E 08/12 www.powerint.com
TOP264-271
capacitor, a high frequency bypass capacitor (CBP) in parallel power traces from other converters. If the line-sensing features
should be used for better noise immunity. The feedback are used, then the sense resistors must be placed within 10 mm
optocoupler output should also be located close to the of the VOLTAGE MONITOR pin to minimize the VOLTAGE
CONTROL and SOURCE pins of TOP264-271 and away from the MONITOR pin node area. The DC bus should then be routed to
drain and clamp component traces. The primary-side clamp the line-sense resistors. Note that external capacitance must
circuit should be positioned such that the loop area from the not be connected to the VOLTAGE MONITOR pin as this may
transformer end (shared with DRAIN) and the clamp capacitor is cause misoperation of the VOLTAGE MONITOR pin related
minimized. The bias winding return node should be connected functions. As with any power supply design, all TOP264-271
via a dedicated trace directly to the bulk capacitor and not to designs should be verified on the bench to make sure that
the SOURCE pins. This ensures that surge currents are routed components specifications are not exceeded under worst-case
away from the SOURCE pins of the TOPSwitch-JX. conditions. The following minimum set of tests is strongly
recommended:
Y Capacitor
The Y capacitor should be connected close to the secondary 1. Maximum drain voltage – Verify that peak VDS does not
output return pin(s) and the positive primary DC input pin of the exceed 675 V at highest input voltage and maximum
transformer. If the Y capacitor is returned to the negative end of overload output power. Maximum overload output power
the input bulk capacitor (rather than the positive end) a dedicated occurs when the output is overloaded to a level just before
trace must be used to make this connection. This is to “steer” the power supply goes into auto-restart (loss of regulation).
leakage currents away from the SOURCE pins in case of a 2. Maximum drain current – At maximum ambient temperature,
common-mode surge event. maximum input voltage and maximum output load, verify
drain current waveforms at start-up for any signs of trans-
Heat Sinking former saturation and excessive leading edge current spikes.
The exposed pad of the E package (eSIP-7C), K package TOP264-271 has a leading edge blanking time of 220 ns to
(eSOP-12) and the V package (eDIP-12) are internally electrically prevent premature termination of the ON-cycle. Verify that
tied to the SOURCE pin. To avoid circulating currents, a heat the leading edge current spike is below the allowed current
sink attached to the exposed pad should not be electrically tied limit envelope (see Figure 34) for the drain current waveform
to any primary ground/source nodes on the PC board. On at the end of the 220 ns blanking period.
double sided boards, top side and bottom side areas connected 3. Thermal check – At maximum output power, both minimum
with vias can be used to increase the effective heat sinking and maximum voltage and ambient temperature; verify that
area. The K package exposed pad may be directly soldered to temperature specifications are not exceeded for TOP264-
a copper area for optimum thermal transfer. In addition, 271, transformer, output diodes and output capacitors.
sufficient copper area should be provided at the anode and Enough thermal margin should be allowed for the part-to-
cathode leads of the output diode(s) for heat sinking. In Figure part variation of the RDS(ON) of TOP264-271, as specified in
29, a narrow trace is shown between the output rectifier and the data sheet. The margin required can either be calculated
output filter capacitor. This trace acts as a thermal relief from the values in the parameter table or it can be accounted
between the rectifier and filter capacitor to prevent excessive for by connecting an external resistance in series with the
heating of the capacitor. DRAIN pin and attached to the same heat sink, having a
resistance value that is equal to the difference between the
Quick Design Checklist
measured RDS(ON) of the device under test and the worst-case
In order to reduce the no-load input power of TOP264-271 maximum specification.
designs, the VOLTAGE MONITOR pin operates at very low
Design Tools
current. This requires careful layout considerations when
designing the PCB to avoid noise coupling. Traces and Up-to-date information on design tools can be found at the
components connected to the VOLTAGE MONITOR pin should Power Integrations website: www.powerint.com
not be adjacent to any traces carrying switching currents.
These include the drain, clamp network, bias winding return or
21
www.powerint.com Rev. E 08/12
TOP264-271
+
for Optimum Heat Sinking
RLS1 J2
RPL1
CB U2
ROV U3
RPL2
RLS2
DB T1
C16
HF LC
Post-Filter
VZOV
R12 Output Filter C18
U1 Capacitors
RIL R16
CBP
Transformer L2
C10
C17
Output
J1 Rectifiers D8
–
D5 R5 D9
DC
IN Y-
Capacitor
VR1
+
C4 C3 C11
Figure 29. Layout Considerations for TOPSwitch-JX using V Package and Operating at 132 kHz.
+
for Optimum Heat Sinking
RLS1 J2
RPL1
CB+
U2
ROV U3
RPL2
RLS2
T1
DB HF LC
C16
C18 Post-Filter
VZOV
RIL R12 Output Filter
U1 Capacitors
RIL CBP R16
CBP
Transformer L2
C10
C17
Output
J1 Rectifiers D8
–
D5 R5 D9
DC
IN Y-
Capacitor
VR1
+
C4 C3 C11
Figure 30. Layout Considerations for TOPSwitch-JX using K Package and Operating at 132 kHz.
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Rev. E 08/12 www.powerint.com
TOP264-271
- DC +
OUT PI-5793-030910
Figure 31. Layout Considerations for TOPSwitch-JX using E Package and Operating at 132 kHz.
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TOP264-271
Thermal Resistance
Thermal Resistance: E Package Notes:
(qJA)........................................... 105 °C/W(1) 1. Free standing with no heat sink.
(qJC)............................................... 2 °C/W(2) 2. Measured at the back surface of tab.
V Package 3. Soldered (including exposed pad for K package) to typical
(qJA)............................68 °C/W(3), 58 °C/W(4) application PCB with a heat sinking area of 0.36 sq. in. (232mm2),
(qJC)............................................... 2 °C/W(2) 2 oz. (610 g/m2) copper clad.
K Package 4. Soldered (including exposed pad for K package) to typical
(qJA) ...........................45 °C/W(3), 38 °C/W(4) application PCB with a heat sinking area of 1 sq. in. (645 mm2),
(qJC)............................................... 2 °C/W(2) 2 oz. (610 g/m2) copper clad.
Conditions
SOURCE = 0 V; TJ = -40 to 125 °C
Parameter Symbol Min Typ Max Units
See Figure 35
(Unless Otherwise Specified)
Control Functions
Switching Frequency FREQUENCY Pin 119 132 145
Connected to SOURCE
in Full Frequency fOSC TJ = 25 °C kHz
FREQUENCY Pin
Mode (average) 59.4 66 72.6
Connected to CONTROL
Frequency Jitter 132 kHz Operation ±5
Df kHz
Deviation 66 kHz Operation ±2.5
Frequency Jitter
fM 250 Hz
Modulation Rate
IV ≤ IV(DC)
75 78 83
Maximum Duty Cycle DCMAX IC = ICD1 VV = 0 V %
IV = 95 mA 30
Soft-Start Time tSOFT TJ = 25 °C 17 ms
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Rev. E 08/12 www.powerint.com
TOP264-271
Conditions
Parameter Symbol SOURCE = 0 V; TJ = -40 to 125 °C Min Typ Max Units
(Unless Otherwise Specified)
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www.powerint.com Rev. E 08/12
TOP264-271
Conditions
Parameter Symbol SOURCE = 0 V; TJ = -40 to 125 °C Min Typ Max Units
(Unless Otherwise Specified)
Voltage Monitor (V) and External Current Limit (X) Inputs (cont.)
Output Overvoltage
Latching Shutdown IOV(LS) TJ = 25 °C 269 336 403 mA
Threshold Current
V Pin Remote
VV(TH) TJ = 25 °C 0.8 1.0 1.6 V
ON/OFF Voltage
V Pin Short-Circuit
IV(SC) TJ = 25 °C VV = VC 300 400 500 mA
Current
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Rev. E 08/12 www.powerint.com
TOP264-271
Conditions
Parameter Symbol SOURCE = 0 V; TJ = -40 to 125 °C Min Typ Max Units
(Unless Otherwise Specified)
Circuit Protection
TOP264
di/dt = 270 mA/ms 1.209 1.30 1.391
TJ = 25 °C
TOP265
di/dt = 350 mA/ms 1.581 1.70 1.819
TJ = 25 °C
TOP266
di/dt = 530 mA/ms 2.371 2.55 2.728
TJ = 25 °C
TOP267
Self Protection di/dt = 625 mA/ms 2.800 3.01 3.222
TJ = 25 °C
Current Limit ILIMIT A
(See Note D) TOP268
di/dt = 675 mA/ms 3.023 3.25 3.478
TJ = 25 °C
TOP269
di/dt = 720 mA/ms 3.236 3.48 3.723
TJ = 25 °C
TOP270
di/dt = 870 mA/ms 3.906 4.20 4.494
TJ = 25 °C
TOP271 di/dt = 1065 mA/ms 4.808 5.17 5.532
TJ = 25 °C
0.70 ×
Initial Current Limit IINIT See Note C A
ILIMIT(MIN)
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TOP264-271
Conditions
Parameter Symbol SOURCE = 0 V; TJ = -40 to 125 °C Min Typ Max Units
(Unless Otherwise Specified)
Output
TOP264 TJ = 25 °C 5.4 6.25
ID = 150 mA TJ = 100 °C 8.35 9.70
TOP265 TJ = 25 °C 4.1 4.70
ID = 200 mA TJ = 100 °C 6.3 7.30
TOP266 TJ = 25 °C 2.8 3.20
ID = 300 mA TJ = 100 °C 4.1 4.75
TOP267 TJ = 25 °C 2.0 2.30
ON-State ID = 400 mA TJ = 100 °C 3.1 3.60
RDS(ON) W
Resistance TOP268 TJ = 25 °C 1.7 1.95
ID = 500 mA TJ = 100 °C 2.5 2.90
TOP269 TJ = 25 °C 1.45 1.70
ID = 600 mA TJ = 100 °C 2.25 2.60
TOP270 TJ = 25 °C 1.20 1.40
ID = 700 mA TJ = 100 °C 1.80 2.10
TOP271 TJ = 25 °C 1.05 1.20
ID = 800 mA TJ = 100 °C 1.55 1.80
18
DRAIN Supply Voltage TJ ≤ 85 °C, See Note F V
36
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TOP264-271
NOTES:
A. Derived during test from the parameters DCMAX, IB and IC(OFF) at 132 kHz.
B. For specifications with negative values, a negative temperature coefficient corresponds to an increase in magnitude with increasing
temperature, and a positive temperature coefficient corresponds to a decrease in magnitude with increasing temperature.
C. Guaranteed by characterization. Not tested in production.
D. For externally adjusted current limit values, please refer to Figures 36 and 37 (Current Limit vs. External Current Limit Resistance)
in the Typical Performance Characteristics section. The tolerance specified is only valid at full current limit.
E. I2f calculation is based on typical values of ILIMIT and fOSC, i.e. ILIMIT(TYP)2 × fOSC, where fOSC = 66 kHz or 132 kHz depending on FREQUENCY
pin connection. See fOSC specification for detail.
F. The device will start up at 18 VDC drain voltage. The capacitance of electrolytic capacitors drops significantly at temperatures below
0 °C. For reliable start-up at 18 V in sub-zero temperatures, designers must ensure that circuit capacitors meet recommended
capacitance values.
G. Breakdown voltage may be checked against minimum BVDSS specification by ramping the DRAIN pin voltage up to but not exceeding
minimum BVDSS.
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TOP264-271
t2
t1
HV
90% 90%
DRAIN t1
D=
VOLTAGE t2
10%
0V
PI-2039-033001
PI-4758-061407
tLEB (Blanking Time)
120 1.3
PI-4737-061207
1.2
100 1.1
1.0
80 0.9
0.8
0.7 IINIT(MIN)
60
0.6
0.5
40
0.4
Dynamic 1
= 0.3
Impedance Slope
20 0.2
0.1
0 0
5 6 7 8 9 0 1 2 3 4 5 6 7 8
CONTROL Pin Voltage (V) Time (µs)
Figure 33. CONTROL Pin I-V Characteristic. Figure 34. Drain Current Operating Envelope.
(X and V Pins)
S1 470 Ω
5W 0-300 kΩ
5-50 V
40 V
V D
470 Ω CONTROL
C C
S2
S4 F X S
0-15 V
S3
47 µF 0.1 µF
0-60 kΩ
NOTES: 1. This test circuit is not applicable for current limit or output characteristic measurements.
PI-5534-072409
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TOP264-271
PI-5581-090309
1.1 1.1
1 1
Maximum
0.9 0.9
Normalized Current Limit
0.8 0.8
Normalized di/dt
0.7 0.7
Typical
0.6 0.6
0.5 0.5
Minimum
0.4 0.4 t
Normalized
0.3 Current Limit 0.3
Notes:
1. Maximum and Minimum levels are
0.2 based on characterization. 0.2
O O
2. T J = 0 C to 125 C.
0.1 0.1
0 0
-200 -150 -100 -50 0
I X ( µA )
Figure 36. Normalized Current Limit vs. X Pin Current.
PI-5582-090309
1.1 1.1
Notes:
1 1. Maximum and Minimum levels are 1
based on characterization.
0.9 2. T J = 0 OC to 125 OC. 0.9
3. Includes the variation of X pin voltage.
0.8 0.8
Maximum s)
µ
Normalized Current Limit
0.7 0.7
Normalized di/dt
0.6 Typical
0.6
0.5 0.5
0.4 0.4
Normalized di
0.3
Normalized Current Limit (A) 0.3
0.2 0.2
Minimum
0.1 0.1
0 0
0 5 10 15 20 25 30 35 40 45
RIL ( kΩ )
Figure 37. Normalized Current Limit vs. External Current Limit Resistance.
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1.1 1.2
PI-4759-061407
PI-176B-033001
1.0
(Normalized to 25 °C)
(Normalized to 25 °C)
Output Frequency
Breakdown Voltage
0.8
1.0 0.6
0.4
0.2
0.9 0
-50 -25 0 25 50 75 100 125 150 -50 -25 0 25 50 75 100 125 150
Junction Temperature (°C) Junction Temperature (°C)
Figure 38. Breakdown Voltage vs. Temperature. Figure 39. Frequency vs. Temperature.
1.2 1.2
PI-4739-061507
PI-4760-061407
1.0 1.0
(Normalized to 25 ϒC)
(Normalized to 25 °C)
0.8
Current Limit
0.8
Current Limit
0.6 0.6
0.4
0.4
0.2
0.2
0
0 -50 -25 0 25 50 75 100 125 150
-50 -25 0 25 50 75 100 125 150
Junction Temperature (°C)
Junction Temperature (°C)
Figure 41. External Current Limit vs. Temperature with RIL = 10.5 kW.
Figure 40. Internal Current Limit vs. Temperature.
Undervoltage Threshold
1.0 1.0
Overvoltage Threshold
(Normalized to 25 °C)
(Normalized to 25 °C)
0.8 0.8
0.6 0.6
0.4 0.4
0.2 0.2
0 0
-50 -25 0 25 50 75 100 125 150 -50 -25 0 25 50 75 100 125 150
Junction Temperature (°C) Junction Temperature (°C)
Figure 42. Overvoltage Threshold vs. Temperature. Figure 43. Undervoltage Threshold vs. Temperature.
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TOP264-271
PI-4740-060607
PI-4741-110907
VX = 1.354 - 1147.5 × IX + 1.759 × 106 ×
5.5
3 0.4
2.5 0.2
2 0
0 100 200 300 400 500 -200 -150 -100 -50 0
VOLTAGE-MONITOR Pin Current (µA) EXTERNAL CURRENT LIMIT Pin Current (µA)
Figure 44. VOLTAGE-MONITOR Pin vs. Current. Figure 45. EXTERNAL CURRENT LIMIT Pin Voltage vs. Current.
1.2 1.2
PI-4764-061407
PI-4763-072208
0.8 0.8
0.6 0.6
0.4 0.4
0.2 0.2
0 0
-50 -25 0 25 50 75 100 125 150 -50 -25 0 25 50 75 100 125 150
Junction Temperature (°C) Junction Temperature (°C)
Figure 46. Control Current Out at 0% Duty Cycle vs. Temperature. Figure 47. Maximum Duty Cycle Reduction Onset Threshold
Current vs. Temperature.
5 1
PI-5569-110409
PI-4744-072208
VC = 5 V
CONTROL Pin Current (mA)
0.5
4
DRAIN Current (A)
0
3
-0.5
Scaling Factors:
TOP271 1.62
TOP270 1.42 -1
2 TOP269 1.17
TOP268 1.00
TOP267 0.85 -1.5
1 TOP266 0.61
TOP265 0.42
TCASE = 25 °C TOP264 0.32 -2
TCASE = 100 °C
0 -2.5
0 2 4 6 8 10 12 14 16 18 20 0 20 40 60 80 100
Drain Voltage (V) Drain Pin Voltage (V)
Figure 48. Output Characteristics. Figure 49. IC vs. DRAIN Voltage.
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10000 500
PI-5570-090309
PI-5571-090309
Scaling Factors: Scaling Factors:
TOP271 1.62 TOP271 1.62
TOP270 1.42
DRAIN Capacitance (pF)
TOP270 1.42
TOP269 1.17 400 TOP269 1.17
TOP268 1.00 TOP268 1.00
132 kHz
1000 TOP267 0.85 TOP267 0.85
Power (mW)
TOP266 0.61 300 TOP266 0.61
TOP265 0.42 TOP265 0.42
TOP264 0.32 TOP264 0.32
200
100
66 kHz
100
10 0
0 100 200 300 400 500 600 0 100 200 300 400 500 600 700
Drain Pin Voltage (V) Drain Pin Voltage (V)
Figure 50. COSS vs. DRAIN Voltage. Figure 51. DRAIN Capacitance Power.
1.2
Remote OFF DRAIN Supply Current
PI-4745-061407
1.0
(Normalized to 25 °C)
0.8
0.6
0.4
0.2
0
-50 -25 0 25 50 75 100 125 150
Junction Temperature (°C)
Figure 52. Remote-OFF DRAIN Supply Current vs. Temperature.
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Rev. E 08/12 www.powerint.com
TOP264-271
eSIP-7C (E Package)
C
2
0.403 (10.24) 0.081 (2.06) 0.264 (6.70)
A
0.397 (10.08) 0.077 (1.96) Ref.
B
Detail A
2
0.325 (8.25) 0.290 (7.37)
Ref. 0.198 (5.04) Ref.
0.320 (8.13)
0.519 (13.18)
Ref.
PI-4917-061510
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TOP264-271
eDIP-12B (V Package)
0.004 [0.10] C A
2
0.325 [8.26] Seating Plane C 0.400 [10.16]
Pin #1 I.D. Max. 0.016 [0.41]
11× A
(Laser Marked) 10 0.011 [0.28]
0.120 [3.05] 0.010 [0.25] Ref. 0.059 [1.50]
2X 1 2 3 4 6 Ref. 6 1 Ref, typ.
0.004 [0.10] C B
0.412 [10.46] 7
2
Ref. 0.400 [10.16]
0.350 [8.89] 0.225 [5.72] 8
0.306 [7.77]
Max. 0.436 [11.08] 0.059 [1.50]
10 Ref.
0.406 [10.32] Ref, typ.
B 12 11 10 9 8 7 7 12
3 4
Detail A 0.023 [0.58]
5 °± 4° 0.018 [0.46]
11×
TOP VIEW 0.104 [2.65] Ref.
0.010 [0.25] M C A B
0.192 [4.87]
H Ref.
0.031 [0.80] 0.020 [0.51]
0.028 [0.72] Ref.
0.070 [1.78] 0.028 [0.71]
Ref.
36
Rev. E 08/12 www.powerint.com
TOP264-271
eSOP-12B (K Package)
0.010 [0.25]
0.356 [9.04] Ref.
Ref. 0.055 [1.40] Ref.
2 0.004 [0.10] C A 2X
0.400 [10.16] 0.325 [8.26]
Pin #1 I.D. H
(Laser Marked) Max. 7 0.010 [0.25]
2X 7 12
0.004 [0.10] C B Gauge Plane
Seating Plane
0.059 [1.50]
0°- 8°
C
Ref, Typ 2 0.034 [0.85]
0.460 [11.68] 0.350 [8.89] 0.225 [5.72] 0.026 [0.65]
Max. 7
0.059 [1.50]
Ref, Typ
DETAIL A (Scale = 9X)
3 4 6 B 6 1 0.049 [1.23]
0.008 [0.20] C 1 2
3 4 0.028 [0.71] 0.046 [1.16]
2X, 5/6 Lead Tips 0.023 [0.58] 0.120 [3.05] Ref
11× Ref.
0.018 [0.46]
0.070 [1.78]
0.010 (0.25) M C A B
37
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TOP264-271
38
Rev. E 08/12 www.powerint.com
TOP264-271
39
www.powerint.com Rev. E 08/12
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Integrations does not assume any liability arising from the use of any device or circuit described herein. POWER INTEGRATIONS MAKES
NO WARRANTY HEREIN AND SPECIFICALLY DISCLAIMS ALL WARRANTIES INCLUDING, WITHOUT LIMITATION, THE IMPLIED
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The products and applications illustrated herein (including transformer construction and circuits external to the products) may be covered
by one or more U.S. and foreign patents, or potentially by pending U.S. and foreign patent applications assigned to Power Integrations.
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whose failure to perform, when properly used in accordance with instructions for use, can be reasonably expected to result in significant
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