Am2056 EPIC2™ Advanced

Extended PCM Interface Controller 2 Micro

Devices
Version Al
Preliminary Data Sheet
6/90

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Publication /I Rev, Amendment

15115 A /0 /
Issue Date: A

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 EPIC::! Dala Sheel 6i90

o.
Upstream: Direction Irom the subscriber to the PCM highways in the exhange.

Downstream: DireC1lOn Irom rCM 10 the subscribers.

Time Slot: Defined period 01 Ijme in the PCM or 10M2 frame consisting of 8 bits
Time siolS are allocated 10 Ihe frames in such a way that Ihe time slOI
boundaries coincide with Ihe boundaries. The lime slots do no!
overlap. The lowest lime 5101 number is O. This lime Slol is the lirs! In
thelrame.

Sub Time SIOI: A quarter or half a lime slot These are allocaled 10 the lime SIO!S In
such a way Ihal time slot and sub time slot bOundaries match The Sub
lime slots are rIOl ovenapping.

Channel: Sequence of bits which is exchanged between Ihe subscriber. Ihe ex·
change equipmen1 and/or the microprocessor. It occupies a defined
number of bils al a defined pasHian within a frame as long as a connec­
tion peIValls. Both lime slots and sub lime slots are channels and
hence a channel may offer a bandwidth of 16 or 64 kbps.

Bit Numbering: The bits in a lime slot are numbered 7 through 0 (LS8) 81t 7 is
Ihe lirst bit 10 be Iransmllted or received. bit 0 Ihe las\.

This Material By rts Respec ive Manufacturer

 EPIC2 Data Sheet 6/90

1. IntroduCllon

, .1. Features

Board Controller for up to 8 ISDN subscribers

Time SIOI assignment freely for ail connected subscribers
• Two serial in1erfaces (PCM and 10M2)

PCIIA interface

- Tristate con1rol signals for external drivers

clock shit!
10M2 interlace
- B channel switching
- D cnannel switching
- Buffered access to monitor and C/I channel
Standard uP interface with multiplexed addresS/dala bus or separate address and dala

Handling of layer 1 functions

detection logic for Cli channel

- Buffered mon~or Channel

uP accesss to PCM/IOM2 channels

44 pin PLCC

Advance low power CMOS technology

Pin compatible with EPIC (PES

This Materia By Its Respective Manufacturer

 EPIC2 Data Sheet 6/90

1.2. Pin configuration

•• 00 flU,). It.02 Je,\J, AO voo "ts ".IJ, "..u. M\) 000

, ~ J 2 ... 4J 42 .. .00

A'

TS1:1l
•
0 J.

J.III
"3

OliO

TwOO 11 17 "LU,

".\J, J.III N.U.

'0

",u. n :l5 ",U

'm:l n E I C2
J4 fSC

Del.
ToO' .] Jl

,""U, I. n lJI'f

''''I, "
JI AU:

""S It 30 t'1:

I"\'X: H
"
.9 20 3' 22 2l 2- <$ ,. 27 21 %t
WI Jl/11

Al .AIX! AO' AC2 ADJ AD' ADS AOI 14)1 V$S lIIDD'S

Figure 1.1; Pin Configuration (lop view)

This Material By Its Respective Manufacturer

 EPIC2 Data Sheet 6;90

1.3. General Device Overview

The ex1ended PCM interface controller 2 EPIC2 (PE8 2056) is a monolithic switching device
for the path control of 24 channels (16 channels of 64kbps and 8 channels of 16kbps). For
these Channels the EPIC2 performs nonblocking space time switching betWeen two serial in·
terfaces, the PCM and the 10M2 interface.

The PCM interface can be progralTVTled to operate at 15.16.1544.2048.2056.3072.3080.4096

and 4104 kbpS. It consists of two duplex ports with a !ristate indication signal for each line.

The 10M2 interface operates at 1536 or 2048 kbps. tt consists of one duplex port.

The EPIC2 handles the layer 1 functions of buHering the CII and monitor channels lor 10M2
compatible devices.

The EPIC2 is controlled by a standard 8 bil parallel microprocessor with a mutliplexed

address·data bus or separate address-<lata busses.

The EPIC2 can handle up to 6 or 8 ISDN subscribers.

Moreover. the EPIC2 is one of the fundamental building blocks for nelWorX with either central.
decentral or mixed Signalling and packet data handling arChitectures. The other key devices
are the IDEC (ISDN digital exchange controller. PE8 2075) and the HSCX (enhanced h.gh
level serial communication controller, SA8 82525).

Applications of the EPIC2 include peripheral ISDN line cards.

The EPIC2 is pin compatible but not software compatible with EPIC (PES 2055) ..

Thi s Material Copyrighted By Its Respective Manufacturer

 EPIC::! Data Sheet 6. 90

1.4. Pin definitions and functions

Syrrbol Pin no. Typ Function

PLCC i
,
Input (I)
Push-pull !
output(O)
Open drain (OD)
I
VDD 1 I Supply voltaQe SV:: 5%. i
,
AO 2 I Address bus bit 0: This input interlaces to the
system 's address bus to select an internal re 9 1' 1
ster ror a read or write access . This pin is only
provided in the PLCC pad<age and only active i1
a demul\iplexed uP interlace mode is selected . I
AxD2 4 I Receive PCM interlace data : Serial data is rece i- I
AxDO 6 I ved at these lines at standard TTL or CMOS I
levels.
i
A1 7 f Address bus bit 1 !,
TSCO 8 0 Tristate contror for the PCM inter1ace : These lines !
TSC2 12 0 are low when the corresponding TxD outputs are j
valid . .

TxDO 9 0 Transmit PCM inter1_ace data : Serial data is sent I

TxD2 13 0 by these lines at standard TTL or CMOS levels.
I
These pins can't be tristated .
I
16 I PCM inter1ace frame synchronization pulse .
PFS I
PDC 17 I I PCM inter1ace data clod(, single or dOuble rate ., I
A2. 18 I Address bus bit 2 I
ADO 19 VO Address data bus: If the multiplexed
AD1 20 I/O addresS/data uP interlace bus mode is selected I
AD2
AD3
21
22
1/0
vO
these pins transfer data and commands between
the uP and the EPIC2. If a demultiplexed mode is
I
AD4 23 VO used, these bits inter1ace with the system data .
ADS 24 1/0 bus. 1
AD6 25 VO
AD7 26 vO

VSS 27 I Ground: OV

RD 28 I Reaci: The signal indicates a read operation,

OS active low.

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 EPIC2 Data Sheet 6190

Syrrbol Pin no. Typ Function

PLCC

WR 29 I Write: This signal indicates a write operation I

R/'N active low. I
I
CS 30 I Chip select: A low on this line selects the EPIC2
lor a readlwrite operation.
I
ALE 31 I Address latch enable: In the Intel type multiple­
xed uP ~rrtertace mode a logical high on this line
indicates an address of Cln EPIC2 intemal reoister
on the enemal addresS/data bus. In the INztel
type derTlJltiplexed uP intertace mode this line is
hardwired to VSS, in the demultiplexed Motorola
type uP irrtertace mode it shpould be connect ed
toVDD.
!
INT 32 00 Interrupt line, active low .

Del 33 0 Data clock output. I

FSC 34 0 Frame synchronization output.

DUO 38 I Data upstream input.

I
A3 39 I Address bus bit 3.

DDO 40 0/00 Data downstream output.

RES 44 I Reset : A logical high on this input forces the

EPIC2 into the reset state .

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 EPIC2 Data Sheet 6/90

1.5. Logic symbol

ION2 tim;n9
DO.. poe
{ rse PFS
} pc;.. tim;"'9

.
FhOC
EPIC2 r.oo } PCMO
'lSC"O

R.02
r'{)2 } PCM2
~

,U rr1,
'"

Figure, .2: Functional symbol

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 EPIC2 Data Sheet 6/90

1.6. System Integration

1.6.1. line cards

The EPIC2 is 10 operate in digital line cards

The EPIC2 sUPPOI1S up 10 8 ISDN subscribers. are connected ....ia Ihe sec·s (PES 208').
IBC-B 2096) or IEC (PEB 20901 and PES In all cases the IDEC 2075) may
I"IP,1nl"m the 0 channel handling. The HSCX may be used as a packet handler,

On line cards, the EPIC2 penorms the swHching function for up \0 8 ISDN subscribers
belWeen Ihe PCM system highways and Ihe 10M2 interface, Moreo ....er.it has Ihe layer' con·
trolling capability ot buffering Ihe C/I and monitor channels of the 10M2 interlace,

Several archnectures are possible,

In completely decentral 0 channel processing architectures (Fig, 1.3), Ihe processing ""''''::I,"ifv
of a line card is usually dimensioned 10 avoid situalions e....en under maximum con­
ceivable 0 channellralfic conditions. In such an architecture the EPIC2 switches the B chan·
nels and periorms C/I and monitor channel control. The IDECs handle the layer 2 functions tor
and data packets In Ihe 0 channel and transfer the extracted data via the uP and an
HOlC controller. e,g the HSCX (enhanced high lelfel serial communication controller SA8
to the system, One 01 the channels 01 the HSCX be used for example lor the si·
information. the other lor data The may access either a time slot 01
programmable bandWid1h on one 01 the system highways (Fig. 1.3} or a separate
1.4), In both cases the highway capacity used for packet traffic can be shared
among several line cards due 10 Ihe slatistical capabilities of Ihe HSCX.

IO~ 2 in t erfoc e

Figure 1.3: Completely decentral packet switching digital line card ar~ -1ecture,

lis i'laterial By t Respective Manufacturer

 EPIC2 Data Sheet 6/90

The pacMI dala of Ihe D channel are switched to Ihe system highways and processed by the
central packet un~.

In this arch~ecture, Ihe EPIC2 switches the 8 channels from the 10M2 port 16) to the
PCM inteliace, The IDEC works in a master/slave conliQuration, Therefore, an additional colil­
sion resolu1ion line is needed, The IDEC separates siQnaling from data packets, The
messages are translered 10 Ihe uP, which in tum hands them over to the group controller
using the HSCX. The packet dala are processed differenlly, The packet dala and the collision
line can be directly transformed between the IDEC and the PCM highway. The EPIC2 then

JOM2 intprfQC€'> PCM inter-fcc€'> B,P

I .... B ... B.P
systl'r'1
high.Oy
coli
2
i

I
II
~c
s
HSCX
S $;gl"lo 11.1"<;
highwOy

oX!
___ I IDEe I
p
p
coli

1.6: Digilalline card arChitecture for mixed handling a collision highway

simply sw~ches the 8 channels (Fig, 1,6), The packet dala are separated by the IDEC and
placed on Ihe PCM highway, Thus, Ihe full 8 subscriber switching capability of the EPIC2 IS
relalned, '

//

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 EPIC2 Data Sheet 6,90

In an architecture wfth completely central D channel handlin.g 1.4), the EPIC2 SWJ!cnes
Ihe B and D channels and perlonns Ihe CII and monitor channel comrollunctions.

The line card microconlroller programs the EPIC2 and is connected to Ihe group control via a
signalin.g hl9hway and an HSCX, Moreover the EPIC2 controls the layer 1 protocol on Ihe
10M2 interlace, txJf1erir19 the CII and monitor channels to the microprocessor

interface 8.%) p..:...P...::C~M...:.......:..;in.:..;:t=e.:..;r_f_o=c;..:,e,--__ s y s -: E' r1

highwc Y

r---------- Signa l!
highwo y
I;"", c<>rd
co"trol

FIgure 1.4: Digital line card architecture with a completely central 0 channel handling

ISDN-S
,-------,

up to B layer 1 dev.cl?s

FIgure 1.5: Schematic summary 01 the line card

A third possibility is a mixed architecture with central dala and decentral signal hand'
fino. This is a very lIexible archileC1ure which reduces the dynamiC load of central processing
units by evaluatino the signalino intonnation on the line caret For this case, any increase 01
packet data traffiC does nol necessitate any in the architec1ure since the line cards
do not have to be modifiOO. The central packet handlif19 unit can simply be expanded.

For such an architecture, the EPIC2 performs B and 0 channel switchif19 in addition 10 C/I and
monitor channel control. The IDECs handle the data 01 the D channel. These messa,
ges are translerred to the group controller via the and an HOLC controller.

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 EPIC2 Data Sheet 6/90

2. Functional description

In the follOwing chaplers Ihe lunclions 01 the PEB 2056 will be COllered in more detail

2.1. PCM Interface

The PCM interlace formats the data transmitted or received at the 2 PCM They
consist eaCh of one data receive (RxDO,RxD2), a data transmit (TxOO.TxD2) and an outpul
lristale indicalion fine (TSCO,TSC2).

The data rate at the PCM interlace can be programmed to , 536.154.4.

2048,2056.3072.3080,4096 and 4104 kbps. The number of time slOts are 24,32.4.8 and 64 In
Ihe 02-mocIe one additional ck>Cl< after Ihe last lime slOl is introduced. are high
resistance during Ihis time. The length of the first high pulse 01 DCL after FSC is Increased
with one PDC period. The PSR:PSX(2-0) has to be programmed to 11 OB (phase Shift - 0 In
transmit direction).

For the synchronization of the time slot structure a framing signal needs to be connec~ed 10
the EPIC2's PFS pin. The rising 01 signal is evaluated by the EPIC2 during me falling
edge 01 POC as shown in figure 5.9. PFS pulse is of arbitrary However, It must be
ensured that the framing sil;}nal is low for at least the last PDC clock period before me neX'l
lraming pulse. PFS doesn'! have to be provided in eactllrame.

With a bit shift programmed to 0 the 01 the PFS mat1<-s the following bits:

24· time slots: bit7, time slot 23

32 time slots: bit7, time slOt 31

4.8 time slots: bi17. time slOt 47

64 lime slots: bit7, lime SIOI 63

In relation 10 the internal liming pattern. prOlJramming 01 the PSR in connection with the CCR
permits shifting 01 the stal1ing point of the bytes on Ihe receiving and transmining highway in
halt clock steps.

Thus the controller can be adapted to system displacements beI'Neen the receive and
transmit hil;}hways.

The following ligures show the r.',ation of the internal grid and the position 01 the bytes
on the highways. on tne time slot N and the PSR-programming.

If output occurs with Ihe falling of c!()d( (CCR:DCX .. '). the last bit of the data byte will
be cut oft; thereby a reliable nonover1aPPi~ 01 the transmitters is assured. latching 01 data
must take place at a rising edge of the dock.

If an output occurs with the rising of c!()d( (CCR:DCX .. O), this restriction will not be
valid; the data may be lOaded either at iii falling or edge ollhe Clock.

is Material By Its Respective Manufacturer

 EP!C2 Data She1l! 6/90

The lollowing values have 10 be writ1en in Ihe phase register and CAM locations to pertorm a
transfer on the PCM highways in limes lot N with a as given in column 1.

PCMTS Phase Phase reg. I Transmit RecelveCAM

I I
! CAM
I
I

N 0 6 N·2 _N !
N 1 7 N-1.N-2· N I
N 2 0 N-' N i
I
N 3 1 N-f N+1,N"
N I N+l
I
N
N
"5 2
3
N·'
N·'
N-1
N... 1
N ... ,
I

6
N 7 "
5
I N·1 N+1 I

• PCM highway 0,1

This f'laterial By rts Respective Manufacturer

 EPIC2 Data Sheet 6/90

2.2. 10M2 Interface

The 10M2 interface lormals Ihe data transmit1ed or received al the 000 and DUO li{",es It
consists 01 a data downstream (000) and a data upstream line (DUO), a clock output (DCl)
and a synchronization output

The 10M2 interface can handle 6 or 8 subscribers depending on the. data rate being used The
maximum data rate is 2,048 MHz and Ihe maximum Del frequency is 4096 MHz, Please see
chapter 4,1,9 lor delails, Single and dOuble clOd< rate' are supported,

The 10M2 interface contains the following channels lor each subscriber:

- 81

- 92

- D
- Monitor

- 4 or 6 bit CII (In Ihe case of 6 bit CII channel the D channel is reserved)

The rising edge of the synchronization (PFS) is evaluated by Ihe deVice The signal is
evaluated al every ne<,;lallYe source clock (PDq slope,

The framing pulse is 01 arbitrary length. However,rt must be ~nsured thallhe SIgnal IS
low lor at least the last clock period before Ihe nex1 framing pulse, This behaviour and the
pulse shape of Ihe generated Del is shown in figure 2,3 .

The generated FSC is controlled by PSR:FSM, the TIMR register and the CMDR register The
different pulse forms are shown in the figures 2.1 and 2.2 They have a period 01 one flame

II PSA:FSM is programmed 10 log~al1 the TIMA and CMDR registers are evaluated. The TIM R
register defines a in multiples of 125 us (TIMRTVAl(7-{)) ... O:125us) setting
TlMR:TV Al(7-0) - 03H delines a periodol500us equallirlQ 4 frames, Programming CM ORST
• 1 starts the timer, AI every bulthe last frame begin in the predefined period the EPIC2 then
outputs a Iog~<ll 1 during tl1e lime slots 0, 1, 2 and 3, At Ihe last fral"!,le begin a logical 1 is sen!
during the first bit period Of Ihe frame.

This function is repeated unlil the timer is SIOIOOE~ (see 2,6,1).

For a repetition period of 500 us the frame signal is shown in figure 2.2 ,

II PSR:FSM is Pl'09rammed 10 logical 0 the EPIC2 outputs a logical 1 durirlQ the lime slOIS 0,
1, 2 and 3 al each frame begir\.

There is no btl shift lunction of the 10M2 interlace, The edQe 01 Dellollows immediately
aHer the first rising edge of PDC following the laHing 01 PDe tollowing the rising edge 01
PFS,

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 EPIC2 Data Sheet 6/90

The time slot 0 starts with this rising edge 01 Del.

11 CCA:D2 is set to logical 1 the first high pulse 01 DCl is prolonged with one ROC clock

period.

000 can be prCXJrammed as push·pull or open drain (PSR:ODS).

2 J

PSR: rsu-o

Figure 2.1: FSC framing signal signal generation

frame
n I n + 1 In + 2 In + 31" + 4 In + 51 n + 6 In + 7 I n .;­
81

n n n n ~ n n 1
t Timer storted

Flgu.... 2.2: FSC output signal. PSR:FSM .. 1, T1MR ..03H. limer running.

This Material Copyrighted By Its Respective Manufacturer

 EPIC2 Data Sheet 6 /90

There is no slandby operation .

2.3. Memory str~cture and switching

The connection between Ihe 10M2 and PCM inlertaces is set by programming Ine
corresponding CAMs (conlenl adressable memory) by indirect address ing tnrougn tne
microprocessor. There are five CAMs, CAMO-4.

2.3.1. 81 and 82 channel switching.

CAMO to CAM3 consist of 8 bytes, one byte for each subscriber. In order 10 control tne data
transler and time slol ass~nment the lollowing dala byte is entered :

7 o
MS1 MSO TSO-63

MS1 : Mode se lect 1

MSO : Mode se lect 0

TSO-63 : Time slot 0-63 : the desired;time slot is entered here as a binary word.

With MSO and MS 1 tne following CAM operating modes may be set:

MS1 MSO

1 1 No transfer
1 0 Normaltransler, hi9hway 1
0 1 Normal transfer, hiQhway 0
0 0 PCM transfer (CCR :TLP.O)
0 0 Testloop (CCR :TLP.1)

CAMO : 81 channel down time 5101: Tllne slot for Ihe switching of a 54 kbit channel 81
lrom Ihe PCM inlerface 10 lhe 10M2 interface.

CAM1: 82 channel down lime slot: TIme 5101 lor the switching of a 54 kbit channel 82
from the PCM interface to the 10M2 intertace.

CAM2: 81 channel up lime 5101: Tllne slollor Ihe switching of a 54 kbit channel B1 from
lhe 10M2 interface to Ihe PCM interface.

CAM3: 82 channel up lime slot: TIme 5101 lor the switching of a 54 kbil channel B2 from
Ihe 10M2 interface 10 the PCM interface.

This Mat er ia l Copyr i ghted By I ts Respective Manu f ac tu rer

 EPIC2 Oata Sheet 6i90

In normal operation. each lime siot is only once per However, in spec-al
applications it is possible 10 the data contained in a lime sial on Ihe receive highways
10 several subscribers simultaneously; this requires lhe channels to be 01 Ihe same type
81 or channel 82),

If the same lime slot is 10 several subscribers in up direction, Ihe data transmil1ed
will be a bgical AND 01 the according data bytes,

For setup 01 the PCM transfer 64 kbit channels are switched between the highways and the
microprocessor port. CCf1 :TL? has to be O.

The CAM conlen1S have Ihe following

CAMO: Highway 0 down time slot.

CAM 1. Highway 1 down lime slot

CAM2: o up time slot.

CAM3: Highway 1 up time slot.

Normally, the address ot the CAM corresponds to the subscriber number If you want 10

switch a channel lor 1, SA(2-0) (see 4.1.4.) has 10 be sella 001.

If you have prOQrammed 6 subscribers this is true for all channels except lor Ihe subscriber 0

81 channel. For this channel has to be set 10110.

II you want 10 use 4 subscribers, 32 time slots and a PCM data cloCk input (POC) Of 2048
MHz you have 10 do the following:

. Set CCA: CFS (1 :0) to 11.

Supply the PCM frame sync in each frame,

. SA(2-0) (see 4.1.4.) has to be set to 100 for the subscriber 081 channel setup.

The 10M2 data rate will be 1,024 MHz and lhe 10M2 data clod<: Ou1put will be 1.024 MHz

(CCR:DR... OI or 2.048 (CCR:DR .. 1).

The PCM transfer takes place through channel 82 of the corresponding subscriber. If the PCM
transfer is prograllYMd via highway 1 (CAM' and CAM3). enannel 81 of this subscriber can
be If the PCM transfer has been programmed via highway 0 (CAMO
and CAM2) , beth channels will be used. The ISTA:PIN and 1STA;?OV intemJpts will guide you
IhfOUQh the ?CM transfer. .

For setup of Ihe lestloop up 10 8 64 kbit channels are looped back 10 the PCM highway.
CCA:n? has 10 be 1. Two channels have to be prOQrammed. In receive direction the

This Material By Its Respective Manufacturer

 EPIC2 Data Sheet 6/90

prO<Jramming is idenHcal 10 the PCM transfer. In transmit direction Ihe test loop can be
prO<Jramme<! as a PCM or as a normal B2 transfer lor t1'Ie same subscriber as in recel''''€!
direction. No ISTA:PIN or ISTA:POV interrupt will be

2.3.2. 0 channel swl1chlng_

CAM4 consists of 4 bytes, one byte lor four subscnbers. In order to control the data transler
and time slol assignment the fOllowing data is entered:

7 o

MS1. Mode seled1

MSO: Mode seled 0

TSO-63: Time slo\ 0-63: Ihe desire<! time slol is en1ered here as a binary word.

Wllh MSO and MS 1 the fOllowing CAM modes may be set:

CAM4:0: o channel up 0: Time slot for Ihe 01 a byte containing Ihe 16 kbil D

channelS of subscriber 0-3 fromlhe 10M2 interface 10 the PCM interface.

CAM4:1. D channel up ,. Time slol for Ihe switChing of a byte containing Ihe , 6 kbi\ D
channels 01 subscriber 4·7 from Ihe 10M2 interface 10 the PCM inlertace

CAM4:2: D channel down 0: Time slot for the 01 a containing the 16 kbrt D
channels of 0-3 from the PCM interface to the 10M2 lntertace.

CAM4:3: D channel down 1: Time slOI for Ihe switching 01 a byte containing Ihe 16 kbi! D
channels 01 subscriber 4· 7 from the PCM interlace to the' 10M2 Interface.

Thi By Its Respec

 EPIC2 Data Sheet 6190

2.4. Microprocessor interlace

The EPIC2 provides interlaces lor Motorola type and Intel type microprocessors In tl'1e Intel
type uP interlace mode either a multiplexed or a demuttiplexed bus struC1ure may be chosen .

The ALE line of the PES 2056 is used to control the bus struC1ure and interface type. ALE is
fixed to + SV for the Motorola type uP interface and it is switching to signal an address or
data transfer in the ITlJniplexed Intel type uP interface mode. Pins 28 and 29 are interpreted as
AD and WA for a Intel type interface or OS and ANI for a Motorola type interface. Tab .2 2.
summarizes these functions. .

ALE Type Of uP Sus structure pin 28 pin 29

interlace
I
I
fixed to 5V Motorola demutliplexed DS Al'N I
;
Fixed to OV Intel demutliplexed RD WR
switching Intel mutliplexed RD WR
J

Table 2.1: uP interface functions

For indirect accesses the indirect access registers are prOvided . The indirect access add ress
register (IMR) contains the address of an indirect register . the indireC1 access data reg ister
(IADR) the data to be read or written . The duration Of an indirect access is dependant on the
clock frequency. With 32 time slots per frame (2M Hz) an indirect access requires a maximum
of 4us . An indirect access af'Nays requires a maximum of 8 PDC clode. ticks. The follQwlng
procedure should be used for indirect access:

Indirect write access .

1. Wri1.e the data for the ind irect register in the IADA.
2. Wri1.e the register's indirect address in the IMA .
3. Read STAR2 . The tranSfer is concluded for ST AA2 :IAR-1 .

Indirect read access.

,. Write the register's indirect address in the IMA.

2. Read STAA2 . The tranSfer is concllded for STAA2:IAR-O.
3. Read the data of the indireC1 register from the IADR.

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 EPIC2 Data Sheet 6/90

2.5. Preprocessed channels

The EPIC2 supports the

Monitor (M) and

Control (C/I)

channels at the 10M2 interface.

The rronitor handler takes care 01 the rronitor channels. the CII handler 01 the CII ct1annels.

2.5.1. CII channel handler

In upstream direc1ion the signalling handler monito~ the received CII channels . Upon a
change

- an interrupt is generated (ISTA:CFI)

- the address of the specific channel is written into the C/I FIFO
the actual value is stored in r~isters CI_U7..CI_UO .

The two D-<:hannel bits are wrinen to r~isters D_U7 .. D_UO.

Only single last look is carried out. The CII channel is sampled in each Irarne. The Change
detec1ion only operates on the 4 bit CII channel. The CII FIFO is 9 bytes deep and can thus
hold 9 Channels, where the CII information changed. Each entry in this FIFO includes the cav
bit indicating the validity 01 the entry. cav., indicates a valid entry. .

The complete CII FIFO is reset . ie. all cav bits are set to lQ<Jical 0 by instructing the EPtC2 to
reset the C/I FIFO with CMDR :CFR .1.

To turn the CII t1andler active CCR :CFLE has to be set to 1. If CCR:CFLE • 0 the change
detec1ion is halted. but registers CI_U7 ..CI_UO are still written in each Irame.

In downstream direction the value written 10 CI4_7 .. CI4_0 or CI6_7 .. CIS_O will be sent in the
C/I channels in each frame .

2.5.2. Monitor handler

The rronitor handler communicates with the subscriber circuits subject to the 10M2 protocol.
It wonts with active handshake protocol. Each byte exchanged between the EPIC2 and the
subSG~r in lhe monitor channel is internally aulonomously ad<nowledc;led lor a safe
comrnJnication.

The monitor handler only wonts upon it has been instructed with a proper instruction in the
command register.

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 EPIC2 Data Sheet 6/90

The 101i0wil"lQ c:ammands are provided by the EPIC2.

By set1il"lQ CMDR:MSO 10 lo<.;lical1 Ihe EPlC2 starts to look for active monrtor chan·
nels. As soon as an active channel is found the 1STA:MAC interrupt is generated and
the address of this channel is stored in MAIR:SAD(2-0).

The search for an active monrtor channel is stopped. when one such channel has been
found.

The address 01 a found channel may be copied to MSAR:SAD(2:0) for further proces·
sin<;l.
By senin<;l CMDR:MT( 1-0) to lo9ical 01 the EPIC2 starts transmitling the c:anlenl of
MFIFO. When the message has been c:amplelely trans1erred. Ihe 1STA:M FI interrupt is
generated. The group of recipient subscribers is defined by MFAR :MTC(' -0). Program­
mil"lQ these bits wrth
- 00 Ihe messsage is sent to the subscriber with the address specified in

MFAR:SAD(2:0).

- the message is broadcast in all monrtor channels. The monitor by1es are transmit­
ted at maximum speed, i.e. one by1e per three frames. The arriving acknow­
ledgements are ignored.
- 10 the MFIFO content is not transmitted and may instantaneously be read agai (test
operation). The ISTA:MFI interrupt is also generated instantaneously.
For the transmission 01 messages Iol"lQer than 16 by1es the selection CM DRMTp·O) z

'1 is provided. This choice transmits a block of 16 by1es and interrupts the micropro­
cessor lor the next by1es to be writlen to MFIFO (ISTA:MFI, STAR 1:MAE - '.
STARI :MRW .. 0). The last block of such a IoI"1Q message is transmitted setting
CMDR:MT(1-0) 1010 or 01.

SUCh a long message can only be transmitted to a sil"lQle subscriber (MSARMTC( '·0)
'" 00).
Set1ing CMDR:MT(1-0) to 10 an answer 10 the sent message is expected from the
same subscriber. The- MSAR:MTC( 1-0) bits need 10 be fixed 10 00. The message is
stored in MFIFO and as soon as it is complete the ISTA:MFI interrupt is generated.
In all cases the transmitled message consists 01 the MF1FO content prior to the command.

If a message shall be received without transmission (e.g. an activemonrtor channel has been
found) the receive and transmission command is issued with an empty MFIFO.

The STAR' :MAB bit is set, rI the remote partner aborts the reception of an arriving message.

This Material Copyrighted By Its Respective Manufacturer

 EPIC2 Data Sheet 6/90

MSARMTC(1·0).CMDRMT(1·0)

xxOO Inactive.

0001 Transmit with message end.

0010 MFIFO e~ty: receive. MFiFO nol emply: transmit with message end, receive.

0011 Transmit without message end.

0101 Broadcast with message end.

0110 Reserved.

011' Reserved.

1001 Reserved.

1010 Test.

, 011 Reserved.

, , xx Reserved.

2.5.3. 10M2 transfer

The 10M2 transfer uti lily allows the synchronous exchange of information between Ihe 10M2
intenace and the uP interface for one programmable subscriber using B1, 82, D or CII
channels.

The information is buHered In Ihe 81, 62, D or ell indirect registers.

Theese steps should be followed for an 10M2 transfer in the up and down directions

Set ITCR:ION to 1. ITCR:SAD(2:0) defines the used subscriber.

The ISTA:JlN occurs aller the oontents of Ihe subsciber have been
sent or received on Ihe 10M2 highway. The interrupt disappears when 1STA is read.
The bytes can be written 10 or read from Ihe subscriber
the previous two sleps for each byte.
SeIITCR:ION 10 0 when ISTA:IIN has occurred for the last byte.
If a byte is sent or received twice before ITCR is written the ISTA:10V interrupt occurs
The interrupt disappears when 1STA is reac!.
ITCR:bi14 should be set to logical, each time ITCR is written.

Material By Its Respect t"lanufacturer

 EPIC2 Data Sheet 6190

2.5.4. PCM transfer

Tl}e PCM transfer utility allows Ihe synchronous exchange 01 information between the PCM
intet1ace and the uP intenace lor one TS channel in Ihe up direction and one TS channel in the
down direction.

The information is buffered in Ihe 82 indirect registers.

Theese steps should be followed for an ?eM transfer in Ihe up directIOn:

Write the chosen 82 up register.

Program the ?eM transler in Ihe CAM (see chapter 2.3 lor details}.

The ISTA:PIN interrupt occurs aNer Ihe conlents of the B2 up register has been sent on

the PCM highway. The interrupt disappears when ISTA is read. The next can be

written to the 82 up register. VNSR:PDIR is logical 0

Repeat the previous slep for each byte.

Wait for Ihe lastISTA:PIN interrupt and program "no transfer" in Ihe CAM.

Read 1STA 10 clear interrupts.

II a byte is sent twice without having been chal1Qed by the microprocessor Ihe

ISTA:PIN and 1M 1STA:POV interrupts occur. The interrupts disappear when 1STA IS

read.

Theese sleps should be fOllowed for an PCM transfer in the down direction:

Program the PCM transfer in the CAM.

The ISTA:PIN interrupt occurs atter the byte received on the PCM highway has been

entered to the 82 down VNSR: PDIR is logiCal 1 . The interrupt disappears

when ISTA is read. The can be read from Ihe mu::roorClCe

Repeal the previous step lor each byte.

Program "no transfer" in the CAM.

Read 1STA to clear

If a byle is received twice without having been read by the the

ISTA:PIN and the ISTA:POV interrupts occur. The interrupts disappear when 1STA IS

read.

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 EPIC2 Data Sheet 6/90

2.6. Special functions

2.6.1. Hardwarellmer

The EPIC2 provides a hardware timer CQntinously interrupting the uP aNer programmable lime
The timer period is selected by programming TIMR:TVAl(7·0j. It's value is gl\len there
in multiples of 125 us. Programming e.g. TV AL(7 ·0) with 07H gives a timer period of , ms. The
timer is started by CMOR :ST to 1. Now the EPIC2 generates a interrupt each
time the timer expires. stop Ihe interrupt generation you can set MASK:TIN to logical'.

Besides this Interrupt generation Ihe timer is used lor generating a proper 10M2 mutliframe
synchronlzation signal.

For both applications the period is equal. The limer is slopped by writing TlMA.

I I

t
Timer stort TIN TIN Timer stop
multifr. synch mul tifr. synch

Figure 2.4: of the timer function

Thi Material By Its Respective Manufacturer

 EPIC2 Data Sheet 6/90

2.6. Special functions

2.6.1. Hardwaretlmer

The EPIC2 provides a hardware limer c.;)ntinously interrupHng the uP after programmable time
periods. The timer period is selected by programming T1MR:TVAL(7·0). It's value is gillen there
in multiples 01125 us. Programming e.g. TVAL(7·0) with 07H a timer 011 ms. The
limer is started by setting CMDR:ST 10 logical 1 Now the generates a inlerrup! each
lime the timer expires. To stop the interrupt generation you can set MASK:T1N to logICal'.

Besides this interrupl generation Ihe timer is used for generating a proper 10M2 multiframe
synchronization

For both apt;lIlc;:am:ms the period is equal. The timer is $lopped by wrrting TIMR

Timer start TlN TlN Timer stop

multifr. synch mul ti fr. synch

FIgura 2.4: ollhe timer function

This 1>1aterial By Its :v1anufacturer