Section 1: The intrinsic common-source MOS gain

stage.

In order to clearly introduce the fundamentals, originality and potential of our analog design
methodology, as well as its requirements, this first chapter will focus on an elementary case of
study, i.e. the synthesis of the intrinsic MOS common-source gain stage. This nevertheless
practical example will enable a complete illustration of the four main aspects combined in our
approach:
- the opamp synthesis technique based on the transconductance-to-drain current ratio of the
MOS transistor;
- the need for the continuous functional modelling of the analog transistor characteristics used in
our methodology;
- the derivation of a small-signal analytical model of the amplifier performance from a so-called
symbolic analysis;
- the MATLAB implementation of the MOSFET and amplifier functional models, whose
adequacy and potential regarding our purpose will be discussed.

The first part will present the study case and the classical methodology usually followed to
solve the problem. In the second part, we will introduce our systematical approach based on
behavioral analysis, gm/ID concept and continuous modelling. Extended design analyses which
can hardly be implemented in SPICE-based approaches will stress the interest of our
methodology. Practical MATLAB implementations will support our discussion [MATLAB].

1.1. Classical approach.

The intrinsic common-source MOS gain stage is an elementary amplifier consisting in a

MOS transistor in common-source configuration, biased by an ideal current source and loaded
by an output capacitor (Fig. 1.1). The major specifications of this stage are:
- the low-frequency amplification gain between input and output nodes, noted Av0,
- the transition or unity-gain frequency, noted fT,
- and the external load capacitor CL.
The main unknowns are:
- the active MOSFET size, in terms of the width over length ratio, noted W / L,
- and the stage bias current ID0.
In addition, the gate and drain saturation voltages are also of interest in order to evaluate the
input and output dynamic swing performance.

-1-
 ID0

Vout
Vin

CL

Fig. 1.1: MOS common-source intrinsic gain stage.

The standard methodology which is used to link the specifications to the unknowns lies on
an approximated intuitive physical approach of the problem [Laker '94]. The first step is to
derive the equations which characterize the circuit behaviour and performance by circuit
inspection. An expert designer will directly link the low-frequency amplifier gain to the ratio of
the circuit equivalent input transconductance to output conductance and relate the poles of the
transfer function to the circuit capacitive nodes. In our study case, we may then straightforwardly
write:

g gm
A v0 = m (1.1) and fT = (1.2),
gd 2.π.C L
where gm and gd are the transconductance and output conductance of the active MOS transistor,
respectively.

In order to determine the problem unknowns, simplified expressions of the small-signal

MOS electrical parameters are commonly used. In the saturation strong inversion regime, we
have:

2.µ.C ox . W. I D ID
gm = (1.3) and gd = (1.4),
n. L V eal .L
where ID is the MOSFET drain current and n, µ, Cox and Veal are technological parameters
fixed by the MOS fabrication process, named the linearised body effect, the inversion-layer
minority carrier mobility, the gate oxide capacitance per unit area and the equivalent Early voltage
per µm of width of the MOS transistor, respectively. From (1.2) and (1.3), we derive a direct
relation between the device sizing and the drain current equalled to ID0, for given transition
frequency and technology specifications:

2
W = n. ( 2. π. f T .C L ) (1.5).
L 2.µ.C ox . I D0

-2-
 A numerical and graphical illustration of this first design approach can be implemented on
MATLAB by the two following files given here for the sake of illustration only; 'ex1.m' executes
equation (1.5), including the physical and technological parameters defined in 'param.m'.

% 'ex1.m' EXAMPLE 1
% Common-source intrinsic MOS gain stage synthesis
% by approximated strong inversion intuitive approach
clear

load parameters % load variables from 'parameters.mat'

% common source specifications

fT = 10e6; % transition frequency [Hz]
CL = 10e-12; % load capacitance [F]

%s.i.
ID0 = logspace(-5,-3,50);
WsLsi = (2*pi*fT*CL)^2/2/Kn./ID0*n;

% plot
semilogx(ID0,WsLsi,'-')
axis('square'); axis([1e-5 1e-3 0 300]);
title ('Fig. 1.2: Strong inversion synthesis')
xlabel ('Bias current ID0 [A]')
ylabel ('Width/length ratio W/L [-]')

% 'param.m' PARAMETER DEFINITIONS

% physical constants
T = 300; % temperature [K]
UT0 = .0259; % thermal voltage (300°K) [V]
epsOx = .345e-10; % permittivity of oxide [F/m]

% technology (canal N)
tox = 30e-9; % gate oxide thickness [m]
Cox = epsOx/tox; % gate oxide capacitance [F/m2]
Lmin = 2; % minimum channel length [µm]
n = 1.35; % body effect factor [V/V]
VTo = 0.7; % threshold voltage [V]
µ = 550e-4; % effective mobility [V2/cm.s]
Veal = 8; % Early voltage [V/µm]
Kn = µ*Cox;

save parameters T UT0 epsOx tox Cox Lmin n VTo µ Veal Kn

% create file 'parameters.mat'

-3-
 Fig. 1.2: Strong inversion synthesis Fig. 1.3: Strong inversion synthesis
300 60

DC open-loop gain [dB]

Width/length ratio W/L [-]

200 40

100 20

0 -5 0 -5
10 10-4 10-3 10 10-4 10-3
Bias current ID0 [A] Bias current ID0 [A]

One can note that this first MATLAB example already takes advantage of direct matrix
formulation. For example, the implementation of equation (1.5) only requires a single line for a
large set of bias currents uniformly spread on a log scale. Figure 1.2 depicts the locus of (W/L,
ID0) pairs achieving the target specification, here 10 MHz. The selection of a particular solution
within this large acceptable set must be based on further criteria, for example, the dc open-loop
gain. This can be straightforwardly derived from equations (1.1) and (1.4) if the device length is
fixed. The optimal length determination lying beyond the scope of the present preliminary study,
our example will use a length equal to the minimum channel length of the technology (Fig. 1.3):

% EXAMPLE 1 - cont.
Av0 = 20*log10((2*pi*fT*Cout)./(ID0/(Veal*Lmin)));
semilogx(ID0,Av0,'-')
axis('square'); axis([1e-5 1e-3 0 60]);
title ('Fig. 1.3: Strong inversion synthesis')
xlabel ('Bias current ID0 [A]')
ylabel ('DC open-loop gain [dB]')

The exact numerical result corresponding to a given gain is obtained by interpolation of the
solution tables using a predefined MATLAB spline function:

% EXEMPLE 1 - cont
[spline(Av0,ID0,50),spline(Av0,WsLsi,50)]

For example, for Av0 = 50 dB with L = 2 µm, we find ID0 = 32 µA and W/L = 132.

-4-
 The computation can be easily restarted for other specifications, for example, fT = 100 kHz
(Fig. 1.4). This clearly shows that allowable solutions spread over orders of magnitude which
can make the initial guess quite uneasy, as announced in the introduction. In the present
elementary case, this difficulty is examplified by the a priori choice of the ID0 range which
depends on the fT specification.

Fig. 1.4: Strong inversion synthesis: fT = 100 kHz

300 100

DC open-loop gain [dB]

Width/length ratio W/L [-]

200

50

100

0 -9 0 -9
10 10-8 10-7 10 10-8 10-7
Bias current ID0 [A] Bias current ID0 [A]

It is not easy, nor efficient, to try to perform even such a basic analog synthesis using
conventional SPICE-like softwares. The latters are indeed analysis tools, not synthesis. Any
SPICE simulation starts by specifying the device terminal voltages, width and length which are
in fact the unknowns of our problem. Moreover these unknowns may not be independently
chosen. For example, when describing in SPICE the circuit of figure 1.1, the value of the ideal
bias current source must exactly match the DC current flowing through the transistor as
computed using the SPICE MOS model, terminal voltages and sizes, otherwise the DC
operating point can not even be established and any further AC or transient simulation run. An
AC simulation is yet required to compute the complete frequency response of the amplifier from
which the low-frequency open-loop gain and transition frequency are eventually extracted. It is
obvious that all the SPICE analysis flow, i.e. firstly establishing a DC operating point, then
running an AC simulation, must be iterated, varying both device biases and sizes, until the
computed Av0 and fT converge towards the specification. Such a synthesis procedure is
cumbersome, even using an automatic optimizer software since the initial point still has to be
guessed adequatly.

-5-
1.2. Systematical approach.

In practical complex opamp architectures, the derivation of the small-signal equivalent

circuit and performance equations will not be as trivial as in the present case and it will be useful
to identify the degrees of freedom of the problem as well as initial guess values. A systematical
approach is therefore preferable.

The systematical approach we propose here, as the physical approach, starts with a
behavioural analysis of the analog circuit at the symbolic level, with the aim to establish
unambiguous relationships between the application target specifications and the unknown
electrical parameters of the circuit. The accuracy of this analysis is of major importance to
ensure the quality of the subsequent synthesis. Therefore, on the contrary to standard
approaches, we will not rely on an approximated intuitive analysis of the topology, nor on
simplified MOSFET models.
On one hand, a complete circuit analysis will systematically be attempted. Depending on the
target performance, small-signal as well as large-signal analyses may be required: small-signal
for performance such as gain, transition frequency, stability…, large-signal for slew rate,
distortion… ISAAC is one of the few softwares dealing with the small-signal symbolic
simulation of complex architectures [Gielen '89]. Concerning the large-signal case, more
complex since often non linear, several theoretical research works are underway with the aim to
develop efficient analysis softwares.
On the other hand, we will use a precise modelling of analog characteristics of MOS
transistors. The EKV model originally developed at the EPFL in Lausanne presently appears as
the best suited model for opamp design, combining physical accuracy with equation simplicity
[Enz '95].

1.2.1. Behavioural analysis.

The systematical investigation of the elementary common-source MOS gain stage starts
with the derivation of its behavioural model which restricts here to the analysis of the small-
signal equivalent circuit (Fig. 1.5). In addition to already defined gm, gd and CL elements, we
consider the gate-to-source, gate-to-drain and gate-to-substrate capacitances of the MOS
transistors, noted Cgs, Cgd and Cgb, respectively.

vin vout
Cgd

Cgs+Cgb gm .vin gd CL
Fig. 1.5 : Small signal equivalent circuit of the common-source MOS stage.

-6-
 The input-output transfer function Av(s) = vout / vin can obtained running ISAAC or, in
such a simple case, by direct derivation of the Kirchoff equations:

s.C gd − g m
A v (s) = (1.6).
(
s. C L + C gd + g d )
We verify that at low frequency, Av tends to the dc open-loop gain previously given by
(1.1) and that neglecting Cgd, the denominator of Av yields a single pole p1 in agreement with
the unity-gain transition frequency fT given by (1.2):

−g d
p1 = (1.7).
2.π.(C L + C gd )

Furthermore, the Av numerator features a zero, z1, associated with direct input-output transfer
through Cgd capacitor,

gm
z1 = (1.8).
2.π.C gd

In a first step, we will neglect both Cgd and z1, so that to be able to compare the results of
the previous approach with the results we will compute now introducing the EKV model.

1.2.2. gm/ID concept and EKV model.

The usefulness of EKV model can be conveniently introduced in combination with our
design methodology based on the transconductance-to-drain current or gm/ID ratio. For that
sake,

a) the behavioural equations can be easily reformulated to emphasize the gm/ID terminology.
Equations (1.1) and (1.2) are thus written:

g g I
A v0 = m .V eal .L (1.9) and f T = m . D0 (1.10).
ID I D 2.π.C L

b) the EKV model provides a simple expression for the gm/ID ratio of the MOS transistor in the
saturation regime. This formula is precise and continuous throughout the weak, moderate and
strong inversion regimes:

(− IC )
1 (1 − e
gm / ID = . (1.11),
n. U T IC

where UT is the thermal potential equal to 26 mV at room temperature and IC, named the
inversion coefficient, is an adimensional number, lower than 1 in weak inversion and higher than
1 in strong inversion. IC is linked to the drain current by:

-7-
 ID
IC = (1.12).
2
2. n. µ.C ox . W . U T
L

The quality of this empirical gm/ID modelling is demonstrated on figure 1.6 by the
excellent agreement with an experimental characteristic measured on a typical MOS transistor.

30
25
gm/ID [1/V]

20
15
10
measurement
5 EKV model

0-10 -8 -6 -4
log of Drain Current / (W/L) [A]
Fig. 1.6: Transconductance-over-drain current ratio vs normalized drain current.

c) relations (1.11-1.12) clearly show that the gm/ID characteristics as a function of the
normalized current I' = ID/(W/L) only depends on the technological parameters, not on the exact
transistor dimensions. It thus constitutes a universal characteristic common to all transistors of
similar type, i.e. nMOS or pMOS, realized in a given fabrication process.
In all the following MATLAB examples, this characteristic will be implemented as a matrix
table of gm/ID values associated to I' values, i.e. [[gm/ID],[I']], calculated using the EKV model.
From figure 1.6, we may also deduce that, in a given technology, the model can be substituted by
a table derived from experimental characteristics without any loss of generality. Such an
experimental look-up table modelling may prove extremely efficient in practical cases of special
operating conditions or devices for which reliable models are not available.

d) consequently, the gm/ID analog parameter turns out to be the key parameter for the synthesis
of MOS operational amplifiers.
The gm/ID formulation of the behavioural symbolic opamp equations allows to eliminate,
from these expressions, an unknown of the problem which is difficult to a priori estimate, i.e.
W/L, whereas gm/ID values always fall within a limited range of well-known values. The MOS
transistor physics constraints gm/ID between 0 and 38 V-1 at room temperature. Practically, the
maximum value hardly excess 25 V-1 for conventional bulk Si MOSFETs.
Furthermore, a clear link exists between the gm/ID ratio and the major analog device
performance. This ratio intuitively conditions the efficiency of the transistor, on one hand, to
amplify a signal and on the other hand, to transform static current into dynamic
transconductance and hence gain-bandwidth product for a given power consumption. In practical
cases, acceptable gm/ID values will often be constrained by the specifications. It proves to be an
unknown for which initial guess values may be conveniently chosen, thereby reducing the

-8-
number of degrees of freedom in a complex system and allowing its iterative optimization if
necessary.
Finally, since gm/ID does not depend on the a priori unknown dimensions of the transistor,
but is unambiguously linked to the adimensional current I' = ID/(W/L), the evaluation of the bias
current and of the gm/ID univoquely imposes the W/L aspect size.

e) a top-down synthesis methodology eventually emerges, starting from the specifications to

deduce the problem unknowns in a logical way.

The formulation of a design flow plan or synthesis algorithm for our simple common-
source example clarifies these different concepts (Fig. 1.7):

gm
Av0 I D /(W/L)
ID

fT gm I D0 (W/L)

Fig. 1.7: Design flow plan for the common-source MOS gain stage.

1° equation (1.2) directly yields gm from the given transition frequency and capacitive load,
while gm/ID is derived from the specified dc open-loop gain and the chosen technology using
equation (1.9);
2° gm and gm/ID yield the bias current ID0 and furthermore gm/ID gives I' by equation (1.11-
1.12);
3° W/L is finally given by ID0/I'.

This approach proves to be deductive or top-down. The MATLAB implementation is given

hereafter for sake of illustration. The technological [[gm/ID],[I']] table is obtained from an
external EKV routine given in Annex. For each of these pairs, the gain is computed considering
minimal channel length and a related [[W/L],[ID0]] locus is obtained.

Numerically we obtain a W/L aspect ratio which in this case significantly differs for the
result of the approximated strong inversion synthesis, for the same gain and transition frequency
specifications, i.e. for 50 dB and 10 MHz respectively, we get W/L = 444.

To explain this result, we compare in figure 1.7, the locus of acceptable (W/L,ID0) pairs for
a given transition frequency as well as the gm/ID vs I' characteristics used in both approaches.

-9-
% 'ex2.m' EXAMPLE 2
% Common-source intrinsic MOS gain stage synthesis
% for a given dc open-loop gain using the top-down approach
% based on gm/ID and EKV model
clear

load parameters

% common source specifications

fT = 10e6; % transition frequency [Hz]
CL = 10e-12; % load capacitance [F]
Av0 = 50; % dc open-loop gain [dB]

% gm/ID vs I' table in saturation from EKV model

VS = 0; VD = 2.5; VG = 0.2 : .05 : 2.5;
m = ekv([n VTo UT0],VS,VD,VG);
Iprim = m(:,2)*Kn;
GmoverId = m(:,3);

% design flow
gm = 2*pi*fT*CL;
gmonID = (10^(Av0/20))/(Veal*Lmin);
ID0 = gm/gmonID;
Ip = spline(GmoverId,Iprim,gmonID);
WovrL = ID0/Ip

% EXAMPLE 2 - cont.

% ekv vs s.i.
ID0si = logspace(-5,-3,50);
WsLsi = gm^2/2/Kn./ID0si*n;

WsLekv = (GmoverId.*Iprim).^(-1)*gm;
ID0ekv = Iprim.*WsLekv;

% plot
subplot(121);
semilogx(ID0si,WsLsi,'--',ID0ekv,WsLekv,'-')
axis('square'); axis([1e-5 1e-3 0 300]);
xlabel ('Bias current ID0 [A]')
ylabel ('Width/length ratio W/L [-]')
title ('Fig. 1.7: Strong inversion (--) vs EKV (__) syntheses')

subplot(122);
semilogx(ID0si./WsLsi,gm./ID0si,'--',Iprim,GmoverId,'-')
axis('square'); axis([1e-10 1e-5 0 30]);
xlabel ('Normalized current I`=ID0/(W/L) [A]')
ylabel ('gm/ID [V-1]')

subplot(111);

- 10 -
 Fig. 1.7: Strong inversion (--) vs EKV (__) syntheses
300 30
Width/length ratio W/L [-]

200 20

gm/ID [V-1]
100 10

0 -5 0
10 10-4 10-3 10-10 10-5
Bias current ID0 [A] Normalized current I`=ID0/(W/L) [A]

The MATLAB implementation clearly illustrated the top-down property of the systematical
approach when compared to the strong inversion one. The latter requires the a priori knowledge
of the adequate bias current range which depends on fT, whereas the gm/ID approach is general
to any specification. The two graphs highlight the discrepancy between the results of the two
synthesis approaches (Fig. 1.7). The strong inversion model dramatically overestimates the
gm/ID values for low normalized current, i.e. when the strong inversion regime obviously gives
way to moderate or even weak inversion for which the model does not apply. Subsequently, in
our study case, the common-source amplifier is synthesized for a specified gain, and hence
gm/ID, with a much higher normalized current when using the strong inversion approach, which
results for a given fT, and hence gm and ID0, in a much lower W/L aspect ratio.
In our numerical example, a 50 dB gain was achieved with gm/ID and L equal to 20 V-1
and 2 µm respectively. We easily verify that this gm/ID value lies in moderate inversion yielding
an identical difference factor of 3 between the two model results for both the normalized current
and W/L. Solutions from the strong inversion approach do not correspond to any physical
reality for gm/ID values larger than 10, which drastically limits the validity of this approach.
Furthermore, we observe that the strong inversion gm/ID model tends to infinite values for low
currents, whereas physically, in weak inversion, gm/ID reaches a plateau maximum value. This
significates that, for a given fT, and hence gm, there exists a minimal current value under which
the frequency specification can not be achieved. The EKV-based design approach clearly shows
that limit, annihilating the illusion for achieving indefinitely low power consumption through
device size increase.

- 11 -
 Next chapters will discuss into further details the potential and limitations of different MOS
models and their implications on analog circuit design, as well as the application of our synthesis
methodology to more practical amplifier design cases.

1.2.3. Extended analyses.

We will now investigate two typical extended analyses of the basic common-source design
case which can be run in reasonable computation time thanks to the combination of gm/ID
methodology, EKV model and MATLAB environment. Such analyses can on the contrary
hardly be implemented in SPICE-based approaches. These two syntheses incorporate and
illustrate various limitations of the architecture which were previously neglected.

We must first consider that the total capacitive load does not reduce to the external load CL,
but also includes the intrinsic device load related to the drain-to-substrate capacitance Cdb. The
latter adds to CL in parallel and is proportional to the device width:

C db ≈ C jbx .W (1.13)

where Cjbx denotes the drain-to-substrate junction capacitance per unit of device width.
The total load charge is then given by Cout = CL+Cdb which changes the amplifier
transition frequency achieved for a given gm. The influence of the transistor size on Cout should
therefore be taken into account during the synthesis, either directly when determining W, or a
posteriori, recomputing fT, verifying the specification and adapting the sizing if required. In both
cases, a coupled equation system should be solved by iterations or by another numerical method.
Several predefined MATLAB functions could serve this purpose. By simplicity, we will only
consider here the a posteriori recomputation of the gain-bandwidth product we will note GBW
and compare to the initial fT specification for reasons to be discussed later:

gm
GBW = (1.14).
2.π.Cout

Secondly, the zero of the extended transfer function given by eq. (1.6) depends on the gate-
to-drain MOSFET capacitance Cgd (Fig. 1.5). This has two components, a physical one
resulting from the technological overlap of the gate and diffused drain region and another linked
to the variations of the internal MOSFET charges with the terminal voltages. The latter is one of
the so-called intrinsic MOSFET capacitances which model small-signal dynamic effects taking
place within the MOSFET structure. Their modelling is rather complex and thus beyond the
scope of this introductive chapter. It is however a very important topic which will be more
extensively covered in section 3 of this course. As a first approximation, but without any loss of
generality, we will only model here the overlap capacitance component as follows:

C gd ≈ C rec .W (1.15)

where Crec is the overlap capacitance per unit of MOSFET width.

a) Pole-zero analysis, transfer function, phase margin and settling time.

- 12 -
 In this first extended analysis of the common-source stage, we will further investigate its
poles and zeros, transfer function, phase margin and settling time performance as a function of
gm/ID, incorporating the previously neglected output and overlap capacitances.

The 'ex3.m' MATLAB file given in Annex illustrates and compares the computation of the
pole-zero locus either numerically from the implementation of the complete transfer function,
here given by eq. (1.6), or analytically from the derivation of the symbolic pole and zero
expressions, here given in eq. (1.7-1.8). Such an analysis is an important preliminary step
towards a systematic synthesis approach as demonstrated in chapter 5.

Figure 1.8 clearly illustrates the here obvious agreement between the numerical (lines) and
analytical (symbols) pole-zero loci, as well as for practical gm/ID values, the negligible impact of
Cdb on the transition frequency specification (i.e. fT = 10 MHz) and the very high-frequency
position of the zero, which validates our previous approximated synthesis. For gm/ID values
larger than 20, Cdb and, hence, Cout significantly rise with the increase of W, thereby reducing
GBW for fixed gm.

Fig. 1.8: Pole-zero locus and GBW for fixed gm = fT.CL

30

25

20
gm/ID [V-1]

15

10

0 4 6 8 10
10 10 10 10
p1 (+,--), GBW (-), z1 (o,-.) [Hz]

- 13 -
 We will now verify, using the bode diagram plot of the Av(s) transfer function that the
variation of the pole position with gm/ID for fixed fT obviously correlates with an increase of
the dc open-loop gain. Two gm/ID values are chosen for sake of comparison, with gm/ID = 20
V-1 corresponding to our gain specification of 50 dB and gm/ID = 5 corresponding to a strong
inversion case. The transfer function calculations may conveniently be implemented in
MATLAB, as given in Annex.

Fig. 1.9: Bode diagram: gm/ID = 20 (_), 5 (- -)

40
Magnitude [dB]

20

-20

-40 4 6 8 10
10 10 10 10
Frequency [Hz]

200
Phase [°]

100

0 4 6 8 10
10 10 10 10
Frequency [Hz]

In both cases of figure 1.9, we may observe that

- on one hand, the transition frequency recomputed in Av(s) = 1 or 0 dB is less than a few
% away from the initial specification (i.e. fT = 10 MHz) and very close to the GBW estimated
from gm and Cout by eq. (1.14),
- and, on the other hand, the phase margin between -180° and the transfer function phase
value at the transition frequency, which guarantees stability in closed loop, keeps close to ideal,
i.e. 90°.
This justifies the simplifying assumption of a first-order system for which fT is also equal
to the gain-bandwidth product GBW given by the dc open-loop gain times the dominant pole
frequency, which does not hold for higher order systems. We may further verify the system
stability in closed loop by calculating the temporal response to an input step voltage. The
MATLAB implementation is given in Annex. When observing the input and output signals in a
linear scale diagram like on an oscilloscope, the two gm/ID cases may not be discriminated.
Since they have almost identical fT values, they present similar exponential behaviour towards
the final value. A log scale representation of the error signal, i.e. the difference between input and

- 14 -
output values refered to input, more conveniently shows the direct influence of the dc open-loop
gain on the final error in closed loop as expected from linear circuit theory (Fig. 1.10). The
settling time of the output signal to a few % of the input step can easily be extracted.

Fig. 1.10: Step response error : gm/ID = 20 (_) and 5 (--)

0

-5

-10
20.log10((Vin-Vout)/Vin) [dB]

-15

-20

-25

-30

-35

-40

-45

-50
0 0.5 1 1.5 2
Time [s] x 10-7

b) Analysis of maximum transition frequency for a given gain.

The following important analysis illustrates a fundamental limitation of any amplifier

architecture in a given technology, i.e. for a given dc open-loop gain and hence fixed gm/ID, the
transition frequency may not be indefinetely raised by increasing the bias current. The reason is
that increased bias current implies larger transistor width and hence, larger intrinsic drain load
capacitance. When the latter dominates the total output load capacitance, it impairs any fT
increase from larger transistor and size. The 'ex4.m' MATLAB file given in Annex implements
such phenomenon, in our basic common-source stage design case, for the two gm/ID values
previously considered. It should be noted that SPICE-like electrical simulation softwares hardly
enable such analyses again.

- 15 -
 Fig. 1.11: Maximum transition frequency
9
10

gm/ID=5

108
GBW product [Hz]

gm/ID=20

107

106 -5 0
10 10
Bias current ID0 [A]

The results are clearly illustrated in Figure 1.11: a larger gm/ID yields a lower current
consumption for a targeted fT, provided the latter is not too high, whereas lower gm/ID achieves
higher fT, but reducing the gain. This is a very important general conclusion: any amplifier
architecture has its own fundamental performance limitations whose exact values depend on
technology. Although it is clear that such limitations can not be exceeded, this is not so obvious
when blindly using automated optimisation softwares based on SPICE. These ignore basic
physical limitations and will just not reach convergence for unpractical specifications, leaving the
designer without any valuable information.

Figure 1.11 also shows that our basic amplifier can, in theory, achieve fairly high frequency
performance. For simple it is, the basic common-source stage has therefore numerous practical
applications, in particular in the range of very high frequencies for which the intrinsic stability
provided by its first-order behaviour is a must. However the transition frequency can not be
indefinetely increased by lowering gm/ID because another physical limit will be reached, i.e. the
transit time of the carriers in the channel which depend on the device length and other
technological parameters. Nevertheless, this time constant can also be expressed as a function of
gm/ID [Enz '95] and therefrom easily incorporated in our approach. This once more justifies the
need for accurate and reliable device modelling as well as systematic amplifier performance
evaluation.

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1.3. Conclusion.

At this point, our systematical design methodology may be summarized as follows.

We have demonstrated that a basic opamp synthesis can be based on functional models of
both opamp and transistor behaviours, thereby reducing a large number of technological and
architectural parameters to a limited set of key electrical performances.

Analytical expressions relating circuit specifications to electrical device parameters are first
derived using symbolic analysis techniques. The original re-formulation of these relations using
the universal gm/ID vs I' characteristics eases the identification of the degrees of freedom of the
problem. Some of them can be conveniently fixed by the limited range of gm/ID values in order
to reduce the problem complexity. A design plan or synthesis algorithm may therefrom be
established, incorporating the technological data. The problem unknowns are thus finally
obtained from a top-down synthesis.

The implementation of our methodology requires the use of models or experimental data
describing the major analog MOS parameters continuously from weak to strong inversion, in
order to guarantee the reliability of the synthesis results. These parameters are, to the first order,
as presented here, the gm/ID vs I' characteristics, as well as the Early voltage and the intrinsic
device capacitances. In chapter 3, their extended formalization will be detailed.

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References

[Enz '95] C. Enz, F. Krummenacher and E.A. Vittoz, "An analytical MOS transistor model valid in all
regions of operation and dedicated to low-woltage and low-current applications", Analog
Integrated Circuit and Signal Processing, vol. 8, n°1, pp. 83-114, 1995.

[Gielen '89] G.G.E. Gielen, H.C.C. Walscharts and W.M.C. Sansen, "ISAAC: A symbolic simulator for
analog integrated circuits, IEEE Journal of Solid-State Circuits, vol. 24, pp. 1587-1597, Dec.
1989.

[Laker'94] K. Laker, W. Sansen, Design of analog integrated circuits and systems, Mc Graw-Hill, 1994.

[MATLAB] MATLAB 4.2.c, The Mathworks, Inc. (Natick MA, USA).

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