EE 335 : Advanced Microprocessor

Chapter-5
Logic Design with Behavioral Models of
Combinational and Sequential Logic

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Ajay Kumar Yadav
Ajay Kumar Yadav
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Kumar College of Engineering

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Electrical & Computer Engineering
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Date: 2003.10.28 Temple University
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Data Types for Behavioral Modeling:

Data types are classified in two categories:

„ Nets (wire) : establish connectivity between
design objects.
„ Register (reg) : similar to variable in ordinary
procedural language, stores the information
while the program executes.
„ Integer : word length depends on the type of
computer.
 Nets:
Net Types
wire Establish connectivity, No Logical behavior or
functionality implied.
tri Establish Connectivity like wire, used to indicate
three stated in hardware.
wand Connected to the output of multiple primitives,
implementation of wired AND.
wor Connected to the output of multiple primitives,
implementation of wired OR.
Register Variables:
„ reg : hardware storage element. Default size is single bit
and default value is “x”.
„ integer: supports numeric computation in procedural
statements. Word length depends upon the host
machine. Default initial value is “0”. Assigned value
must be decimal equivalent.
„ real: A 64 bit value stored in double precision. Default
initial value is “0.0”. $realtobits and $bitstoreal syntax
are used to convert data types to permit real data
transfer.
„ Constants: A constant is declared with the keyword
parameter. Constant can be a integer, real number or
reg type.
Two Dimensional Array:

reg [31:0] memory [0:256]

Word size Memory size

User Defined Name

Two channel Mux with 32-bit Datapath:
Propagation Delay & Continuous
Assignments:
Verilog Counterparts:
Logic Verilog
Description Description

Circuit Structural
Schematic Model

User-Defined
Truth Table
Primitives

Boolean Continuous
Equations Assignments
Cyclic Behavioral Models:
„ Model edge sensitive functionality (e.g. posedge or
negedge of clock).
„ Cyclic Behavior is abstract – do not use hardware to
specify signal values.
„ Do not expire after the execution of last procedural
statements.
„ Execution can be unconditional or can be governed by
an optional event control expression.
„ Capable of modeling both edge sensitive and level
sensitive behavior.

Continuous-assignment statement are limited to level sensitive modeling

Cyclic Behavior & Edge Detection:
„ Always activate at the beginning of the simulation.
„ Delay control operator and event control operator
control the execution.(#,@)
„ posedge and negedge are the two event control expressions
used for rising edge and falling edge respectively.
„ After a complete execution of cyclic behavior, the
computational activity flow return to the always
keyword.
„ If a procedural statement has both delay and event
control expression, the activity will wait for the
indicated time and then test for event control
expression.
Continuous-Assignment Models:

A A_gt_B
Compare_32 A_lt_B
B A_eq_B

module compare_32 (A_gt_B, A_lt_B, A_eq_B, A, B) ;

parameter size=32 ;
input [size-1:0] A, B;
output A_gt_B, A_lt_B, A_eq_B ;

assign A_gt_B = (A>B),

A_lt_B= (A<B),
A_eq_B = (A==B) ;

endmodule
Dataflow/RTL Models:
„ Describes concurrent operations on signals in a
sequential machine.
„ The computations are initiated at the active edge
of clk and completed in a time to be stored in a
register at the next active edge.
„ RTL model are written for a specific architecture
:that is, the registers, data paths and machine
operations and their schedule are known a
priori.
 Blocking and Non-Blocking Operator:

„ Ordinary procedural assignment operator “=”, stores the

value immediately after the statement execution and
before the next statement can execute. Also called as
Blocking assignment operator.
“If there is data dependencies among the variables, outcome may get
affected.”
„ To avoid such cases Non-Blocking assignment “<=”
operator is generally used. It effectively executes the
statement concurrently rather than sequentially.
Example(4-bit serial shift register):
module shiftreg_BA(A,E, clk, rst);
input E, clk, rst;
output A;
reg A, B, C, D;
always @(posedge clk or posedge rst)
begin
if (rst)
begin A=0; B=0; C=0; D=0; end
else
begin D=E; C=D; B=C; A=B; end
end

always @(posedge clk or posedge rst)

begin
if (rst)
begin A=0; B=0; C=0; D=0; end
else
begin D<=E; C<=D; B<=C; A<=B; end
end

endmodule
Simulation Result:

“Blocking Operator”

“Non-Blocking Operator”
Algorithm-Based Models:
„ Algorithms based models are abstract in nature.
„ It defines the sequence of procedural
assignment within a cyclic behaviour, the
execution of statement determines the storage
variable and output of the machine.
„ Eliminates the need of a priori architecture.
„ Algorithm model execute sequentially, without
an explicit architecture.
“Not all Algorithms can be implemented in hardware”
Linear Feedback Shift Register:
Reset

C3 C2 C1
R R R R
D S + D S + D S + D S
Y[4]
Clk Y[1] Clk Y[2] Clk Y[3] Clk

Clock

• Used in data-compression circuits implementing a signature analysis

technique called cyclic redundancy check.
• C1, C2, C3 are binary tap coefficients, which determine whether Y[N]
is fed back to a given stage of the register.
•Vector of tap coefficients characterize polynomial of LFSR and its
cyclic nature.
Verilog code of LFSR:
module LFSR (Y, clk, rst);
parameter length=8;
parameter in_state =8'b10010001;
parameter [1:length] tap=8'b11001111;
input clk, rst;
output [1:length] Y;
reg [1:length] Y;
always @(posedge clk)
begin
if(rst==0) Y<=in_state;
else
begin Y[1]<=Y[8];
Y[2]<=tap[7]?Y[1]^Y[8]:Y[1];
Y[3]<=tap[6]?Y[2]^Y[8]:Y[2];
Y[4]<=tap[5]?Y[3]^Y[8]:Y[3];
Y[5]<=tap[4]?Y[4]^Y[8]:Y[4];
Y[6]<=tap[3]?Y[5]^Y[8]:Y[5];
Y[7]<=tap[2]?Y[6]^Y[8]:Y[6];
Y[8]<=tap[1]?Y[7]^Y[8]:Y[7];
end
end
endmodule
Simulation result of LFSR:
Digital Machines with Repetitive Algorithms:

*** Data movement in LFSR for multiple cycles ***

Loop Constructs in Verilog:
„ for loop:
for( initial_stat; control_exp; index _stat)
„ repeat loop:
repeat ( N)
„ while loop:
while (expression)
„ forever loop:
causes unconditional repetitive execution of
statements, subject to the disable statement.
*** repeat can also be terminated by a disable statement ***
Example for for loop:

*** Verilog code for multiple cycle in LFSR ***

 Intellectual Property Reuse:
count =0;
temp_reg = data; // storing the data word in temp register

while (temp_reg)
begin
if (temp_reg [0] ) count =count+1;
temp_reg = temp_reg >> 1;
end

while (temp_reg)
begin
count =count + temp_reg[0];
temp_reg = temp_reg >> 1;
end

*** while loop will execute till the time temp register is not equal to zero ***
Difference between forever & always :

„ always declares a concurrent behaviour whereas

forever loop is a computational activity flow and used
within the behaviour only.
„ forever loop can be nested whereas always cannot be
nested.
„ forever loop executes within a sequential activity flow,
whereas always becomes active and execute at the
beginning of the simulation.
„ To stop the forever loop disable is required but always
automatically stops at the end of the simulation.
Example of disable construct :
output [3:0] index;
input [15:0] word;
input trigger;
reg [3:0] index;

always @ (trigger)
begin: search_1
index = 0;
for ( index = 0; index <= 15; index = index+1 )
if ( word [index])
disable search_1;
end

1. Execution of disable allows the simulator to come out of the

loop.
2. If there is named block after the disable, it will prematurely
terminate the named block of procedural statement
Tasks:
„ Declared within a module and referenced only from
within a cyclic or single pass behavior.
„ Assigned parameters are associated with the declared
input and output variables of the task.
„ Additional local variables can be declared within a task.
„ task must be named and all the declarations are local to
the task.
„ All the arguments to the task are passed by a value –
not by a pointer to the value.
„ task may have event control operator but not delay
control operator.
Example of task :
module task_a (out, sum, in, data_a, data_b, clk, rst);
output [3:0] sum;
output out;
input [3:0] data_a, data_b ;
input clk, rst, in;
reg sum, out;
always @ (posedge clk or posedge rst)
begin
if (rst) {out,sum}<=0;
else
Add(out, sum, data_a, data_b, in);
task add;
output [3:0] sum;
output out;
input [3:0] data_a, data_b;
input in;
begin {out,sum}<=data_a + ( data_b + in); end
endtask
end
endmodule
Functions:
„ functions are declared within a parent module
and can be referenced in any valid expression.
„ function returns a value at the function’s
identifier.
„ function cannot invoke task and may not
contain a timing controls. ( @, #, wait )
„ function can call other functions but not
recursively.
„ It may contain a declaration of input and local
variables, but may not have declared output.
Example of function :
module word_align (word_out, word_in);
output [7:0] word_out;
input [7:0] word_in ;

assign word_out = align_word(word_in);

function [7:0] align_word;

input [7:0] word_in;
begin
align_word = word_in;
if (align_word!=0)
while (align_word[7]= = 0 )
align_word = align_word<<1;
end
endfunction
endmodule
ASM Charts for Behavioral Modeling :

„ Algorithmic state machine (ASM) charts are an

abstraction of the functionality of a sequential
machine.
„ Display the computational activity as well as the
sequential steps that occur under the influence of
the machine’s input.
„ An ASM chart is organized into blocks using
three fundamental elements: state box, decision
box and conditional box.
ASM Chart for a Vehicle Speed Controller :

Brake has Priority over Accelerator

ASMD Chart :

Two stage Pipeline Register

ASM charts for an Up-Down Counter :

Up- down Counter with and without the conditional output boxes
Barrel Shifter :
„ Used in digital signal processors to avoid
overflow problems by scaling the input and
output of a datapath operation.
„ Shifting the word to the right effectively divide
the word by a power of 2 whereas shifting to the
left multiplies the word by a power of 2.
„ It can be implemented using the combinational
logic as well as registered logic.
8-bit Barrel Shifter with Registered Output :
Example of 32-Word Register File :

assign Data_Out_1=Reg_file[Read_Addr_1];
assign Data_Out_2=Reg_file[Read_Addr_2];
always @ (posedge clock)
begin
if (Write_Enable)
Reg_file[Write_Addr]<=Data_in;
end
endmodule
Keypad Scanner and Encoder :
Keypad Code for Hexadecimal Scanner :
Key Row [3:0] Col [3:0] Code
0 0001 0001 0000
1 0001 0010 0001
2 0001 0100 0010
3 0001 1000 0011
4 0010 0001 0100
5 0010 0010 0101
6 0010 0100 0110
7 0010 1000 0111
8 0100 0001 1000
9 0100 0010 1001
A 0100 0100 1010
B 0100 1000 1011
C 1000 0001 1100
D 1000 0010 1101
E 1000 0100 1110
F 1000 1000 1111
ASM Chart for Keypad :
Text Bench Model for Hex-Keypad :

Row[0] Code[3]

Row[1] Code[2]
Key Grayhill 072
Signal X Row_Signal Row[2] Hex Keypad Code[1]
Generator 16
for Keys Code
Row[3] Code[0]
Generator
Valid

Col [3]
Col [2]
Col [1]
Col [0]

***www.grahill.com***
Summary :
„ Data types are broadly classified as net and wire.
„ Different systems can be implemented using Cyclic
Behavioral, Dataflow/RTL and Architectural based
model.
„ Different loop constructs which Verilog supports are:
for, while, repeat and forever.
„ Verilog supports two types of subprograms:
„ Task create a hierarchical organization of the procedural
statements within a verilog behavior.
„ Function substitute for an expression.
„ ASM charts are abstraction of the functionality of a
sequential machine and are used to model the behavior
of the system.