Dual Image Sensor FMC Module

Hardware Guide
 Table of Contents
1.0  Introduction ............................................................................................................................................................................... 3 
1.1  Description............................................................................................................................................................................ 3 
1.2  Features ............................................................................................................................................................................... 3 
1.3  Ordering Information ............................................................................................................................................................. 4 
1.4  References ........................................................................................................................................................................... 4 
2.0  Functional Description .............................................................................................................................................................. 5 
2.1  FMC Connector .................................................................................................................................................................... 6 
2.2  Voltage Sources ................................................................................................................................................................... 8 
2.3  I2C Chain 1 – IPMI Identification EEPROM .......................................................................................................................... 9 
2.4  I2C Chain 2 – Peripheral Configuration .............................................................................................................................. 11 
2.5  Dual Image Sensor Interfaces ............................................................................................................................................ 12 
2.6  Video Clock Synthesizer ..................................................................................................................................................... 13 
2.7  DVI Output .......................................................................................................................................................................... 14 
2.8  GPIO .................................................................................................................................................................................. 15 
3.0  Known Issues & Limitations .................................................................................................................................................... 16 
3.1  PG_C2M ............................................................................................................................................................................. 16 
3.2  GA[0:1] ............................................................................................................................................................................... 16 
4.0  Revisions ................................................................................................................................................................................ 17 

Figures
Figure 1 – Dual Image Sensor FMC Module, Top ...................................................................................................................................... 3 
Figure 2 – Dual Image Sensor FMC Module, Bottom ................................................................................................................................. 3 
Figure 3 – Dual Image Sensor FMC Module, Block Diagram ..................................................................................................................... 5 
Figure 4 – IPMI Identification, Block Diagram............................................................................................................................................. 9 
Figure 5 – I2C Peripheral Configuration, Block Diagram .......................................................................................................................... 11 
Figure 6 – OmniVision Image Sensor Interface, Block Diagram............................................................................................................... 12 
Figure 7 – Video Clock Synthesizer, Block Diagram ................................................................................................................................ 13 
Figure 8 – DVI Output, Block Diagram ..................................................................................................................................................... 14 
Figure 9 – GPIO, Block Diagram .............................................................................................................................................................. 15 
Figure 10 – Dual Image Sensor FMC Module, PG_C2M related components (R105, R106, D100 unpopulated).................................... 16 

Tables

Table 1 - Ordering Information ................................................................................................................................................................... 4 

Table 2 – FMC LPC Connector Pinout ....................................................................................................................................................... 6 
Table 3 – Dual Image Sensor FMC Module, FMC Pinout........................................................................................................................... 7 
Table 4 – Dual Image Sensor FMC Module, Voltage Sources ................................................................................................................... 8 
Table 5 – IPMI Identification, I2C EEPROM Address ............................................................................................................................... 10 
Table 6 – IPMI Identification, GA[0:1] mapping for FMC carriers ............................................................................................................. 10 
Table 7 – IPMI Identification, EEPROM Content ...................................................................................................................................... 10 
Table 8 – I2C Peripheral Configuration, Device Summary ....................................................................................................................... 11 
Table 9 – Video Clock Generator, Clock Output Usage ........................................................................................................................... 13 

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1.0 Introduction
The purpose of this manual is to describe the functionality and contents of the Dual Image Sensor FMC Module from Avnet Electronics
Marketing. This document includes descriptions of the hardware features.

1.1 Description
The Dual Image Sensor FMC Module is not a stand-alone module, but rather a plug-in module designed to interface with FMC
compatible baseboards. In that role, the Dual Image Sensor FMC Module provides a number of video interfaces to its host via
a LPC FMC connector. The Dual Image Sensor FMC Module is shown in Figure 1 and Figure 2.

1.2 Features
The Dual Image Sensor FMC Module provides the following features.

Video Input
— Dual interface for OmniVision image sensor modules
Video Output
— DVI Output Interface (HDMI connector)
Clock Source
— Video Clock Synthesizer
I2C Configuration
— IPMI Identification EEPROM
— Peripheral Configuration
Other I/O
— General Purpose I/O pins

Figure 1 – Dual Image Sensor FMC Module, Top

Figure 2 – Dual Image Sensor FMC Module, Bottom

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 1.3 Ordering Information
The following table lists the evaluation kit part numbers and available software options.
Internet link at www.em.avnet.com/fmc-image

Part Number Hardware

AES-Dual Image Sensor FMC Module-G Dual Image Sensor FMC Module

Table 1 - Ordering Information

1.4 References

Texas Instruments TFP410 datasheet: PanelBus DVI Transmitter 165 MHz

http://focus.ti.com/docs/prod/folders/print/tfp410.html

Texas Instruments CDCE925 datasheet: Programmable 2-PLL VCXO Clock Synthesizer

http://focus.ti.com/docs/prod/folders/print/cdce925.html

Texas Instruments PCA9546A datasheet: 4-Channel I2C Multiplexer with Reset

http://focus.ti.com/docs/prod/folders/print/pca9546a.html

Texas Instruments TXS0104E datasheet: 4-Bit Bidirectional Voltage Level Translator

http://focus.ti.com/docs/prod/folders/print/txs0104e.html

Texas Instruments SN74AVCH16T245 datasheet: 16-Bit Dual Supply Bus Transceiver

http://focus.ti.com/docs/prod/folders/print/sn74avch16t245.html

Texas Instruments SN74AVCH20T245 datasheet: 20-Bit Dual Supply Bus Transceiver

http://focus.ti.com/docs/prod/folders/print/sn74avch20t245.html

Texas Instruments TPS71718 datasheet:

http://focus.ti.com/docs/prod/folders/print/tps71718.html

Texas Instruments TPS54140 datasheet:

http://focus.ti.com/docs/prod/folders/print/tps54140.html

Texas Instruments TPS22942 datasheet:

http://focus.ti.com/docs/prod/folders/print/tps22942.html

FMC Specification
http://www.vita.com/fmc.html

Platform Management FRU Information Storage Definition V1.0

http://download.intel.com/design/servers/ipmi/FRU1011.pdf

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2.0 Functional Description
The Dual Image Sensor FMC Module is a low pin count (LPC) FMC module containing interfaces intended for video
processing. This module contains no processing intelligence and requires that it be plugged into a compatible baseboard for
power, control and data processing. Figure 3 depicts the architecture of the Dual Image Sensor FMC Module. Subsequent
sections provide details of the board design

Image Sensors DVI over HDMI GPIO

(CON300) (CON301) (CON400) (CON500)

HDMI 1x6
2x16 header 2x16 header
connector header

PCLK XCLK PCLK XCLK

Video Clock Generation I2C Mux
1 1 2 2

Y4
CDCE925 PCA9546 TFP410
Y5

Y2 Y1

voltage voltage voltage voltage

translation translation translation translation

(CON100) I2C

FMC LPC

Figure 3 – Dual Image Sensor FMC Module, Block Diagram

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 2.1 FMC Connector
The FMC LPC connector provides 68 single-ended I/O or 34 differential I/O as defined in Table 2.

Table 2 – FMC LPC Connector Pinout

Note: For the FMC LPC, the connector columns K, J, F, E, B, and A are not used and not shown in the above table.

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 The FMC LPC pin allocation for the Dual Image Sensor FMC Module is defined in Table 3.

H G D C
1 - GND 1 PG_C2M GND 1
2 PRSNT_M2C_L CAM2_PCLK 2 GND - 2
3 GND VIDEO_CLK_S6 3 GND - 3
4 CAM1_PCLK GND 4 - GND 4
5 - GND 5 - GND 5
6 GND VIDEO_CLK_V6 6 GND - 6
7 CAM1_RSVD[5] CAM1_RSVD[6] 7 GND - 7
8 CAM1_RSVD[4] GND 8 CAM1_RST GND 8
9 GND CAM1_RSVD[3] 9 GPIO[3] GND 9
10 CAM1_RSVD[1] CAM1_RSVD[2] 10 GND CAM1_VSYNC 10
11 CAM1_RSVD[0] GND 11 CAM1_D[9] CAM1_HREF 11
12 GND CAM1_D[7] 12 CAM1_D[8] GND 12
13 CAM1_D[5] CAM1_D[6] 13 GND GND 13
14 CAM1_D[4] GND 14 CAM1_D[1] CAM1_D[3] 14
15 GND CAM2_RST 15 CAM1_D[0] CAM1_D[2] 15
16 CAM2_RSVD[3] I2C_MUX_RST 16 GND GND 16
17 CAM2_RSVD[2] GND 17 CAM2_RSVD[5] GND 17
18 GND CAM2_RSVD[1] 18 CAM2_RSVD[4] CAM2_PWDN 18
19 CAM2_D[9] CAM2_RSVD[0] 19 GND CAM2_RSVD[6] 19
20 CAM2_D[8] GND 20 CAM2_VSYNC GND 20
21 GND CAM2_D[7] 21 CAM2_HREF GND 21
22 CAM2_D[5] CAM2_D[6] 22 GND DVO_IDCK+ 22
23 CAM2_D[4] GND 23 DVO_D[11] CAM1_PWDN 23
24 GND CAM2_D[3] 24 DVO_D[10] GND 24
25 CAM2_D[1] CAM2_D[2] 25 GND GND 25
26 CAM2_D[0] GND 26 DVO_D[7] DVO_D[9] 26
27 GND DVO_D[5] 27 DVO_D[6] DVO_D[8] 27
28 DVO_D[3] DVO_D[4] 28 GND GND 28
29 DVO_D[2] GND 29 - GND 29
30 GND DVO_D[1] 30 TDI SCL 30
31 DVO_HSYNC DVO_D[0] 31 TDO1 SDA 31
32 DVO_VSYNC GND 32 3P3VAUX GND 32
33 GND DVO_DE 33 - GND 33
34 HDMI_HOTPLUG DVO_RST# 34 - GA0 34
35 GPIO[0] GND 35 GA1 12P0V 35
36 GND GPIO[1] 36 3P3V GND 36
37 I2C_MUX_SDA GPIO[2] 37 GND 12P0V 37
38 I2C_MUX_SCL GND 38 3P3V GND 38
39 GND VADJ 39 GND 3P3V 39
40 VADJ GND 40 3P3V GND 40

Table 3 – Dual Image Sensor FMC Module, FMC Pinout

1
TDO is connected to TDI in order not to break the JTAG chain
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 2.2 Voltage Sources
All voltages on the Dual Image Sensor FMC Module are implemented using TI discrete power solutions. The following table
lists all the voltage sources available on the Dual Image Sensor FMC Module.

Voltage Name Voltage Current Description

supplied by FMC connector
3P3VAUX 3.3 V Used by IPMI Identification prior to module power-up.
3P3V 3.3 V

VADJ 2.5 V or 3.3 V Used for all signals connected to FMC connector.

12P0V 12.0 V

supplied by on-board voltage regulators

REG_1P8V 1.8 V 150 mA Used by CDCE925 clock synthesizer.
Generated by TPS71718DCKRG4.
REG_5P0V 5.0 V 1500 mA Used by GPIO and optionally, image sensors.
Generated by TPS54140.
HDMI_5P0V 5.0 V 100 mA Used by HDMI connector
Generated by TPS22942DCKR.
jumper selectable voltages
VCAM 3.3 V or 5.0 V Image Sensor voltage source.
Selectable with jumper J302.
VGPIO 3.3 V or 5.0 V GPIO voltage source.
Selectable with jumper J500.

Table 4 – Dual Image Sensor FMC Module, Voltage Sources

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 2.3 I2C Chain 1 – IPMI Identification EEPROM
The Dual Image Sensor FMC Module implements two I2C chains. The first I2C chain is used to implement the IPMI
identification for the FMC module.
3P3VAUX

GA1
GA0 EEPROM

SCL
SDA

PRSTN_M2C_L

PG_C2M
EN#
VADJ

VREF_A_M2C

FMC LPC
Connector
(CON100)

Figure 4 – IPMI Identification, Block Diagram

Before the module is powered-up, the carrier must identify the FMC module. At this point, the main power to the module is off.
Only the auxiliary 3.3V power rail (3P3VAUX) is active.

The carrier detects the presence of an FMC module by verifying that PRSTN_M2C_L is asserted low. It then queries the I2C
EEPROM to discover which voltage is requested by the module for VADJ. The EEPROM for this module will support the
following voltages:

• 2.5 V
• 3.3 V

The carrier will power up the module by applying the requested voltage to VADJ. When the voltage is valid, the PG_C2M (ie.
power good) will be asserted high. An inverted version of this signal is used to enable all the voltage level translators
connected to VADJ.

VREF_A_M2C is not used for this FMC module.

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 The address of the I2C EEPROM will be determined by the GA[0:1] signals driven by the carrier.

Note : The GA[0:1] bits are incorrectly connected on the Dual Image Sensor FMC Module (they are swapped).

Table 5 describes the normal EEPROM address, and the actual EEPROM address for the Dual Image Sensor FMC Module.

Normal FMC Dual Image Sensor FMC

GA[0:1] I2C EEPROM Address Module
I2C EEPROM Address
00 0xA0 0xA0
01 0xA2 0xA4
10 0xA4 0xA2
11 0xA6 0xA6
Table 5 – IPMI Identification, I2C EEPROM Address

The GA[0:1] swap error will only be a problem on FMC carriers which are using both GA[0:1]==01 and GA[0:1]==10.
This case does not exist in the current portfolio of FMC carriers, listed in Table 6.

GA[0:1] mapping
FMC Carrier FMC slot 1 FMC slot 2
Avnet Virtex-6 LX130T development kit 00b
Avnet Spartan-6 LX150T development kit 00b 01b
Avnet Spartan-6 LX16 low cost 00b
Avnet Spartan-6 LX45T co-processing kit 00b
Xilinx ML605 00b 01b
Xilinx SP601 10b
Xilinx SP605 10b
Table 6 – IPMI Identification, GA[0:1] mapping for FMC carriers

The EEPROM content is defined by the Platform Management FRU Information Storage Definition V1.0.
http://download.intel.com/design/servers/ipmi/FRU1011.pdf

For the Dual Image Sensor FMC Module, the content is described in Table 7.

Content Dual Image Sensor FMC Module

Board Information
- Manufacturer Date/Time -
- Manufacturer Avnet
- Product Dual Image Sensor FMC Module
- Serial -
- Part Number AES-FMC-IMAGEOV-G
- FRU File ID -
Table 7 – IPMI Identification, EEPROM Content

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 2.4 I2C Chain 2 – Peripheral Configuration
The Dual Image Sensor FMC Module implements two I2C chains. The second I2C chain is used to configure the FMC
module’s peripherals.

VADJ
3P3V

CAM1_SCL
Image
VADJ 2 CAM1_SDA Sensor 1

3P3V
MUX_SCL
MUX_SDA
CAM2_SCL
Image off-board
1 CAM2_SDA devices
VADJ Sensor 2

REG_5P0V
I2C_SW_RST
HDMI_SCL
HDMI
4 HDMI_SDA EDID

3P3V

TMDS_PLL_SCL
TMDS
3 TMDS_PLL_SDA Serializer
on-board
devices
I2C Clock
FMC LPC
Multiplexer Synth.
Connector
(PCA9546A)
(CON100)

Figure 5 – I2C Peripheral Configuration, Block Diagram

The Texas Instruments PCA9546A I2C Multiplexer performs two purposes:

• Voltage level translation (2.5 V, 3.3 V, 5.0 V)

• I2C address conflict resolution

The following table lists the I2C addresses that may be present on each of the I2C Multiplexer’s ports. Notice that the I2C
Multiplexer’s address is always visible regardless of which port is enabled.

Device I2C Address

I2C Multiplexer 0xE0 (PCA9546)
Mux Port 1
Image Sensor 0x60 (OV9715)
Mux Port 2
Image Sensor 0x60 (OV9715)
Mux Port 3
TMDS serializer 0x70 (TFP410)
Video Clock Synth. 0xC8 (CDCE925)
Mux Port 4
DVI DDC EDID 0xA0 / 0xA2 / 0xA6
Table 8 – I2C Peripheral Configuration, Device Summary

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 2.5 Dual Image Sensor Interfaces
The following block diagram illustrates the connections to each of the OmniVision image sensor interfaces.

REG_5P0V

3P3V
J302
3P3V

VADJ CAM{i}_SCL
PG_C2M EN# VCAM CAM{i}_SDA

3P3V

CAM{i}_XCLK
CAM{i}_RST
CAM{i}_PWDN

CAM{i}_PCLK Voltage Level

CAM{i}_VSYNC Translation
circuit
CAM{i}_HREF
CAM{i}_D[9:0]

CAM{i}_RSVD[6:0]

Voltage Level OmniVision

Translator Image Sensor
FMC LPC (SN74AVCH16T245) Connectors
Connector (CON300/CON301)
(CON100)

Figure 6 – OmniVision Image Sensor Interface, Block Diagram

The OmniVision image sensors use the VCAM voltage selected by the J302 jumper. This voltage will either be 3.3 V or 5.0 V.

All image sensor signals connected to the FMC connector pass through several Texas Instruments SN74AVCH16T245 voltage
level translators. The voltage level translators are enabled by an inverted version of the PG_C2M signal, which indicates when
the VADJ voltage is valid.

The XCLK signals, originating from the on-board Texas Instruments CDCE925 clock synthesizer, are also voltage translated
using a simple passive circuit. The I2C signals, originating from the Texas Instruments PCA9546A I2C Multiplexer do not
require voltage translation, as this device already performs voltage translation.

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 2.6 Video Clock Synthesizer
A Video Clock Generator is included on the FMC module in order to provide a clock for all video applications.

The following block diagram illustrates the connections for the Video Clock Generator.

REG_1P8V REG_1P8V

S0 3P3V
VDDout
VADJ
TMDS_PLL_SCL
for S6 carrier CLK0_M2C_N Y1
TMDS_PLL_SDA
for V6 carrier LA00_P_CC Y2

Y3

27 MHz
CAM1_PCLK CAM1_XCLK
CLK0_M2C_P Y4

for both Image Sensor #1

S6 and V6 Connector
carriers (CON300)

CAM2_PCLK CAM2_XCLK
CLK1_M2C_P Y5

FMC LPC Image Sensor #2 Video Clock

Connector Connector Synthesizer
(CON100) (CON301) (CDCE925)

Figure 7 – Video Clock Synthesizer, Block Diagram

The Texas Instruments CDCE925 clock synthesizer has five clock outputs which are used as follows.

Clock PLL Description

Y1 PLL1 Can be used for any application
Y2 PLL1 Can be used for any application
Y3 - Unused
Y4 PLL2 Must be used for Camera #1’s XCLK
Y5 PLL2 Must be used for Camera #2’s XCLK
Table 9 – Video Clock Generator, Clock Output Usage
The Y4 and Y5 clock outputs are dedicated to be used as the reference clock (XCLK) for the image sensor modules.

The Y1 and Y2 clock outputs can be used for any application. One of these applications could be the clock source for the DVI
output.

The default mode of the CDCE925 is to output a 27 MHz clock on all of its outputs.

Configuration is performed via I2C. The SDA/SCL pins of the CDCE925 device are 3.3 V tolerant.
The settings of the CDCE925 video clock synthesizer can be calculated automatically using the TI Pro-Clock™ software.

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 2.7 DVI Output
The DVI Output interface is implemented using the Texas Instruments TFP410 TMDS Serializer. This device generates a DVI
compatible output signal which is sent to an HDMI connector.

Since HDMI monitors are capable of displaying DVI signals, this output can be used to drive:

• DVI monitor (using a HDMI to DVI cable)

• HDMI monitor (using an HDMI cable)

The following block diagram illustrates the connections between the FMC connector and TMDS Serializer.

3P3V
3P3V

VADJ
TMDS_PLL_SCL
TMDS_PLL_SDA
DVO_IDCK+
DVO_RST# HDMI_5P0V
DVO_VSYNC
HDMI_TXC+
DVO_HSYNC HDMI_TXC- REG_5P0V
DVO_DE
HDMI_TX[2:0]+ HDMI_SCL
DVO_D[11:0]
HDMI_TX[2:0]- HDMI_SDA

Voltage Level TMDS HDMI

Translator Serializer Connector
(SN74AVC20T245) (TFP410) (CON400)

DVO_HOTPLUG HDMI_HOTPLUG

Voltage Level
FMC LPC
Translator
Connector
(SN74CB3T1G125)
(CON100)

Figure 8 – DVI Output, Block Diagram

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 2.8 GPIO
A general purpose header will be provided for user specific functionality. One of the intended purposes of the GPIO header is
motor control for the image sensor modules.

The following block diagram illustrates the connections between the FMC connector and GPIO header.

REG_5P0V

3P3V
J500

VADJ
VGPIO

GPIO[3:0]

FMC LPC Voltage Level GPIO

Connector Translator Header
(CON100) (TXS0104E) (CON500)

Figure 9 – GPIO, Block Diagram

The GPIO header uses the VGPIO voltage selected by the J500 jumper. This voltage will either be 3.3 V or 5.0 V.

All bidirectional GPIO signals pass through a Texas Instruments TXS0104E voltage level translator.

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3.0 Known Issues & Limitations
This section describes the known issues and limitations for the Dual Image Sensor FMC Module.

3.1 PG_C2M
The FMC specification specified that a pull-up may be used used on a FMC carrier for the C2M_PG signal.

The Dual Image Sensor FMC Module schematics, however, has a pull-down (R106) on this signal. It also has a LED (R105,
D100), which acts as an additional pull-down. This creates contention with the pull-up on the FMC carrier.

This is a design error, and should not be copied to a new design.

This error has been handled by not populating the components shown in the following figure.

Figure 10 – Dual Image Sensor FMC Module, PG_C2M related components (R105, R106, D100 unpopulated)

3.2 GA[0:1]
The FMC specification specified that the GA[0:1] signals should be connected to the IPMI EEPROM’s A[1:0] address lines as
follows:.
• GA[0] => I2C EEPROM device’s A[1]
• GA[1] => I2C EEPROM device’s A[0]

The Dual Image Sensor FMC Module schematics, however, has the GA[0:1] connected in reverse order.
• GA[0] => I2C EEPROM device’s A[0]
• GA[1] => I2C EEPROM device’s A[1]

This is a design error, and should not be copied to a new design.

This error has not been fixed on the module since it can be handled by software. For more information on how this affects the
address of the I2C EEPROM, refer to section “I2C Chain 1 – IPMI Identification EEPROM”.

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4.0 Revisions
V1.0 Initial release for production board (AES-Dual Image Sensor FMC Module-G Revision) April 10, 2010

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