CDRom Examples Hardware Design

PROJECT
PLANNING
TECHNIQUES
EXAMPLES:
Hardware Design
Project
Parviz F. Rad
Vittal Anantatmula
Unit of Supply Cost
Resources: Measure Limit ($US)
1. Personnel
1.1. Design Engineers
1.1.1. Design Manager
1.1.1.1. Senior level Yr 1 275,000
1.1.2. Circuit Design Engineers
1.1.2.1. Analog
1.1.2.1.1. Principle level Yr 1 255,000
1.1.2.1.2. Staff level Yr 2 225,000
1.1.2.1.3. Sr. level Yr 1 200,000
1.1.2.1.4. Intermediate level Yr 3 167,500
1.1.2.1.5. Engineer level Yr 1 145,000
1.1.2.2. Digital
1.1.2.2.1. Staff level Yr 1 200,000
1.1.2.2.2. Sr. level Yr 1 185,000
1.1.2.2.3. Intermediate level Yr 2 160,000
1.1.3. Mask Design Engineers
1.1.3.1. Sr. level Yr 1 130,000
1.1.3.2. Intermediate level Yr 1 115,000
1.1.3.3. Engineer level Yr 1 97,500
1.2. CAE Engineers (Computer Automated Engineering)
1.2.1. Staff level Yr 1 200,000
1.2.2. Sr. Level Yr 1 185,000
1.3. ESD Engineers (Electro-Static Discharge)
1.3.1. Principle level Yr 1 210,000
1.3.2. Staff level Yr 2 182,500
1.4. Applications Engineers
1.4.2. Intermediate level Yr 1 125,500
1.4.3. Engineer level Yr 1 105,000
1.5. Product Engineers
1.5.1. Staff level Yr 1 150,000
1.5.2. Sr. level Yr 1 135,500
1.6. FA Engineers (Failure Analysis)
1.6.2. Sr. level Yr 1 130,000
1.7. Project Management
1.7.1. Staff level Yr 3 140,000
1.8. System Administration
1.8.1. Staff level Yr 1 130,000
2. Tools
2.1. Computers
2.1.1. Unix 5 payments, yearly 17 4,000
2.1.2. PC 5 payments, yearly 15 500
2.2. LCD projector 5 payments, yearly 3 850
2.3. Plotter 5 payments, yearly 1 2000
2.4. Printer
2.4.1. Color 5 payments, yearly 1 1,100
2.4.2. B/W 5 payments, yearly 1 625
2.5. Test boards
2.5.1. AC board fab run each Unlimited 5,000
2.5.2. DC board fab run each Unlimited 4,000
2.5.3. Jitter board fab run each Unlimited 5,000
2.5.4. Sockets each Unlimited 1,500
2.5.5. Application board each Unlimited 2,000
2.6. Test equipment
2.6.1. AC setup 5 payments, yearly 2 60,000
2.6.2. DC setup 5 payments, yearly 1 45,000
3. Licenses
3.1. Software
3.1.1. Cadence yearly 25 20,000
3.1.2. Microsoft project yearly 3 500
All personnel (Section 1.0) available in this project environment are salaried employees.
A small amount of the fringe benefit may vary year to year, but for this assignment it is
considered constant. Depending on the software utilized in creating the project schedule
in later assignments, care must be given to make sure that an overtime rate is assigned as
$0.00. The personnel resources are not able to receive overtime pay. In order to indicate
this, all personnel rates are as given as cost/year. The personnel are first grouped by
function. The lowest function level is then grouped by job title.
Most of the tools available in this project environment (Section 2.0, excluding section
2.5) are capitalized purchases. The tools are depreciated in a straight-line manner over
five years. The depreciation value per year is included in the RBS for cost purposes. In
order to allocate cost for the RBS it is assumed that the tools have been recently
purchased, therefore current book value is equal to purchase price. The tools are grouped
by logical segments. Some segments are then further grouped by type.
The test boards and sockets (Section 2.5) are generated and charged on a per - project basis
if needed. The boards are purchased from a vendor and processed as a sheet. The vendor
can yield up to six boards but guarantees a yield of four. If the yield is higher than four,
the charge does not change.
Work Breakdown Structure
0.0 ABC123 Integrated circuit database

1.0 Circuit design schematics
1.1 Base-level schematics
1.1.1 Multiplexer1
1.1.2 Multiplexer2
1.1.3 Rotational frequency detector
1.1.4 Variable controlled oscillator
1.1.5 Digital/analog converter
1.1.6 Counter1
1.1.7 Counter2
1.2 Block-level schematics
1.2.1 Equalizer
1.2.2 CDR PLL
1.2.3 Transmitter PLL
1.2.4 LVDS driver
1.2.5 Decoder
1.2.6 Encoder
1.2.7 Cable driver
1.3 Top-level schematic
2.0 Mask design cells
2.1 Base-level cells
2.1.1 Multiplexer1
2.1.2 Multiplexer2
2.1.3 Rotational frequency detector
2.1.4 Variable controlled oscillator
2.1.5 Digital/analog converter
2.1.6 Counter1
2.1.7 Counter2
2.2 Block-level cells
2.2.1 Equalizer
2.2.2 CDR PLL
2.2.4 LVDS driver
2.2.5 Decoder
2.2.6 Encoder
2.2.7 Cable driver
2.3 Top-level cell
3.0 Documentation
3.1 NPPRS Deliverables
3.1.1 Product requirement specification
3.1.2 Intellectual property plan
3.1.3 CAD and design library development plan
3.1.4 Project risk analysis
3.1.5 Design FMEA
3.1.6 Business case
3.1.7 Buildsheet
3.1.8 DRC/LVS report
3.1.9 Patent applications
3.1.10 Final design review
3.2 Supplemental design documents
3.2.1 Intermediate circuit design reviews
3.2.1.1 Equalizer
3.2.1.2 CDR PLL
3.2.1.3 Transmitter PLL
3.2.1.4 Multiplexer1
3.2.1.6 LVDS driver
3.2.1.7 Decoder
3.2.1.8 Encoder
3.2.1.9 Cable driver
3.2.2 Mask design reviews
3.2.2.1 CDR PLL
3.2.2.3 Cable Driver
3.2.2.4 Equalizer
3.2.2.5 Top-level floorplan review
3.3 Miscellaneous documents
3.3.1 Weekly project review
3.3.2 HSPICE model
3.3.3 DFT analysis
Terms, etc.:
Buildsheet A document that graphically represents the package assembly

requirements for a specific integrated circuit. Package DRCs are
performed while generating this document.
CDR PLL Clock/Data Recovery Phase-Locked Loop
DFT Design for testability. A DFT analysis is performed on the circuit to
decide if additional circuitry is needed to enable various aspects of the
circuit’s functionality to be verified once the physical IC is produced.
DRC/LVS Design Rules Check/Layout vs. Schematic
FMEA Failure Mode Effects Analysis
HSPICE Software used to generate models of a circuit that customers can use to
integrate into their system design model to test functionality.
LVDS Low Voltage Differential Signal
NIBU Network Interface Business Unit, a business unit within the Wired
Communications Division of National Semiconductor
NPPRS Network Interface Business Unit’s New Product Phase Review System is
the structured stage-gate process utilized to develop new products, in
which the deliverables at each phase are clearly defined.
Weekly Project
Review Due to the duration of the design portion of this project, weekly project
reviews are generated for middle and upper management and the team.
The reviews encompass all nine areas of project management as shown in
the RBS.
Resource Intensity Duration Total Effort
0.0 ABC123 Integrated Circuit Database

1.0 Circuit Design Schematics
1.1 Base-level Schematics
1.1.1 Multiplexer1
Analog Design Engineer 1 wkr 2 days 2 wkr-days
Unix Workstation 1 box 2 days 2 box-days
Cadence Software 1 license 2 days 2 license-days
1.1.2 Multiplexer2
Analog Design Engineer 1 wkr 2 days 2 wkr-days
1.1.3 Rotational Frequency Detector
Interm. Analog Design Engineer 1 wkr 10 days 10 wkr-days
Sr. Analog Design Engineer 1 wkr 2 days 2 wkr-days
1.1.4 Variable Controlled Oscillator
1.1.5 Digital/Analog Converter
1.1.6 Counter1
Interm. Digital Design Engineer 1 wkr 4 days 4 wkr-days
1.1.7 Counter2
Digital Design Engineer 1 wkr 5 days 5 wkr-days
1.2 Block-level Schematics
1.2.1 Equalizer
Principle Analog Design Engineer 1 wkr 30 days 30 wkr-days
1.2.2 CDR PLL
Interm Analog Design Engineer 2 wkr 35 days 70 wkr-days
1.2.4 LVDS driver
1.2.5 Decoder
1.2.6 Encoder
1.2.7 Cable Driver
1.3 Top-level Schematic
Sr. Design Manager 1 wkr 3 days 3 wkr-days
Staff CAE Engineer 1 wkr 3 days 3 wkr-days
2.0 Mask Design Cells
2.1 Base-level Cells
2.1.1 Multiplexer1
Mask Design Engineer 1 wkr 4 days 4 wkr-days
2.1.2 Multiplexer2
Sr. Mask Design Engineer 1 wkr 7 days 7 wkr-days
2.1.6 Counter1
2.1.7 Counter2
2.2 Block-level Cells
2.2.1 Equalizer
2.2.2 CDR PLL
Plotter 1 plotter 1 day 1 plotter-day
Plotter 1 plotter 1 day 1 plotter-day
2.2.4 LVDS Driver
2.2.5 Decoder
2.2.6 Encoder
2.2.7 Cable Driver
2.3 Top-level Cell
Plotter 1 plotter 2 days 2 plotter-days
3.0 Documentation
3.1.1 Product Requirement Specification
Principle Applications Engineer 1 wkr 4 days 4 wkr-days
PC 1 PC 4 days 4 PC-days
3.1.2 Intellectual Property Plan
Staff Project Manager 1 wkr 3 days 3 wkr-days
3.1.3 CAD and Design Library Development Plan
Staff CAE Engineer 1 wkr 1 day 1 wkr-day
3.1.4 Project Risk Analysis
3.1.5 Design FMEA
3.1.6 Business Case
Principle Marketing Engineer 1 wkr 1 day 1 wkr-day
3.1.7 Buildsheet
Mask Design Engineer 1 wkr 1 day 1 wkr-day
Unix Workstation 1 box 1 day 1 box-day
B/W Printer 1printer 1 hour 1 printer-hr
3.1.8 DRC/LVS Report
B/W Printer 1 printer 1 hour 1 printer-hr
3.1.9 Patent Applications
Sr. Design Manager 1 wkr 1 days 1 wkr-day
3.1.10 Final Design Review
B/W Printer 1 printer 3 hours 3 printer-hrs
3.2 Supplemental Design Documents
3.2.1 Intermediate Circuit Design Reviews
3.2.1.1 Equalizer
B/W Printer 1 printer 1 hr 1 printer-hr
3.2.1.2 CDR PLL
Interm Analog Design Engineer 2 wkr 3 days 6 wkr-days
Analog Design Engineer 1 wkr 1 day 1 wkr-day
Analog Design Engineer 1 wkr 1 day 1 wkr-day
3.2.1.6 LVDS Driver
Interm. Analog Design Engineer 1 wkr 1 day 1 wkr-day
3.2.1.7 Decoder
Interm. Digital Design Engineer 1 wkr 1 day 1 wkr-day
3.2.1.8 Encoder
Interm. Digital Design Engineer 1 wkr 1 day 1 wkr-day
3.2.2 Mask Design Reviews
3.2.2.1 CDR PLL
Plotter 1 plotter 3 hours 3 plotter-hrs
Mask Design Engineer 1 wkr 1 days 1 wkr-day
Unix Workstation 1 box 1 days 1 box-day
3.2.2.4 Equalizer
3.2.2.5 Top-level Floorplan Review
3.3 Miscellaneous Documents
3.3.1 Weekly Project Review
Staff Project Manager 1 wkr 12 hours 12 wkr-hrs
PC 1 PC 12 hours 3 PC-hrs
LCD projector 1 LCD 2 hours 2 LCD-hrs
MSProject Software 1 license 5 hours 5 license-hrs
3.3.2 HSPICE Model
Applications Engineer 1 wkr 6 days 6 wkr-days
3.3.3 DFT Analysis
Interm. Applications Engineer 1 wkr 3 days 3 wkr-days
PC 1 PC 1 day 1 PC-day
Resource Intensity Duration Total Effort Cost ($US)
0.0 ABC123 Integrated Circuit Database

Sr. Design Manager 16 Sr. Design Manager -days 16889
Principle Analog Design Engineer 125 Principle Analog Design Engineer -days 122323
Sr. Analog Design Engineer 67 Sr. Analog Design Engineer -days 51402
Interm. Analog Design Engineer 204 Interm. Analog Design Engineer -days 73257
Analog Design Engineer 6 Analog Design Engineer -days 3342
Interm. Digital Design Engineer 35 Interm. Analog Design Engineer -days 21511
Sr. Mask Design Engineer 37 Sr. Mask Design Engineer -days 18494
Mask Design Engineer 67 Mask Design Engineer -days 25138
Staff CAE Engineer 10 Staff CAE Engineer -day 7673
Principle Applications Engineer 4 Principle Applications Engineer -days 2536
Interm. Applications Engineer 3 Interm. Applications Engineer -days 1445
Applications Engineer 6 Applications Engineer -days 2419
Principle Marketing Engineer 1 Principle Marketing Engineer -day 693
Staff Project Manager 124 Staff Project Manager -hrs 8352
Unix Workstation 403 Unix Workstation -days 6372
PC 146 PC-hrs 43
LCD Projector 2 Projector-hrs 1
B/W Printer 19 Printer-hr 17
Plotter 47 Plotter-hrs 56
Cadence Software 365 Cadence license -days 28595
MSProject Software 5 MSProject license-hrs 2
Subtotal Cost 390560
1.0 Circuit Design Schematics
Staff CAE Engineer 3 Staff CAE Engineer -days 2302
Cadence Software 277 Cadence License-days 21189
1.1 Base-level Schematics
Subtotal Cost 39309
1.1.1 Multiplexer1
Analog Design Engineer 1 Analog Design Engineer 2 days 2 Analog Design Engineer -days 1114
Unix Workstation 1 Unix Workstation 2 days 2 Unix Workstation -days 31
Cadence Software 1 Cadence License 2 days 2 Cadence license-days 154
1.1.2 Multiplexer2
Analog Design Engineer 1 Analog Design Engineer 2 days 2 Analog Design Engineer -days 1114
Interm. Analog Design Engineer 1 Interm. Analog Design Engineer 10 days 10 Interm. Analog Design Engineer -days 6426
Sr. Analog Design Engineer 1 Sr. Analog Design Engineer 2 days 2 Sr. Analog Design Engineer -days 1535
Cadence Software 1 Cadence License 20 days 20 Cadence License-days 1540
1.1.6 Counter1
Interm. Digital Design Engineer 1 Interm. Analog Design Engineer 4 days 4 Interm. Analog Design Engineer -days 2458
1.1.7 Counter2
Interm. Digital Design Engineer 1 Interm. Analog Design Engineer 5 days 5 Interm. Analog Design Engineer -days 3073
1.2 Block-level Schematics
Interm Analog Design Engineer 87 Interm. Analog Design Engineer -days 55906
Interm. Digital Design Engineer 16 Interm. Digital Design Engineer -days 9834
1.2.1 Equalizer
Principle Analog Design Engineer 1 Principle Analog Design Engineer 30 days 30 Principle Analog Design Engineer -days 29358
1.2.2 CDR PLL
Interm Analog Design Engineer 2 Interm. Analog Design Engineer 35 days 70 Interm. Analog Design Engineer -days 44982
1.2.4 LVDS driver
1.2.5 Decoder
Interm. Digital Design Engineer 1 Interm. Digital Design Engineer 8 days 8 Interm. Digital Design Engineer -days 4917
1.2.6 Encoder
1.2.7 Cable Driver
1.3 Top-level Schematic
Sr. Design Manager 1 Sr. Design Manager 3 days 3 Sr. Design Manager -days 3167
Staff CAE Engineer 1 Staff CAE Engineer 3 days 3 Staff CAE Engineer -days 2302
2.0 Mask Design Cells
Plotter 4 Plotter-days 36
Subtotal Cost 65524
2.1 Base-level Cells
Subtotal Cost 22827
2.1.1 Multiplexer1
Mask Design Engineer 1 Mask Design Engineer 4 days 4 Mask Design Engineer -days 1501
2.1.2 Multiplexer2
Sr. Mask Design Engineer 1 Sr. Mask Design Engineer 7 days 7 Sr. Mask Design Engineer -days 3499
Sr. Mask Design Engineer 1 Mask Design Engineer 12 days 12 Mask Design Engineer -days 5998
2.1.6 Counter1
2.1.7 Counter2
2.2 Block-level Cells
Plotter 2 Plotter-day 18
Subtotal Cost 28740
2.2.1 Equalizer
2.2.2 CDR PLL
Plotter 1 plotter 1 day 1 Plotter-day 9
Plotter 1 Plotter 1 day 1 Plotter-day 9
2.2.4 LVDS driver
2.2.5 Decoder
2.2.6 Encoder
2.2.7 Cable Driver
2.3 Top-level Cell
Plotter 1 Plotter 2 days 2 Plotter-days 17
3.0 Documentation
Analog Design Engineer 2 Analog Design Engineer -day 1114
Sr. Mask Design Engineer 1 Sr. Mask Design Engineer -day 500
PC 146 PC-hrs 43
LCD projector 2 Projector-hrs 1
Cadence Software 6 Cadence License -days 462
MSProject Software 5 MSProject License-hrs 2
Subtotal Cost 76568
Sr. Mask Design Engineer 1 Sr. Mask Design Engineer -day 500
Staff Project Manager 12 Staff Project Manager -days 6468
PC 16 PC-days 35
Unix Workstation 10 Unix Workstation -day 155
Subtotal Cost 44570
3.1.1 Product Requirement Specification
Principle Applications Engineer 1 Principle Applications Engineer 4 days 4 Principle Applications Engineer -days 2536
PC 1 PC 4 days 4 PC-days 11
3.1.2 Intellectual Property Plan
Sr. Design Manager 1 Sr. Design Manager 2 days 2 Sr. Design Manager -day 2111
Staff Project Manager 1 Staff Project Manager 3 days 3 Staff Project Manager -days 1617
3.1.3 CAD and Design Library Development Plan
Staff CAE Engineer 1 Staff CAE Engineer 1 day 1 Staff CAE Engineer -day 767
Sr. Mask Design Engineer 1 Sr. Mask Design Engineer 1 day 1 Sr. Mask Design Engineer -day 500
3.1.4 Project Risk Analysis
3.1.5 Design FMEA
3.1.6 Business Case
Principle Marketing Engineer 1 Principle Marketing Engineer 1 day 1 Principle Marketing Engineer -day 693
3.1.7 Buildsheet
Mask Design Engineer 1 Mask Design Engineer 1 day 1 Mask Design Engineer -day 375
Unix Workstation 1 Unix Workstation 1 day 1 Unix Workstation -day 16
B/W Printer 1 Printer 1 hour 1 Printer-hr 1
3.1.8 DRC/LVS Report
B/W Printer 1 Printer 1 hour 1 Printer-hr 1
3.1.9 Patent applications
3.1.10 Final Design Review
B/W Printer 1 Printer 3 hours 3 Printer-hrs 1
3.2 Supplemental Design Documents
Interm. Digital Design Engineer 2 Interm. Digital Design Engineer -day 1230
Subtotal Cost 18430
3.2.1 Intermediate Circuit Design Reviews
Interm. Digital Design Engineer 2 Interm. Digital Design Engineer -day 1230
Subtotal Cost 15668
3.2.1.1 Equalizer
B/W Printer 1 Printer 1 hr 1 Printer-hr 1
3.2.1.2 CDR PLL
Interm Analog Design Engineer 2 Interm. Analog Design Engineer 3 days 6 Interm. Analog Design Engineer -days 3856
Analog Design Engineer 1 Analog Design Engineer 1 day 1 Analog Design Engineer -day 557
Analog Design Engineer 1 Analog Design Engineer 1 day 1 Analog Design Engineer -day 557
3.2.1.6 LVDS driver
Interm. Analog Design Engineer 1 Interm. Analog Design Engineer 1 day 1 Interm. Analog Design Engineer -day 643
3.2.1.7 Decoder
Interm. Digital Design Engineer 1 Interm. Digital Design Engineer 1 day 1 Interm. Digital Design Engineer -day 615
3.2.1.8 Encoder
Interm. Digital Design Engineer 1 Interm. Digital Design Engineer 1 day 1 Interm. Digital Design Engineer -day 615
3.2.2 Mask Design Reviews
Subtotal Cost 2795
3.2.2.1 CDR PLL
Plotter 1 Plotter 3 hours 3 Plotter-hrs 4
Mask Design Engineer 1 Mask Design Engineer 1 days 1 Mask Design Engineer -day 375
Unix Workstation 1 Unix Workstation 1 days 1 Unix Workstation -day 16
3.2.2.4 Equalizer
B/W Printer 1 Printer 1 hr 1 Printer -hr 1
Plotter 1 Plotter 3 hours 3 Plotter -hrs 4
3.2.2.5 Top-level Floorplan Review
B/W Printer 1 Printer 1 hr 1 Printer -hr 1
Plotter 1 Plotter 3 hours 3 Plotter -hrs 4
3.3 Miscellaneous Documents
PC 18 PC-hrs 8
LCD projector 2 Projector-hrs 1
Cadence Software 6 Cadence License -days 462
MSProject Software 5 MSProject License-hrs 2
Subtotal Cost 13568
3.3.1 Weekly Project Review
Staff Project Manager 1 Staff Project Manager 12 hours 12 Staff Project Manager -hrs 809
PC 1 PC 12 hours 12 PC-hrs 5
LCD Projector 1 Projector 2 hours 2 Projector-hrs 1
MSProject Software 1 MSProject License 5 hours 5 MSProject License-hrs 2
3.3.2 HSPICE model
Applications Engineer 1 Applications Engineer 6 days 6 Applications Engineer -days 2419
Cadence Software 1 Cadence License 6 days 6 Cadence License -days 462
3.3.3 DFT analysis
Interm. Applications Engineer 1 Interm. Applications Engineer 3 days 3 Interm. Applications Engineer -days 1445
PC 1 PC 1 day 1 PC-day 3
* - Daily rates area calculated from the rates given in the RBS. The costs for the resources utilized in the WBS are given as yearly in
the RBS. The yearly costs were divided by 260 (52 weeks/yr, 5 days/week) to arrive at daily costs then divided by 8 to arrive at
hourly costs if necessary. Since all the human resources are paid on a salary basis, they are not eligible for overtime. This will be
taken into account when developing the schedule. The daily costs are rounded up to the next whole dollar.
Project Cost Comparison by Resource
(Expressed as a percentage of the total cost at given level of the WBS)
Integrated Circuit Mask
Circuit Design Design Docu-
Database Schematics Cells mentation
Resource: Level 0.0 % Level 1.0 % Level 2.0 % Level 3.0 %
Sr. Design Manager 4.32 1.27 3.22 15.16
Principle Analog Design Engineer 31.32 36.23 11.95 31.95
Sr. Analog Design Engineer 13.16 17.60 3.51 7.01
Interm. Analog Design Engineer 18.76 26.64 1.96 7.55
Analog Design Engineer 0.86 0.90 0.00 1.45
Interm. Digital Design Engineer 5.51 6.18 0.00 8.03
Sr. Mask Design Engineer 4.74 0.00 27.46 0.65
Mask Design Engineer 6.44 0.00 32.07 5.39
Staff CAE Engineer 1.96 0.93 7.03 1.00
Principle Applications Engineer 0.65 0.00 0.00 3.31
Interm. Applications Engineer 0.37 0.00 0.00 1.89
Applications Engineer 0.62 0.00 0.00 3.16
Principle Marketing Engineer 0.18 0.00 0.00 0.91
Staff Project Manager 2.14 0.00 0.00 10.91
Unix Workstation 1.63 1.72 2.15 0.91
PC 0.01 0.00 0.00 0.06
LCD projector 0.00 0.00 0.00 0.00
B/W Printer 0.00 0.00 0.00 0.02
Plotter 0.01 0.00 0.05 0.03
Cadence Software 7.32 8.53 10.60 0.60
MSProject Software 0.00 0.00 0.00 0.00
Totals 100.00 100.00 100.00 100.00
Project Cost Comparison by Level

(Expressed as a percentage of the total cost at given level of the WBS)
Level Costs Level 0.0 %
Level 1.0: Circuit Design Schematics $248,468 63.62
Level 2.0: Mask Design Cells $65,524 16.78
Level 3.0: Documentation $76,568 19.60
Total $390,560 100.00
The distribution of resources shown in the above two tables are fairly consistent with
previous similar projects that have been completed within the department. Level 3.0 is
usually slightly lower and Level 1.0 slightly higher, as some of the reviews are accounted
for in the Level 1.0 deliverables. This WBS captures the reviews in the documentation
portion, therefore the differences are justified.
The total cost for the design project is in line with the cost of similarly scoped projects.
The use of the lead designer, principle analog design engineer, is slightly heavier in this
project due to the incorporation of technology that other engineers do not have much
experience with.
Precedence Table
Order of
Exectution Lowest level Elements Predecessors Successors
1 Product Requirement Specification Design Database Start Design FMEA
Base-level Schematic: Multiplexer1
Base-level Schematic: Multiplexer2
Base-level Schematic: Counter1
CAD and Design Library Development Plan
Project Risk Analysis
2 Design FMEA Product Requirement Specification DFT analysis
Base-level Schematic: Multiplexer1 Product Requirement Specification Base-level Cell: Multiplexer1
Block-level Schematic: Decoder
Base-level Schematic: Multiplexer2 Product Requirement Specification Base-level Cell: Multiplexer2
Base-level Schematic: Counter1 Product Requirement Specification Base-level Cell: Counter1

Base-level Schematic: Counter2 Product Requirement Specification Base-level Cell: Counter2
Block-level Schematic: Encoder
Block-level Schematic: LVDS Driver Product Requirement Specification Block-level Cell: LVDS Driver
CAD and Design Library Development Plan Product Requirement Specification Top-level Schematic
Project Risk Analysis Product Requirement Specification Top-level Schematic
3 DFT Analysis Design FMEA Base-level Schematic: Rotational Freq. Detector
Base-level Schematic: Variable Controlled Osc
Base-level Schematic: Digital/Analog Converter
Block-level Schematic: Equalizer
Block-level Schematic: Transmitter PLL
Block-level Schematic: Cable Driver
Base-level Cell: Multiplexer1 Base-level Schematic: Multiplexer1 Block-level Cell: Decoder
Base-level Cell: Multiplexer2 Base-level Schematic: Multiplexer2 Block-level Cell: Encoder
Base-level Cell: Counter1 Base-level Schematic: Counter1 Block-level Cell: Decoder
Base-level Cell: Counter2 Base-level Schematic: Counter2 Block-level Cell: Encoder
Block-level Schematic: Decoder Base-level Schematic: Multiplexer1 Block-level Cell: Decoder
Block-level Schematic: Encoder Base-level Schematic: Multiplexer2 Block-level Cell: Encoder
Block-level Cell: LVDS Driver Block-level Schematic: LVDS driver Interm. Circuit Design Review: LVDS Driver
Top-level Cell
4 Base-level Schematic: Rotational Freq. Detector DFT analysis Base-level Cell: Rotational Frequency Detector
Block-level Schematic: CDR PLL
Base-level Schematic: Variable Controlled Osc. DFT analysis Base-level Cell: Variable Controlled Oscillator
Base-level Schematic: Digital/Analog Converter DFT analysis Base-level Cell: Digital/Analog Converter
Block-level Schematic: Equalizer DFT analysis Block-level Cell: Equalizer
Interm. Circuit Design Review: Equalizer
Block-level Schematic: Transmitter PLL DFT analysis Block-level Cell: Transmitter PLL
Interm. Circuit Design Review: Transmitter PLL
Block-level Schematic: Cable Driver DFT analysis Block-level Cell: Cable Driver
Interm. Circuit Design Review: Cable Driver
Block-level Cell: Decoder Base-level Cell: Multiplexer1 Interm. Circuit Design Review: Decoder
Base-level Cell: Counter1 Top-level Cell
Block-level Cell: Encoder Base-level Cell: Multiplexer2 Interm. Circuit Design Review: Encoder
Base-level Cell: Counter2 Top-level Cell
Block-level Schematic: Encoder
Interm. Circuit Design Review: LVDS Driver Block-level Cell: LVDS driver Top-level Schematic
5 Base-level Cell: Rotational Frequency Detector Base-level Schematic: Rotational Freq. Detector Block-level Cell: CDR PLL
Base-level Cell: Variable Controlled Oscillator Base-level Schematic: Variable Controlled Osc Block-level Cell: CDR PLL
Base-level Cell: Digital/Analog Converter Base-level Schematic: Digital/Analog Converter Block-level Cell: CDR PLL
Block-level Schematic: CDR PLL Base-level Schematic: Rotational Freq. Detector Block-level Cell: CDR PLL
Base-level Schematic: Variable Controlled Osc Interm. Circuit Design Review: CDR PLL
Base-level Schematic: Digital/Analog Converter
Block-level Cell: Equalizer Block-level Schematic: Equalizer Mask Design Review: Equalizer
Interm. Circuit Design Review: Equalizer Block-level Schematic: Equalizer Top-level Schematic
Block-level Cell: Transmitter PLL Block-level Schematic: Transmitter PLL Mask Design Review: Transmitter PLL
Interm. Circuit Design Review: Transmitter PLL Block-level Schematic: Transmitter PLL Top-level Schematic
Block-level Cell: Cable Driver Block-level Schematic: Cable Driver Mask Design Review: Cable Driver
Interm. Circuit Design Review: Cable Driver Block-level Schematic: Cable Driver Top-level Schematic
Interm. Circuit Design Review: Decoder Block-level Cell: Decoder Top-level Schematic
Interm. Circuit Design Review: Encoder Block-level Cell: Encoder Top-level Schematic
6 Block-level Cell: CDR PLL Base-level Cell: Rotational Frequency Detector Mask Design Review: CDR PLL
Base-level Cell: Variable Controlled Oscillator
Base-level Cell: Digital/Analog Converter
Interm. Circuit Design Review: CDR PLL Block-level Schematic: CDR PLL Top-level Schematic
Mask Design Review: Equalizer Block-level Cell: Equalizer Top-level Cell
Mask Design Review: Transmitter PLL Block-level Cell: Transmitter PLL Top-level Cell
Mask Design Review: Cable Driver Block-level Cell: Cable Driver Top-level Cell
7 Mask Design Review: CDR PLL Block-level Cell: CDR PLL Top-level Cell
Top-level Schematic Interm. Circuit Design Review: CDR PLL Final Design Review
Interm. Circuit Design Review: Equalizer Intellectual Property Plan (SS)
Interm. Circuit Design Review: Transmitter PLL Mask Design Review: Top-level Floorplan Review
Interm. Circuit Design Review: Cable Driver (SS + 5d)
Interm. Circuit Design Review: Decoder
Interm. Circuit Design Review: Encoder
Interm. Circuit Design Review: LVDS Driver
CAD and Design library Development Plan
Project Risk Analysis
Intellectual Property Plan Top-level Schematic Final Design Review
Mask Design Review: Top-level floorplan review Top-level Schematic Top-level Cell
8 HSPICE model Top-level Schematic Design Database Complete
Patent applications Top-level Schematic Design Database Complete
Business Case Top-level Schematic Design Database Complete
Final Design Review Top-level Schematic Top-level Cell
Intellectual Property Plan
9 Top-level Cell Block-level Cell: LVDS Driver DRC/LVS Report
Block-level Cell: Decoder Buildsheet (SS + 5d)
Block-level Cell: Encoder
Mask Design Review: Equalizer
Mask Design Review: Transmitter PLL
Mask Design Review: Cable Driver
Mask Design Review: CDR PLL
Mask Design Review: Top-level Floorplan Review
Final Design Review
10 Buildsheet Top-level Cell Design Database Complete
DRC/LVS Report Top-level Cell
Design Database Product Design FMEA DFT analysis Base Level Base Level Cell
Start Requirement Schematic RF D
Specification RF D
4.0 3.1.1 3.1.5 3.3.3 1.1.3 2.1.3
Base Level Base Level Cell

Schematic V C O
V C O
1.1.4 2.1.4
Base Level Base Level Cell HSPICE

Schematic D A C Model
D A C
1.1.5 2.1.5 3.3.2
Block Level Block Level Cell Mask Design Patent

Schematic CDR PLL Review Application
CDR PLL CDR PLL
1.2.2 2.2.2 3.2.2.1 3.1.9
Interm. Design Top Level Business

Review Schematic Case
CDR PLL
3.2.1.2 1.3 3.1.6
S S
Block Level Block Level Cell Mask Design

Schematic Equalizer Review Intellectual Final Design
Equalizer Equalizer Property Plan Review
1.2.1 2.2.1 3.2.2.4
3.1.2 3.1.10
Interm. Design SS + 5d
Review
Equalizer Top-level Top Level LVS/DRC Design
3.2.1.1 Floorplan Review Cell Report Database
Complete
3.2.2.5 2.3 3.1.8 5.0

Schematic Transmitter PLL Review SS + 5d
Buildsheet
Transmitter PLL Transmitter PLL
1.2.3 2.2.3 3.2.2.2
3.1.7
Interm. Design
Review
Transmitter PLL
3.2.1.3

Schematic Cable Driver Review
Cable Driver Cable Driver
1.2.7 2.2.7 3.2.2.3
Base Level Base Level Cell Interm. Design

Schematic Multiplexer 1 Review
Multiplexer 1 Cable Driver
1.1.1 2.1.1 3.2.1.7
Block Level Block Level Cell Interm. Design

Schematic Decoder Review
Decoder Decoder
1.2.5 2.2.5 3.2.1.5

Schematic Counter 1
Counter 1
1.1.6 2.1.6

Schematic Multiplexer 2
Multiplexer 2
1.1.2 2.1.2

Schematic Encoder Review
Encoder Encoder
1.2.6 2.2.6 3.2.1.6

Schematic Counter 2
Counter 2
1.1.7 2.1.7

Schematic LVDS Driver Review
LVDS Driver LVDS Driver
1.2.4 2.2.4 3.2.1.4
Design and CAD

Library
Development Plan
3.1.3
Project Risk
Analysis
3.1.4
uary February March April May June
ID WBS Task Name Duration Float Start Finish Predecessors Successors Resource Names 1/5 1/19 2/2 2/16 3/2 3/16 3/30 4/13 4/27 5/11 5/25
0 0 ABC123 Integrated Circuit Database 104 days 0 days Mon 1/6/03 Thu 5/29/03 0
1 1 Circuit Design Schematics 83 days 0 days Wed 1/8/03 Fri 5/2/03 1
2 1.1 Base-level Schematics 25 days 5 days Wed 1/8/03 Tue 2/11/03 1.1
3 1.1.1 Multiplexer 1 2 days 0 days Wed 1/8/03 Thu 1/9/03 39 15,21
4 1.1.2 Multiplexer 2 2 days 0 days Wed 1/8/03 Thu 1/9/03 39 16,22
5 1.1.3 Rotational Frequency Detector 10 days 0 days Wed 1/15/03 Tue 1/28/03 88 12,23 1.1.3
6 1.1.4 Variable Controlled Oscillator 6 days 0 days Wed 1/15/03 Wed 1/22/03 88 12,24 1.1.4
7 1.1.5 Digital/Analog Converter 20 days 0 days Wed 1/15/03 Tue 2/11/03 88 12,25 1.1.5
8 1.1.6 Counter 1 4 days 0 days Wed 1/8/03 Mon 1/13/03 39 15,26 1.1
9 1.1.7 Counter 2 5 days 0 days Wed 1/8/03 Tue 1/14/03 39 16,27 1.1.
10 1.2 Block-level Schematics 60 days 2 days Wed 1/8/03 Tue 4/1/03 1.2
11 1.2.1 Equalizer 30 days 0 days Wed 1/15/03 Tue 2/25/03 88 29,51 1.2.1
12 1.2.2 CDR PLL 35 days 0 days Wed 2/12/03 Tue 4/1/03 5,6,7 30,52 1.2.2
13 1.2.3 Transmitter PLL 40 days 0 days Wed 1/15/03 Tue 3/11/03 88 31,53 1.2.3
14 1.2.4 LVDS Driver 5 days 0 days Wed 1/8/03 Tue 1/14/03 39 32,54 1.2.
15 1.2.5 Decoder 8 days 0 days Tue 1/14/03 Thu 1/23/03 3,8 33,55 1.2.5
16 1.2.6 Encoder 8 days 0 days Wed 1/15/03 Fri 1/24/03 4,9 34,56 1.2.6
17 1.2.7 Cable Driver 12 days 0 days Wed 1/15/03 Thu 1/30/03 88 35,57 1.2.7
18 1.3 Top-level Schematic 20 days 0 days Mon 4/7/03 Fri 5/2/03 41,51,52,53,54,55,56,57,42 40SS,63SS+5 days,87,48,44,47 1.3
19 2 Mask Design Cells 97 days 0 days Fri 1/10/03 Mon 5/26/03 2
20 2.1 Base-level Cells 35 days 48 days Fri 1/10/03 Thu 2/27/03 2.1
21 2.1.1 Multiplexer 1 4 days 6 days Fri 1/10/03 Wed 1/15/03 3 33 2.1
22 2.1.2 Multiplexer 2 4 days 7 days Fri 1/10/03 Wed 1/15/03 4 34 2.1
23 2.1.3 Rotational Frequency Detector 7 days 38 days Wed 1/29/03 Thu 2/6/03 5 30 2.1.3
24 2.1.4 Variable Controlled Oscillator 8 days 41 days Thu 1/23/03 Mon 2/3/03 6 30 2.1.4
25 2.1.5 Digital/Analog Converter 12 days 23 days Wed 2/12/03 Thu 2/27/03 7 30 2.1.5
26 2.1.6 Counter 1 3 days 5 days Tue 1/14/03 Thu 1/16/03 8 33 2
27 2.1.7 Counter 2 3 days 5 days Wed 1/15/03 Fri 1/17/03 9 34
28 2.2 Block-level Cells 66 days 16 days Wed 1/15/03 Wed 4/16/03 2.2
29 2.2.1 Equalizer 8 days 0 days Wed 2/26/03 Fri 3/7/03 11 62 2.2.1
30 2.2.2 CDR PLL 11 days 0 days Wed 4/2/03 Wed 4/16/03 12,23,24,25 59 2.2.2
31 2.2.3 Transmitter PLL 7 days 0 days Wed 3/12/03 Thu 3/20/03 13 60 2.2.3
32 2.2.4 LVDS Driver 3 days 79 days Wed 1/15/03 Fri 1/17/03 14 36
33 2.2.5 Decoder 2 days 73 days Fri 1/24/03 Mon 1/27/03 15,21,26 36 2.

34 2.2.6 Encoder 2 days 72 days Mon 1/27/03 Tue 1/28/03 16,22,27 36
35 2.2.7 Cable Driver 6 days 0 days Fri 1/31/03 Fri 2/7/03 17 61 2.2.7
36 2.3 Top-level Cell 12 days 0 days Fri 5/9/03 Mon 5/26/03 32,33,34,63,48,59,60,61,62 46,45SS+5 days 2.3
37 3 Documentation 104 days 0 days Mon 1/6/03 Thu 5/29/03 3
38 3.1 NPPRS deliverables 104 days 0 days Mon 1/6/03 Thu 5/29/03 3.1
39 3.1.1 Product Requirement Specification 2 days 0 days Mon 1/6/03 Tue 1/7/03 89 3,4,8,9,43,41,14,42
40 3.1.2 Intellectual Property Plan 2 days 18 days Mon 4/7/03 Tue 4/8/03 18SS 48
41 3.1.3 CAD and Design Library Development Plan 2 days 61 days Wed 1/8/03 Thu 1/9/03 39 18
42 3.1.4 Project Risk Analysis 2 days 61 days Wed 1/8/03 Thu 1/9/03 39 18
43 3.1.5 Design FMEA 2 days 0 days Wed 1/8/03 Thu 1/9/03 39 88

uary February March April May June
ID WBS Task Name Duration Float Start Finish Predecessors Successors Resource Names 1/5 1/19 2/2 2/16 3/2 3/16 3/30 4/13 4/27 5/11 5/25
44 3.1.6 Business Case 3 days 16 days Mon 5/5/03 Wed 5/7/03 18 90
45 3.1.7 Buildsheet 1 day 9 days Fri 5/16/03 Fri 5/16/03 36SS+5 days 90
46 3.1.8 DRC/LVS Report 3 days 0 days Tue 5/27/03 Thu 5/29/03 36 90 3

47 3.1.9 Patent Application 2 days 17 days Mon 5/5/03 Tue 5/6/03 18 90
48 3.1.10 Final Design Review 4 days 0 days Mon 5/5/03 Thu 5/8/03 18,40 36 3.
49 3.2 Supplemental Design Documents 68 days 14 days Wed 1/15/03 Fri 4/18/03 3.2
50 3.2.1 Intermediate Design Reviews 58 days 0 days Wed 1/15/03 Fri 4/4/03 3.2.1
51 3.2.1.1 Equalizer 2 days 26 days Wed 2/26/03 Thu 2/27/03 11 18
52 3.2.1.2 CDR PLL 3 days 0 days Wed 4/2/03 Fri 4/4/03 12 18
53 3.2.1.3 Transmitter PLL 3 days 15 days Wed 3/12/03 Fri 3/14/03 13 18
54 3.2.1.4 LVDS Driver 1 day 57 days Wed 1/15/03 Wed 1/15/03 14 18
55 3.2.1.5 Decoder 1 day 50 days Fri 1/24/03 Fri 1/24/03 15 18
56 3.2.1.6 Encoder 1 day 49 days Mon 1/27/03 Mon 1/27/03 16 18
57 3.2.1.7 Cable Driver 2 days 44 days Fri 1/31/03 Mon 2/3/03 17 18 3.

58 3.2.2 Mask Design Reviews 50 days 14 days Mon 2/10/03 Fri 4/18/03 3.2.2
59 3.2.2.1 CDR PLL 2 days 14 days Thu 4/17/03 Fri 4/18/03 30 36
60 3.2.2.2 Transmitter PLL 1 day 34 days Fri 3/21/03 Fri 3/21/03 31 36
61 3.2.2.3 Cable Driver 1 day 63 days Mon 2/10/03 Mon 2/10/03 35 36
62 3.2.2.4 Equalizer 1 day 43 days Mon 3/10/03 Mon 3/10/03 29 36
63 3.2.2.5 Top-level Floorplan Review 2 days 17 days Mon 4/14/03 Tue 4/15/03 18SS+5 days 36
64 3.3 Miscellaneous Documents 101.5 days 1.5 days Tue 1/7/03 Wed 5/28/03 3.3
65 3.3.1 Weekly Project Reviews 101.5 days 1.5 days Tue 1/7/03 Wed 5/28/03 89 90
87 3.3.2 HSPICE Model 6 days 13 days Mon 5/5/03 Mon 5/12/03 18 90 3.3.2
88 3.3.3 DFT analysis 3 days 0 days Fri 1/10/03 Tue 1/14/03 43 5,6,7,11,13,17 3.
89 4 Design Database Start 0 days 0 days Mon 1/6/03 Mon 1/6/03 39,65 1/6
90 5 Design Database Complete 0 days 0 days Thu 5/29/03 Thu 5/29/03 44,46,47,65,45,87 5/29
ABC123 Integrated Circuit Databas
ID Resource Name Initials Group Max. Units Std. Rate Ovt. Rate Cost/Use Accrue At Base Calendar
1 Sr. Design Manager S 100% $275,000.00/yr $0.00/hr $0.00 Prorated Standard
2 Principle Analog Design Engineer P 100% $255,000.00/yr $0.00/hr $0.00 Prorated Standard
3 Staff Analog Design Engineer S 200% $225,000.00/yr $0.00/hr $0.00 Prorated Standard
4 Sr. Analog Design Engineer S 100% $200,000.00/yr $0.00/hr $0.00 Prorated Standard
5 Intermediate Analog Design Engineer I 300% $167,500.00/yr $0.00/hr $0.00 Prorated Standard
6 Analog Design Engineer A 100% $145,000.00/yr $0.00/hr $0.00 Prorated Standard
7 Staff Digital Design Engineer S 100% $200,000.00/yr $0.00/hr $0.00 Prorated Standard
8 Sr. Digital Design Engineer S 100% $185,000.00/yr $0.00/hr $0.00 Prorated Standard
9 Intermediate Digital Design Enginee I 200% $160,000.00/yr $0.00/hr $0.00 Prorated Standard
10 Sr. Mask Design Engineer S 100% $130,000.00/yr $0.00/hr $0.00 Prorated Standard
11 Intermediate Mask Design Engineer I 100% $115,000.00/yr $0.00/hr $0.00 Prorated Standard
12 Mask Design Engineer M 100% $97,500.00/yr $0.00/hr $0.00 Prorated Standard
13 Staff CAE Engineer S 100% $200,000.00/yr $0.00/hr $0.00 Prorated Standard
14 Sr. CAE Engineer S 100% $185,000.00/yr $0.00/hr $0.00 Prorated Standard
15 Principle ESD Engineer P 100% $210,000.00/yr $0.00/hr $0.00 Prorated Standard
16 Staff ESD Engineer S 200% $182,500.00/yr $0.00/hr $0.00 Prorated Standard
17 Principle Applications Engineer P 100% $165,000.00/yr $0.00/hr $0.00 Prorated Standard
18 Intermediate Applications Engineer I 100% $125,500.00/yr $0.00/hr $0.00 Prorated Standard
19 Applications Engineer A 100% $105,000.00/yr $0.00/hr $0.00 Prorated Standard
20 Staff Product Engineer S 100% $150,000.00/yr $0.00/hr $0.00 Prorated Standard
21 Sr. Product Engineer S 100% $135,500.00/yr $0.00/hr $0.00 Prorated Standard
22 Principle FA Engineer P 100% $160,000.00/yr $0.00/hr $0.00 Prorated Standard
23 Sr. FA Engineer S 100% $130,000.00/yr $0.00/hr $0.00 Prorated Standard
24 Intermediate FA Engineer I 100% $115,500.00/yr $0.00/hr $0.00 Prorated Standard
25 Principle Marketing Engineer P 100% $180,000.00/yr $0.00/hr $0.00 Prorated Standard
26 Staff Project Manager S 300% $140,000.00/yr $0.00/hr $0.00 Prorated Standard
27 Staff System Administrator S 100% $155,500.00/yr $0.00/hr $0.00 Prorated Standard
28 Intermediate System Administrator I 200% $130,000.00/yr $0.00/hr $0.00 Prorated Standard
29 Unix Computer U 1,700% $4,000.00/yr $0.00/hr $0.00 Prorated Standard
30 PC P 1,500% $500.00/yr $0.00/hr $0.00 Prorated Standard
31 LCD Projector L 300% $850.00/yr $0.00/hr $0.00 Prorated Standard
32 Plotter P 100% $2,000.00/yr $0.00/hr $0.00 Prorated Standard
33 Color Printer C 100% $1,100.00/yr $0.00/hr $0.00 Prorated Standard
34 B/W Printer B 100% $625.00/yr $0.00/hr $0.00 Prorated Standard
35 AC Test Boards A 100% $0.00/hr $0.00/hr $5,000.00 Prorated Standard
36 DC Test Boards D 100% $0.00/hr $0.00/hr $4,000.00 Prorated Standard
37 Jitter Test Boards J 100% $0.00/hr $0.00/hr $5,000.00 Prorated Standard
38 Sockets S 100% $0.00/hr $0.00/hr $1,500.00 Prorated Standard
39 Applications Test Boards A 100% $0.00/hr $0.00/hr $2,000.00 Prorated Standard
40 AC Test Equipment Setup A 200% $60,000.00/yr $0.00/hr $0.00 Prorated Standard
41 DC Test Equipment Setup D 100% $45,000.00/yr $0.00/hr $0.00 Prorated Standard
42 Cadence Software License C 2,500% $20,000.00/yr $0.00/hr $0.00 Prorated Standard
43 MSProject 98 Software License M 300% $500.00/yr $0.00/hr $0.00 Prorated Standard
Resource Expenditure Bar Chart
Five Most-used Resource for the Entire Project
400
350
300
250
Usage (hours)
200
150
100
50
0
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21
Project Duration (weeks)
Unix Computer Cadence Software License Principle Analog Design Engineer Mask Design Engineer PC
(Unix Computer - only)
400
350
300
250
Usage (hours)
200
150
100
50
0
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21
(Cadence Software License - only)
400
350
300
250
Usage (hours)
200
150
100
50
0
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21
(Principle Analog Design Engineer - only)
120
100
80
Usage (hours)
60
40
20
0
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21
(Mask Design Engineer - only)
120
100
80
Usage (hours)
60
40
20
0
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21
(PC - only)
70
60
50
Usage (hours)
40
30
20
10
0
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21
Five Most-used Resource for the WBS Level - 1 Elements
Task 1.0: Circuit Design Schematics
350
300
250
Usage (hours)
200
150
100
50
0
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21
Unix Computer Cadence Software License Principle Analog Design Engineer

Intermediate Analog Design Engineer Sr. Analog Design Engineer
350
300
250
Usage (hours)
200
150
100
50
0
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21
(Cadence Software - only)
350
300
250
Usage (hours)
200
150
100
50
0
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21
120
100
80
Usage (hours)
60
40
20
0
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21
(Intermediate Analog Design Engineer - only)
140
120
100
Usage (hours)
80
60
40
20
0
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21
Intermediate Analog Design Engineer

(Sr. Analog Design Engineer - only)
60
50
40
Usage (hours)
30
20
10
0
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21
Task 2.0: Mask Design Cells
120
100
80
Usage (hours)
60
40
20
0
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21
Unix Computer Cadence Software License Mask Design Engineer Sr. Mask Design Engineer Plotter
120
100
80
Usage (hours)
60
40
20
0
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21
(Cadence Software License - only)
120
100
80
Usage (hours)
60
40
20
0
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21
(Mask Design Engineer - only)
120
100
80
Usage (hours)
60
40
20
0
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21
(Sr. Mask Design Engineer - only)
70
60
50
Usage (hours)
40
30
20
10
0
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21
(Plotter - only)
45
40
35
30
Usage (hours)
25
20
15
10
0
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21
Task 3.0: Documentation
70
60
50
Usage (hours)
40
30
20
10
0
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21
PC Staff Project Manager Unix Computer Principle Analog Design Engineer MSProject 98 Software License
(PC - only)
70
60
50
Usage (hours)
40
30
20
10
0
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21
(Staff Project Manager - only)
70
60
50
Usage (hours)
40
30
20
10
0
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21
60
50
40
Usage (hours)
30
20
10
0
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21
60
50
40
Usage (hours)
30
20
10
0
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21
(MSProject 98 Software License - only)
6
4
Usage (hours)
0
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21
Weekly Cost ($K US)
$0
$5
$10
$15
$20
$25
$30
$35
$40
$45
$2
1
0.
30
$3
2
5.
46
$3
3
9.
81
$3
4
2.
37
$2
5
5.
25
$1
6
9.
21
$2
7
2.
79
$1
8
7.
90
$2
9
0.
07
$1
0.
10
97
$2
4.
11
42
$8
.8
12
3
Entire Project
$6
.1
13
8

Cash Flow Bar Chart
$6
.1
14
8
$1
3.
15
80
$1
4.
16
12
$8
17 .4
1
$6
.1
18
8
$1
.5
19
9
$0
.8
20
1
$0
.8
21
1
$0
$50
$100
$150
$200
$250
$300
$350
Cumulative Cost ($K US)

Cash Flow Bar Chart
Level 1 - Task 1.0: Circuit Design Schematics
$40 $200
66
6.
$3
$180
$35
$160
$30
$140
26
5.
Cumulative Cost (k$ US)

$2
Weekly Cost (k$ US)
$25
$120
$20 $100
13
8.
$1
51
6.
$1
04
5.
$80
$1
$15
32
73
1.
$60
$1
0.
$1
$10
$40
0
.8
7
7
.3
.3
.3
.3
.3
$5
$5
$5
$5
$5
$5
$5
5
2
.4
.2
$20
$3
$3
$0 $0
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21
Cash Flow Bar Chart
Level 1 - Task 2.0: Mask Design Cells
$14 $80
90
1.
$70
$1
$12
$60
$10
9
.7

$8
$50
Weekly Cost (k$ US)
$8
0
.2
$7
1
$40
.6
$6
1
.1
$6
1
$6
.6
$5
8
.0
.9
$30
$5
$4
0
.4
$4
$4
$20
6
6
.9
.9
.9
$2
$2
$2
4
.3
$2
$2
$10
3
.9
$0
$0 $0
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21
Cash Flow Bar Chart
Level 1 - Task 3.0: Documentation
$20 $100
53
8.
$1
$18 $90
84
6.
$1
$16 $80
$14 $70
51
2.

$1
Weekly Cost (k$ US)
$12 $60
58
0.
$1
$10 $50
$8 $40
3
$6 $30
.3
$5
1
.2
$4
$4 $20
1
.8
3
.5
$2
3
7
$2
.1
.0
1
$2
$2
9
.7
.5
$2 $10
$1
1
0
$1
.2
.2
.2
.2
1
1
$1
$1
$1
$1
.8
.8
.8
.8
.8
$0
$0
$0
$0
$0
$0 $0
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21
Element Original Compressed Change in Original Modified Change in Increase in
Number Description Duration Duration Duration Resource Effort* Effort* Effort* Cost
1.1.5 Base level 20 days 12.5 days 7.5 days Sr. Analog Design Eng. 160 175 15 $1,442.30
Schematic Unix Computer 160 175 15 $28.85
DAC Cadence Software License 160 175 15 $144.23
Total 45 $1615.38
1.2.2 Block level 35 days 25 days 10 days Interm. Analog Design Eng. 560 600 40 $3,221.16
Schematic Sr. Analog Design Eng. 280 300 20 $1,923.07
CDR PLL Unix Computer 840 900 60 $115.39
Cadence Software License 840 900 60 $576.93
Total 180 $5836.55
1.3 Top Level 20 days 12 days 8 days Principle Analog Design Eng. 160 192 32 $3,923.08
Schematic Unix Computer 160 192 32 $61.54
Cadence Software License 160 192 32 $307.69
Total 96 $4292.31
Total Cost Increase $11,744.24
* - Units of effort are not shown in the table. The effort is resource x time where the resource is listed in the resource column and time
is in hours (e.g. Unix Computer-hours).
In the previous assignment, the total cost of the project was calculated to be approximately $335,000. Fifteen percent of the total cost
is approximately $50,000. The fifteen percent reduction in total duration was accomplished with a cost increase of under $12,000. In
each case, the increased effort is a result of the coordination and merging of work. The more complicated schematics (1.2.2, and 1.3)
required a larger coordination effort, thus proved more costly.
Design Database Product Design FMEA DFT analysis Base Level Base Level Cell
DesS
i gt na r D
t atabase RequP
i r reomd eu nc t Design FMEA DFT analysis Schematic R F D
Start SpR
e cei qf iuc i ar tei m
o ne n t R F D
4.0 Sp
3 e. 1c .i f1i c a t i o n 3.1.5 3.3.3 1.1.3 2.1.3
4.0 3.1.1 3.1.5 3.3.3

Schematic V C O
V C O
1.1.4 2.1.4
Base Level Base Level Cell HSP I C E

S c Bh ae smea tL i ec v e l D A C Model
SDc Ah eCm a t i c
1 . 1D. 5A C 2.1.5 3.3.2

1.1.5
Block Level Block Level Cell Mask Design Patent

S cBhl eo m
c ka tLi ec v e l CDR P L L Review Application
C DS R
c hP
emL La t i c CDR P L L
1C. D
2 .R2 P L L 2.2.2 3.2.2.1 3.1.9
1.2.2
Interm. Design Top Level Business

I nRt e rv m
i e. wD e s i g n S c hT eo m
p aLt ei cv e l C a s e
C D RR ePv Li e
Lw Schematic
3 .C2D. 1R. 2P L L 1.3 3.1.6
3.2.1.2 1.3
S S

Schematic Equalizer Review Intellectual Final Design
Equalizer Equalizer Property Plan F
R i en va il e Dwe s i g n
1.2.1 2.2.1 3.2.2.4 Review
3.1.2 3.1.10
3.1.10
Interm. Design SS + 5d
Review
Equalizer Top-level Top Level LVS/DRC Design
3.2.1.1 Floorplan Review TCoepl l L e v e l RLe Vp S

o r/ tD R C D a t aD be as si ge n
Cell Report C oD
m ap t l ae bt a
ese
3.2.2.5 2.3 3.1.8 C5o. m
0 plete
2.3 3.1.8 5.0
Schematic Tr a n s m i t t e r P L L Review SS + 5d
Buildsheet
Tr a n s m i t t e r P L L Tr a n s m i t t e r P L L
1.2.3 2.2.3 3.2.2.2
3.1.7
Interm. Design
Review
Tr a n s m i t t e r P L L
3.2.1.3
Block Level Block Level Cell Mask Design Legend

Schematic Cable Driver Review
Cable Driver Cable Driver
1.2.7 2.2.7 3.2.2.3
Critical
PC
a tr iht i c a l
E l e mPeant th
Element
Base Level Base Level Cell Interm. Design
Schematic Multiplexer 1 Review
Multiplexer 1 Cable Driver
1.1.1 2.1.1 3.2.1.7

Schematic Decoder Review
Decoder Decoder
1.2.5 2.2.5 3.2.1.5

Schematic Counter 1
Counter 1
1.1.6 2.1.6

Schematic Multiplexer 2
Multiplexer 2
1.1.2 2.1.2

Schematic Encoder Review
Encoder Encoder
1.2.6 2.2.6 3.2.1.6

Schematic Counter 2
Counter 2
1.1.7 2.1.7

Schematic LVDS Driver Review
LVDS Driver LVDS Driver
1.2.4 2.2.4 3.2.1.4
Design and CAD

Library
Development Plan
3.1.3
Project Risk
Analysis
3.1.4
Original Modified Change in
Original Modified Change in Effort Effort Effort
Scope Element Duration Duration Duration (resource- (resource- (resource- Original Modified Change in
H Number Adjust Number Description (days) (days) (days) hrs) hrs) hrs) Cost Cost Cost
1 inc. by 7% 3.1.1 Product Requirement Specification 4 4 0 96 102.72 6.72 $6,623.07 $6,623.13 $0.06
2 inc. by 7% 3.1.5 Design FMEA 3 3 0 112 119.84 7.84 $8,467.30 $8,468.79 $1.49
3 inc. 15% 1.1.1 Multiplexer 1 2 2 0 48 55.2 7.2 $1,300.00 $1,300.00 $0.00
4 dec. to 85% 1.1.6 Counter 1 4 3.4 0.6 96 81.6 -14.4 $2,830.77 $2,406.01 ($424.76)
5 inc. by 7% 1.1.2 Multiplexer 2 2 2 0 48 51.36 3.36 $1,300.00 $1,300.00 $0.00
6 inc. by 7% 1.1.7 Counter 2 5 5 0 120 128.4 8.4 $3,538.46 $3,538.46 $0.00
7 inc. to 135% 1.2.4 LVDS Driver 5 5 0 120 162 42 $3,682.69 $3,682.69 $0.00
8 inc. by 7% 3.1.3 CAD and Design Library Development Plan 2 2 0 48 51.36 3.36 $5,346.15 $5,346.15 $0.00
9 inc. by 7% 3.1.4 Project Risk Analysis 3 3 0 80 85.6 5.6 $4,813.46 $4,812.95 ($0.51)
10 inc. by 7% 3.3.3 DFT analysis 3 3 0 96 102.72 6.72 $7,834.61 $7,835.79 $1.18
11 inc. by 7% 2.1.1 Multiplexer 1 4 4 0 96 102.72 6.72 $1,869.23 $1,869.23 $0.00
12 inc. by 7% 1.2.5 Decoder 8 8 0 192 205.44 13.44 $5,661.54 $5,307.69 ($353.85)
13 inc. 15% 2.1.6 Counter 1 3 3 0 72 82.8 10.8 $1,401.92 $1,401.93 $0.01
14 dec. to 85% 2.1.2 Multiplexer 2 4 3.4 0.6 96 81.6 -14.4 $1,869.23 $1,588.85 ($280.38)
15 inc. by 7% 1.2.6 Encoder 8 8 0 192 205.44 13.44 $5,661.54 $5,661.53 ($0.01)
16 inc. by 7% 2.1.7 Counter 2 3 3 0 72 77.04 5.04 $1,401.92 $1,401.93 $0.01
17 inc. to 135% 2.2.4 LVDS Driver 3 3 0 72 97.2 25.2 $1,401.92 $1,401.94 $0.02
18 inc. by 7% 1.1.3 Rotational Frequency Detector 10 10 0 256 273.92 17.92 $8,903.85 $8,904.14 $0.29
19 inc. by 7% 1.1.4 Variable Controlled Oscillator 6 6 0 144 154.08 10.08 $4,419.23 $4,419.24 $0.01
20 inc. by 7% 1.1.5 Digital/Analog Converter 20 20 0 480 513.6 33.6 $17,230.77 $17,230.76 ($0.01)
21 inc. by 7% 1.2.1 Equalizer 30 30 0 720 770.4 50.4 $32,192.31 $32,192.32 $0.01
22 inc. by 7% 1.2.3 Transmitter PLL 40 40 0 960 1027.2 67.2 $42,923.07 $42,923.07 $0.00
23 inc. 15% 1.2.7 Cable Driver 12 12 0 304 349.6 45.6 $10,800.01 $10,800.01 $0.00
24 dec. to 85% 2.2.5 Decoder 2 1.7 0.3 48 40.8 -7.2 $934.62 $794.43 ($140.19)
25 inc. by 7% 2.2.6 Encoder 2 2 0 48 51.36 3.36 $934.62 $934.63 $0.01
26 inc. by 7% 3.2.1.4 LVDS Driver 1 1 0 17 18.19 1.19 $659.91 $659.51 ($0.40)
27 inc. to 135% 2.1.3 Rotational Frequency Detector 7 7 0 168 226.8 58.8 $4,146.15 $4,146.16 $0.01
28 inc. by 7% 2.1.4 Variable Controlled Oscillator 8 8 0 208 222.56 14.56 $5,026.92 $5,027.11 $0.19
29 inc. by 7% 2.1.5 Digital/Analog Converter 12 12 0 288 308.16 20.16 $7,107.70 $7,107.70 $0.00
30 inc. by 7% 1.2.2 CDR PLL 35 35 0 2520 2696.4 176.4 $81,711.53 $81,711.58 $0.05
31 inc. by 7% 2.2.1 Equalizer 8 8 0 208 222.56 14.56 $5,700.00 $5,700.20 $0.20
32 inc. by 7% 3.2.1.1 Equalizer 2 2 0 33 35.31 2.31 $1,992.61 $1,993.23 $0.62
33 inc. 15% 2.2.3 Transmitter PLL 7 7 0 192 220.8 28.8 $5,240.38 $5,240.38 $0.00
34 dec. to 85% 3.2.1.3 Transmitter PLL 3 2.54 0.46 49 41.65 -7.35 $2,988.76 $2,531.15 ($457.61)
35 inc. by 7% 2.2.7 Cable Driver 6 6 0 144 154.08 10.08 $3,553.85 $3,553.85 $0.00
36 inc. by 7% 3.2.1.7 Cable Driver 2 2 0 33 35.31 2.31 $1,319.53 $1,319.95 $0.42
37 inc. to 135% 3.2.1.5 Decoder 1 1 0 17 22.95 5.95 $631.06 $630.68 ($0.38)
Original Modified Change in
Original Modified Change in Effort Effort Effort
Scope Element Duration Duration Duration (resource- (resource- (resource- Original Modified Change in
H Number Adjust Number Description (days) (days) (days) hrs) hrs) hrs) Cost Cost Cost
38 inc. by 7% 3.2.1.6 Encoder 1 1 0 17 18.19 1.19 $631.06 $630.68 ($0.38)
39 inc. by 7% 2.2.2 CDR PLL 11 11 0 400 428 28 $11,215.38 $11,215.38 $0.00
40 inc. by 7% 3.2.1.2 CDR PLL 3 3 0 73 78.11 5.11 $4,286.83 $4,287.44 $0.61
41 inc. by 7% 3.2.2.4 Equalizer 1 1 0 20 21.4 1.4 $393.56 $393.75 $0.19
42 inc. by 7% 3.2.2.2 Transmitter PLL 1 1 0 20 21.4 1.4 $393.56 $393.75 $0.19
43 inc. 15% 3.2.2.3 Cable Driver 1 1 0 20 23 3 $393.56 $393.76 $0.20
44 dec. to 85% 3.2.2.1 CDR PLL 2 1.66 0.34 36 30.6 -5.4 $783.95 $652.20 ($131.75)
45 inc. by 7% 1.3 Top-level Schematic 20 20 0 512 547.84 35.84 $25,115.37 $25,114.94 ($0.43)
46 inc. by 7% 3.1.2 Intellectual Property Plan 3 3 0 112 119.84 7.84 $8,467.30 $8,468.29 $0.99
47 inc. to 135% 3.2.2.5 Top-level Floorplan Review 2 2 0 36 48.6 12.6 $783.95 $783.95 $0.00
48 inc. by 7% 3.3.2 HSPICE Model 6 6 0 160 171.2 11.2 $4,938.47 $4,937.53 ($0.94)
49 inc. by 7% 3.1.9 Patent Application 2 2 0 40 42.8 2.8 $3,050.00 $3,049.38 ($0.62)
50 inc. by 7% 3.1.6 Business Case 3 3 0 56 59.92 3.92 $2,313.46 $2,313.71 $0.25
51 inc. by 7% 3.1.10 Final Design Review 4 4 0 67 71.69 4.69 $3,985.52 $3,984.89 ($0.63)
52 inc. by 7% 2.3 Top-level Cell 12 12 0 528 564.96 36.96 $20,969.24 $20,969.40 $0.16
53 inc. by 7% 3.1.8 DRC/LVS Report 3 3 0 49 52.43 3.43 $1,171.45 $1,171.22 ($0.23)
54 inc. by 7% 3.1.7 Buildsheet 1 1 0 17 18.19 1.19 $390.68 $390.45 ($0.23)
55 inc. by 7% 3.3.1 Weekly Project Reviews 101.5 101.5 0 651 696.57 45.57 $17,064.39 $17,064.42 $0.03
457.5 455.2 2.3 11307 12193.51 886.51 409768.42 407982.31 -1786.11
ABC123 Integrated Circuit Database
ID Resource Name Initials Group Max. Units Std. Rate Ovt. Rate Cost/Use Accrue At Base Calendar Code
1 Sr. Design Manager S 1 100% $275,000.00/yr $0.00/hr $0.00 Prorated Standard
2 Principle Analog Design Engineer P 2 100% $255,000.00/yr $0.00/hr $0.00 Prorated Standard
17 Principle Applications Engineer P 3 100% $165,000.00/yr $0.00/hr $0.00 Prorated Standard
30 PC P 4 1,500% $500.00/yr $0.00/hr $0.00 Prorated Standard
4 Sr. Analog Design Engineer S 5 100% $200,000.00/yr $0.00/hr $0.00 Prorated Standard
9 Intermediate Digital Design Enginee I 6 200% $160,000.00/yr $0.00/hr $0.00 Prorated Standard
26 Staff Project Manager S 7 300% $140,000.00/yr $0.00/hr $0.00 Prorated Standard
6 Analog Design Engineer A 8 100% $145,000.00/yr $0.00/hr $0.00 Prorated Standard
29 Unix Computer U 9 1,700% $4,000.00/yr $0.00/hr $0.00 Prorated Standard
42 Cadence Software License C 10 2,500% $20,000.00/yr $0.00/hr $0.00 Prorated Standard
5 Intermediate Analog Design Engineer I 11 300% $167,500.00/yr $0.00/hr $0.00 Prorated Standard
13 Staff CAE Engineer S 12 100% $200,000.00/yr $0.00/hr $0.00 Prorated Standard
10 Sr. Mask Design Engineer S 13 100% $130,000.00/yr $0.00/hr $0.00 Prorated Standard
18 Intermediate Applications Engineer I 14 100% $125,500.00/yr $0.00/hr $0.00 Prorated Standard
12 Mask Design Engineer M 15 100% $97,500.00/yr $0.00/hr $0.00 Prorated Standard
34 B/W Printer B 16 100% $625.00/yr $0.00/hr $0.00 Prorated Standard
32 Plotter P 17 100% $2,000.00/yr $0.00/hr $0.00 Prorated Standard
19 Applications Engineer A 18 100% $105,000.00/yr $0.00/hr $0.00 Prorated Standard
25 Principle Marketing Engineer P 19 100% $180,000.00/yr $0.00/hr $0.00 Prorated Standard
31 LCD Projector L 20 300% $850.00/yr $0.00/hr $0.00 Prorated Standard
43 MSProject 98 Software License M 21 300% $500.00/yr $0.00/hr $0.00 Prorated Standard
ABC123 Integrated Circuit Database
ID Resource Name Initials Group Max. Units Std. Rate Ovt. Rate Cost/Use Accrue At Base Calendar
1 Sr. Design Manager S 1 100% $305,250.00/yr $0.00/hr $0.00 Prorated Standard
2 Principle Analog Design Engineer P 2 100% $283,050.00/yr $0.00/hr $0.00 Prorated Standard
17 Principle Applications Engineer P 3 100% $183,150.00/yr $0.00/hr $0.00 Prorated Standard
30 PC P 4 1,500% $555.00/yr $0.00/hr $0.00 Prorated Standard
4 Sr. Analog Design Engineer S 5 100% $222,000.00/yr $0.00/hr $0.00 Prorated Standard
9 Intermediate Digital Design Enginee I 6 200% $177,600.00/yr $0.00/hr $0.00 Prorated Standard
26 Staff Project Manager S 7 300% $155,400.00/yr $0.00/hr $0.00 Prorated Standard
6 Analog Design Engineer A 8 100% $160,950.00/yr $0.00/hr $0.00 Prorated Standard
29 Unix Computer U 9 1,700% $4,440.00/yr $0.00/hr $0.00 Prorated Standard
42 Cadence Software License C 10 2,500% $22,200.00/yr $0.00/hr $0.00 Prorated Standard
5 Intermediate Analog Design Engineer I 11 300% $179,225.00/yr $0.00/hr $0.00 Prorated Standard
13 Staff CAE Engineer S 12 100% $214,000.00/yr $0.00/hr $0.00 Prorated Standard
10 Sr. Mask Design Engineer S 13 100% $139,100.00/yr $0.00/hr $0.00 Prorated Standard
18 Intermediate Applications Engineer I 14 100% $134,285.00/yr $0.00/hr $0.00 Prorated Standard
12 Mask Design Engineer M 15 100% $104,325.00/yr $0.00/hr $0.00 Prorated Standard
34 B/W Printer B 16 100% $668.75/yr $0.00/hr $0.00 Prorated Standard
32 Plotter P 17 100% $2,140.00/yr $0.00/hr $0.00 Prorated Standard
19 Applications Engineer A 18 100% $112,350.00/yr $0.00/hr $0.00 Prorated Standard
25 Principle Marketing Engineer P 19 100% $192,600.00/yr $0.00/hr $0.00 Prorated Standard
31 LCD Projector L 20 300% $909.50/yr $0.00/hr $0.00 Prorated Standard
43 MSProject 98 Software License M 21 300% $495.00/yr $0.00/hr $0.00 Prorated Standard
ID WBS H numbers % Complete Task Name Duration Float Start Finish
0 0 0 40% ABC123 Integrated Circuit Database 102.34 days 0 days Mon 1/6/03 Wed 5/28/03
1 1 0 43% Circuit Design Schematics 79.48 days 0 days Thu 1/9/03 Thu 5/1/03
2 1.1 0 46% Base-level Schematics 23.75 days 4.8 days Thu 1/9/03 Wed 2/12/03
3 1.1.1 3 50% Multiplexer 1 1.88 days 0 days Thu 1/9/03 Mon 1/13/03
4 1.1.2 5 50% Multiplexer 2 1.88 days 0 days Thu 1/9/03 Mon 1/13/03
5 1.1.3 18 44% Rotational Frequency Detector 9.69 days 0 days Thu 1/16/03 Thu 1/30/03
6 1.1.4 19 45% Variable Controlled Oscillator 5.75 days 0 days Thu 1/16/03 Fri 1/24/03
7 1.1.5 20 46% Digital/Analog Converter 18.75 days 0 days Thu 1/16/03 Wed 2/12/03
8 1.1.6 4 50% Counter 1 3.75 days 0 days Thu 1/9/03 Wed 1/15/03
9 1.1.7 6 49% Counter 2 4.75 days 0 days Thu 1/9/03 Thu 1/16/03
10 1.2 0 43% Block-level Schematics 57.92 days 0.9 days Thu 1/9/03 Tue 4/1/03
11 1.2.1 21 43% Equalizer 28.13 days 0 days Thu 1/16/03 Tue 2/25/03
12 1.2.2 30 41% CDR PLL 34.17 days 0 days Wed 2/12/03 Tue 4/1/03
13 1.2.3 22 43% Transmitter PLL 37.63 days 0 days Thu 1/16/03 Tue 3/11/03
14 1.2.4 7 49% LVDS Driver 4.81 days 0 days Thu 1/9/03 Thu 1/16/03
15 1.2.5 12 46% Decoder 7.56 days 0 days Wed 1/15/03 Mon 1/27/03
16 1.2.6 15 46% Encoder 7.56 days 0 days Thu 1/16/03 Tue 1/28/03
17 1.2.7 23 42% Cable Driver 11.5 days 0 days Thu 1/16/03 Mon 2/3/03
18 1.3 45 32% Top-level Schematic 18.75 days 0 days Fri 4/4/03 Thu 5/1/03
19 2 0 38% Mask Design Cells 92.73 days 0 days Mon 1/13/03 Thu 5/22/03
20 2.1 0 43% Base-level Cells 33.31 days 26.07 days Mon 1/13/03 Thu 2/27/03
21 2.1.1 11 45% Multiplexer 1 3.81 days 5.63 days Mon 1/13/03 Fri 1/17/03
22 2.1.2 14 45% Multiplexer 2 3.85 days 6.59 days Mon 1/13/03 Fri 1/17/03
23 2.1.3 27 42% Rotational Frequency Detector 6.69 days 36.54 days Thu 1/30/03 Mon 2/10/03
24 2.1.4 28 42% Variable Controlled Oscillator 7.69 days 0 days Fri 1/24/03 Wed 2/5/03
25 2.1.5 29 42% Digital/Analog Converter 11.44 days 22.73 days Wed 2/12/03 Thu 2/27/03
26 2.1.6 13 45% Counter 1 2.88 days 4.69 days Wed 1/15/03 Mon 1/20/03
27 2.1.7 16 45% Counter 2 2.88 days 4.69 days Thu 1/16/03 Tue 1/21/03
28 2.2 0 34% Block-level Cells 63.54 days 18.52 days Thu 1/16/03 Wed 4/16/03
29 2.2.1 31 32% Equalizer 7.56 days 0 days Tue 2/25/03 Fri 3/7/03
30 2.2.2 39 32% CDR PLL 10.44 days 0 days Tue 4/1/03 Wed 4/16/03
31 2.2.3 33 32% Transmitter PLL 6.63 days 0 days Tue 3/11/03 Wed 3/19/03
32 2.2.4 17 45% LVDS Driver 2.88 days 75.54 days Thu 1/16/03 Tue 1/21/03
33 2.2.5 24 43% Decoder 1.88 days 70.04 days Mon 1/27/03 Tue 1/28/03
34 2.2.6 25 43% Encoder 1.88 days 69.04 days Tue 1/28/03 Wed 1/29/03
35 2.2.7 35 32% Cable Driver 5.69 days 0 days Mon 2/3/03 Mon 2/10/03
36 2.3 52 32% Top-level Cell 11.38 days 0 days Tue 5/6/03 Thu 5/22/03
37 3 0 36% Documentation 102.34 days 0 days Mon 1/6/03 Wed 5/28/03
38 3.1 0 41% NPPRS deliverables 101.23 days 1.11 days Mon 1/6/03 Tue 5/27/03
39 3.1.1 1 50% Product Requirement Specification 3.75 days 0 days Mon 1/6/03 Thu 1/9/03
40 3.1.2 46 42% Intellectual Property Plan 2.13 days 16.63 days Fri 4/4/03 Tue 4/8/03
41 3.1.3 8 50% CAD and Design Library Development Plan 1.88 days 58.85 days Thu 1/9/03 Mon 1/13/03
42 3.1.4 9 52% Project Risk Analysis 2.69 days 58.04 days Thu 1/9/03 Tue 1/14/03
43 3.1.5 2 56% Design FMEA 2.5 days 0 days Thu 1/9/03 Tue 1/14/03
44 3.1.6 50 32% Business Case 2.81 days 16.3 days Thu 5/1/03 Tue 5/6/03
45 3.1.7 54 32% Buildsheet 0.94 days 0 days Tue 5/13/03 Wed 5/14/03
46 3.1.8 53 31% DRC/LVS Report 2.88 days 0 days Thu 5/22/03 Tue 5/27/03
ID WBS H numbers % Complete Task Name Duration Float Start Finish
47 3.1.9 49 32% Patent Application 1.88 days 17.24 days Thu 5/1/03 Mon 5/5/03
48 3.1.10 51 32% Final Design Review 3.75 days 0 days Thu 5/1/03 Tue 5/6/03
49 3.2 0 32% Supplemental Design Documents 65.48 days 0 days Thu 1/16/03 Fri 4/18/03
50 3.2.1 0 33% Intermediate Design Reviews 55.92 days 6 days Thu 1/16/03 Fri 4/4/03
51 3.2.1.1 32 32% Equalizer 1.88 days 25.73 days Tue 2/25/03 Thu 2/27/03
52 3.2.1.2 40 32% CDR PLL 2.81 days 0 days Tue 4/1/03 Fri 4/4/03
53 3.2.1.3 34 32% Transmitter PLL 2.81 days 0 days Tue 3/11/03 Fri 3/14/03
54 3.2.1.4 26 43% LVDS Driver 0.94 days 0 days Thu 1/16/03 Fri 1/17/03
55 3.2.1.5 37 32% Decoder 0.94 days 0 days Mon 1/27/03 Mon 1/27/03
56 3.2.1.6 38 32% Encoder 0.94 days 0 days Tue 1/28/03 Tue 1/28/03
57 3.2.1.7 36 31% Cable Driver 1.94 days 0 days Mon 2/3/03 Wed 2/5/03
58 3.2.2 0 31% Mask Design Reviews 48.1 days 0 days Mon 2/10/03 Fri 4/18/03
59 3.2.2.1 44 31% CDR PLL 1.94 days 0 days Wed 4/16/03 Fri 4/18/03
60 3.2.2.2 42 31% Transmitter PLL 0.97 days 0 days Thu 3/20/03 Thu 3/20/03
61 3.2.2.3 43 31% Cable Driver 0.97 days 0 days Mon 2/10/03 Tue 2/11/03
62 3.2.2.4 41 31% Equalizer 0.97 days 0 days Fri 3/7/03 Mon 3/10/03
63 3.2.2.5 47 31% Top-level Floorplan Review 1.94 days 0 days Fri 4/11/03 Tue 4/15/03
64 3.3 0 34% Miscellaneous Documents 101.34 days 0 days Tue 1/7/03 Wed 5/28/03
65 3.3.1 55 32% Weekly Project Reviews 101.34 days 0 days Tue 1/7/03 Wed 5/28/03
66 3.3.1.1 0 100% Weekly Project Reviews 1 12 hrs 0 hrs Tue 1/7/03 Wed 1/8/03
73 3.3.1.8 0 0% Weekly Project Reviews 8 10.75 hrs 520 hrs Tue 2/25/03 Wed 2/26/03
87 3.3.2 48 33% HSPICE Model 5.5 days 13.61 days Thu 5/1/03 Thu 5/8/03
88 3.3.3 10 56% DFT analysis 2.5 days 0 days Tue 1/14/03 Thu 1/16/03
89 4 0 0% Design Database Start 0 days 0 days Mon 1/6/03 Mon 1/6/03
90 5 0 0% Design Database Complete 0 days 0 days Wed 5/28/03 Wed 5/28/03

Original
Resource Resource Std. Asstm J Resource
Number Resource Rate ($/yr) Change Std. Rate ($/yr) $/hr
1 Sr. Design Manager $275,000.00 1.11 $305,250.00 $146.75
2 Principle Analog Design Engineer $255,000.00 1.11 $283,050.00 $136.08
3 Principle Applications Engineer $165,000.00 1.11 $183,150.00 $88.05
4 PC $500.00 1.11 $555.00 $0.27
5 Sr. Analog Design Engineer $200,000.00 1.11 $222,000.00 $106.73
6 Intermediate Digital Design Engineer $160,000.00 1.11 $177,600.00 $85.38
7 Staff Project Manager $140,000.00 1.11 $155,400.00 $74.71
8 Analog Design Engineer $145,000.00 1.11 $160,950.00 $77.38
9 Unix Computer $4,000.00 1.11 $4,440.00 $2.13
10 Cadence Software License $20,000.00 1.11 $22,200.00 $10.67
11 Intermediate Analog Design Engineer $167,500.00 1.07 $179,225.00 $86.17
12 Staff CAE Engineer $200,000.00 1.07 $214,000.00 $102.88
13 Sr. Mask Design Engineer $130,000.00 1.07 $139,100.00 $66.88
14 Intermediate Applications Engineer $125,500.00 1.07 $134,285.00 $64.56
15 Mask Design Engineer $97,500.00 1.07 $104,325.00 $50.16
16 B/W Printer $625.00 1.07 $668.75 $0.32
17 Plotter $2,000.00 1.07 $2,140.00 $1.03
18 Applications Engineer $105,000.00 1.07 $112,350.00 $54.01
19 Principle Marketing Engineer $180,000.00 1.07 $192,600.00 $92.60
20 LCD Projector $850.00 1.07 $909.50 $0.44
21 MSProject 98 Software License $500.00 0.99 $495.00 $0.24
Original Schedule Increased resource cost schedule
Cost
Cost of increase of Calculated
Cost of remaining remaining remaining new EAC
H Number Task EAC - J ACWP - J work EAC - Chg ACWP - Chg work work value EAC-Workmod delta EAC
1 Product Requirement Specification $6,623.08 $5,029.01 $1,594.07 $7,351.62 $5,582.19 $1,769.43 $175.36 $7,176.26 $7,174.97 ($1.29)
2 Design FMEA $8,467.31 $5,588.48 $2,878.83 $9,398.71 $6,203.21 $3,195.50 $316.67 $9,082.04 $9,013.41 ($68.63)
3 Multiplexer 1 $1,300.00 $611.00 $689.00 $1,443.00 $678.21 $764.79 $75.79 $1,367.21 $1,352.81 ($14.40)
4 Counter 1 $2,830.78 $1,330.46 $1,500.32 $3,142.14 $1,476.80 $1,665.34 $165.02 $2,977.12 $2,945.75 ($31.37)
5 Multiplexer 2 $1,300.00 $611.00 $689.00 $1,443.00 $678.21 $764.79 $75.79 $1,367.21 $1,352.81 ($14.40)
6 Counter 2 $3,538.46 $1,663.07 $1,875.39 $3,927.68 $1,846.01 $2,081.67 $206.28 $3,721.40 $3,731.29 $9.89
7 LVDS Driver $3,682.69 $1,730.86 $1,951.83 $3,958.94 $1,860.70 $2,098.24 $146.41 $3,812.53 $3,810.48 ($2.05)
8 CAD and Design Library Development Plan $5,346.15 $3,109.23 $2,236.92 $5,883.45 $3,403.52 $2,479.93 $243.01 $5,640.44 $5,600.62 ($39.82)
9 Project Risk Analysis $4,813.45 $3,012.51 $1,800.94 $5,342.95 $3,343.90 $1,999.05 $198.11 $5,144.84 $5,155.51 $10.67
10 DFT analysis $7,834.61 $5,183.67 $2,650.94 $8,638.50 $5,726.65 $2,911.85 $260.91 $8,377.59 $8,379.20 $1.61
11 Multiplexer 1 $1,869.23 $803.77 $1,065.46 $2,014.85 $866.38 $1,148.47 $83.01 $1,931.84 $1,920.40 ($11.44)
12 Decoder $5,661.53 $2,434.46 $3,227.07 $6,284.29 $2,702.24 $3,582.05 $354.98 $5,929.31 $5,940.62 $11.31
13 Counter 1 $1,401.93 $602.83 $799.10 $1,511.14 $649.79 $861.35 $62.25 $1,448.89 $1,448.17 ($0.72)
14 Multiplexer 2 $1,869.23 $803.77 $1,065.46 $2,014.85 $866.38 $1,148.47 $83.01 $1,931.84 $1,939.28 $7.44
15 Encoder $5,661.53 $2,434.46 $3,227.07 $6,284.29 $2,702.24 $3,582.05 $354.98 $5,929.31 $5,940.62 $11.31
16 Counter 2 $1,401.93 $602.83 $799.10 $1,511.14 $649.79 $861.35 $62.25 $1,448.89 $1,448.17 ($0.72)
17 LVDS Driver $1,401.93 $602.83 $799.10 $1,511.14 $649.79 $861.35 $62.25 $1,448.89 $1,448.17 ($0.72)
18 Rotational Frequency Detector $8,903.84 $4,705.57 $4,198.27 $9,625.57 $5,112.38 $4,513.19 $314.92 $9,310.65 $9,378.14 $67.49
19 Variable Controlled Oscillator $4,419.24 $1,900.27 $2,518.97 $4,750.73 $2,042.81 $2,707.92 $188.95 $4,561.78 $4,552.78 ($9.00)
20 Digital/Analog Converter $17,230.76 $7,409.23 $9,821.53 $19,126.16 $8,224.25 $10,901.91 $1,080.38 $18,045.78 $17,930.77 ($115.01)
21 Equalizer $32,192.32 $12,876.93 $19,315.39 $35,733.46 $14,293.39 $21,440.07 $2,124.68 $33,608.78 $33,500.13 ($108.65)
22 Transmitter PLL $42,923.07 $17,169.23 $25,753.84 $47,644.61 $19,057.84 $28,586.77 $2,832.93 $44,811.68 $44,815.71 $4.03
23 Cable Driver $10,800.01 $5,496.93 $5,303.08 $11,678.77 $5,977.90 $5,700.87 $397.79 $11,280.98 $11,282.89 $1.91
24 Decoder $934.62 $373.85 $560.77 $1,007.42 $402.97 $604.45 $43.68 $963.74 $944.46 ($19.28)
25 Encoder $934.62 $373.85 $560.77 $1,007.42 $402.97 $604.45 $43.68 $963.74 $944.46 ($19.28)
26 LVDS Driver $659.91 $264.14 $395.77 $706.73 $282.88 $423.85 $28.08 $678.65 $662.41 ($16.24)
27 Rotational Frequency Detector $4,146.16 $1,658.46 $2,487.70 $4,462.24 $1,784.90 $2,677.34 $189.64 $4,272.60 $4,263.03 ($9.57)
28 Variable Controlled Oscillator $5,026.92 $2,783.84 $2,243.08 $5,408.35 $2,990.53 $2,417.82 $174.74 $5,233.61 $5,250.93 $17.32
29 Digital/Analog Converter $7,107.70 $2,843.08 $4,264.62 $7,649.54 $3,059.82 $4,589.72 $325.10 $7,324.44 $7,290.97 ($33.47)
30 CDR PLL $81,711.53 $32,684.61 $49,026.92 $88,895.96 $35,558.38 $53,337.58 $4,310.66 $84,585.30 $84,781.86 $196.56
31 Equalizer $5,700.00 $3,083.08 $2,616.92 $6,206.99 $3,386.21 $2,820.78 $203.86 $6,003.13 $5,986.62 ($16.51)
32 Equalizer $1,992.61 $597.99 $1,394.62 $2,211.79 $663.76 $1,548.03 $153.41 $2,058.38 $2,073.24 $14.86
33 Transmitter PLL $5,240.38 $2,950.58 $2,289.80 $5,711.53 $3,243.34 $2,468.19 $178.39 $5,533.14 $5,522.64 ($10.50)
34 Transmitter PLL $2,988.77 $896.84 $2,091.93 $3,317.51 $995.48 $2,322.03 $230.10 $3,087.41 $3,110.19 $22.78
35 Cable Driver $3,553.85 $1,066.15 $2,487.70 $3,824.77 $1,147.43 $2,677.34 $189.64 $3,635.13 $3,625.56 ($9.57)
36 Cable Driver $1,319.53 $396.07 $923.46 $1,413.14 $424.17 $988.97 $65.51 $1,347.63 $1,368.98 $21.35
37 Decoder $631.08 $189.54 $441.54 $700.46 $210.36 $490.10 $48.56 $651.90 $656.71 $4.81
38 Encoder $631.08 $189.54 $441.54 $700.46 $210.36 $490.10 $48.56 $651.90 $656.71 $4.81
39 CDR PLL $11,215.38 $6,595.38 $4,620.00 $12,133.38 $7,161.55 $4,971.83 $351.83 $11,781.55 $11,770.18 ($11.37)
40 CDR PLL $4,286.84 $1,286.27 $3,000.57 $4,681.07 $1,404.54 $3,276.53 $275.96 $4,405.11 $4,388.52 ($16.59)
41 Equalizer $393.58 $119.73 $273.85 $421.74 $128.29 $293.45 $19.60 $402.14 $408.67 $6.53
42 Transmitter PLL $393.58 $119.73 $273.85 $421.74 $128.29 $293.45 $19.60 $402.14 $408.67 $6.53
43 Cable Driver $393.58 $119.73 $273.85 $421.74 $128.29 $293.45 $19.60 $402.14 $408.67 $6.53
44 CDR PLL $783.95 $237.41 $546.54 $840.07 $254.41 $585.66 $39.12 $800.95 $813.92 $12.97
45 Top-level Schematic $25,115.38 $10,092.31 $15,023.07 $27,816.53 $11,140.92 $16,675.61 $1,652.54 $26,163.99 $26,327.64 $163.65
46 Intellectual Property Plan $8,467.31 $3,567.12 $4,900.19 $9,398.69 $3,959.49 $5,439.20 $539.01 $8,859.68 $8,873.84 $14.16
47 Top-level Floorplan Review $783.95 $237.41 $546.54 $840.07 $254.41 $585.66 $39.12 $800.95 $813.92 $12.97
48 HSPICE Model $4,938.45 $2,658.45 $2,280.00 $5,384.77 $2,921.82 $2,462.95 $182.95 $5,201.82 $5,117.48 ($84.34)
49 Patent Application $3,050.01 $1,232.31 $1,817.70 $3,385.51 $1,367.86 $2,017.65 $199.95 $3,185.56 $3,247.28 $61.72
50 Business Case $2,313.47 $1,109.43 $1,204.04 $2,540.24 $1,206.53 $1,333.71 $129.67 $2,410.57 $2,427.78 $17.21
51 Final Design Review $3,985.51 $1,196.28 $2,789.23 $4,423.88 $1,327.83 $3,096.05 $306.82 $4,117.06 $4,147.45 $30.39
52 Top-level Cell $20,969.22 $10,125.37 $10,843.85 $22,722.93 $11,073.30 $11,649.63 $805.78 $21,917.15 $21,888.53 ($28.62)
53 DRC/LVS Report $1,171.46 $351.65 $819.81 $1,255.31 $376.82 $878.49 $58.68 $1,196.63 $1,203.02 $6.39
54 Buildsheet $390.69 $117.42 $273.27 $418.65 $125.82 $292.83 $19.56 $399.09 $392.51 ($6.58)
55 Weekly Project Reviews $17,064.41 $5,120.41 $11,944.00 $18,937.80 $5,682.45 $13,255.35 $1,311.35 $17,626.45 $17,625.72 ($0.73)
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PROJECT

0.0 ABC123 Integrated circuit database

Buildsheet A document that graphically represents the package assembly

0.0 ABC123 Integrated Circuit Database

0.0 ABC123 Integrated Circuit Database

Project Cost Comparison by Level

Base-level Schematic: Counter1 Product Requirement Specification Base-level Cell: Counter1

Base Level Base Level Cell

Base Level Base Level Cell HSPICE

Block Level Block Level Cell Mask Design Patent

Interm. Design Top Level Business

Block Level Block Level Cell Mask Design

Block Level Block Level Cell Mask Design

Block Level Block Level Cell Mask Design

Base Level Base Level Cell Interm. Design

Block Level Block Level Cell Interm. Design

Base Level Base Level Cell

Base Level Base Level Cell

Block Level Block Level Cell Interm. Design

Base Level Base Level Cell

Block Level Block Level Cell Interm. Design

Design and CAD

4 1.1.2 Multiplexer 2 2 days 0 days Wed 1/8/03 Thu 1/9/03 39 16,22

33 2.2.5 Decoder 2 days 73 days Fri 1/24/03 Mon 1/27/03 15,21,26 36 2.

43 3.1.5 Design FMEA 2 days 0 days Wed 1/8/03 Thu 1/9/03 39 88

46 3.1.8 DRC/LVS Report 3 days 0 days Tue 5/27/03 Thu 5/29/03 36 90 3

52 3.2.1.2 CDR PLL 3 days 0 days Wed 4/2/03 Fri 4/4/03 12 18

53 3.2.1.3 Transmitter PLL 3 days 15 days Wed 3/12/03 Fri 3/14/03 13 18

54 3.2.1.4 LVDS Driver 1 day 57 days Wed 1/15/03 Wed 1/15/03 14 18

55 3.2.1.5 Decoder 1 day 50 days Fri 1/24/03 Fri 1/24/03 15 18

56 3.2.1.6 Encoder 1 day 49 days Mon 1/27/03 Mon 1/27/03 16 18

57 3.2.1.7 Cable Driver 2 days 44 days Fri 1/31/03 Mon 2/3/03 17 18 3.

60 3.2.2.2 Transmitter PLL 1 day 34 days Fri 3/21/03 Fri 3/21/03 31 36

61 3.2.2.3 Cable Driver 1 day 63 days Mon 2/10/03 Mon 2/10/03 35 36

62 3.2.2.4 Equalizer 1 day 43 days Mon 3/10/03 Mon 3/10/03 29 36

Unix Computer Cadence Software License Principle Analog Design Engineer

Intermediate Analog Design Engineer

Project Duration (weeks)

Cumulative Cost ($K US)

Cumulative Cost (k$ US)

Cumulative Cost (k$ US)

Cumulative Cost (k$ US)

Base Level Base Level Cell

Base Level Base Level Cell HSP I C E

1 . 1D. 5A C 2.1.5 3.3.2

Block Level Block Level Cell Mask Design Patent

Interm. Design Top Level Business

Block Level Block Level Cell Mask Design

3.2.1.1 Floorplan Review TCoepl l L e v e l RLe Vp S

Block Level Block Level Cell Mask Design Legend

Block Level Block Level Cell Interm. Design

Base Level Base Level Cell

Base Level Base Level Cell

Block Level Block Level Cell Interm. Design

Base Level Base Level Cell

Block Level Block Level Cell Interm. Design

Design and CAD

37 3 0 36% Documentation 102.34 days 0 days Mon 1/6/03 Wed 5/28/03

89 4 0 0% Design Database Start 0 days 0 days Mon 1/6/03 Mon 1/6/03

90 5 0 0% Design Database Complete 0 days 0 days Wed 5/28/03 Wed 5/28/03

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