A Matlab/Simulink Model for Capacitor Voltages Balancing in

Modular Multilevel Converters

Nada Ahmed, Ahmed Massoud

Qatar University, Qatar, Qatar University, nada.hussein@qu.edu.qa

Keywords: MMC, Sorting algorithm, voltage balancing, and STATCOM [6]. One of the main challenges of the MMC
fundamental switching frequency, and PD-PWM. is to keep the submodule (SM) capacitor voltages balanced at
their nominal values. Hence, several balancing techniques
Abstract have been developed in the literature [9-19].
In [9], a developed predictive algorithm for capacitor
The modular multilevel converter (MMC) is a potential voltage balancing which aims to combine a low switching
candidate for high power applications due to its modularity, frequency with a low capacitor voltage ripple is presented.
availability, and enhanced power quality features. This algorithm evaluates the amount of charge that should be
Nevertheless, the voltage balancing of the floating capacitors stored in each SM capacitor during the fundamental
in the series-connected submodules (SMs) of the MMC frequency period. The study in [10] shows a model predictive
represents a bottleneck in this type of multilevel converters. control strategy that takes the advantage of a cost function
minimization topology to eliminate the circulating currents
In this paper, a generalized voltage balancing technique for
and carry out the voltage balancing problem of the MMC.
MMCs is modelled using Matlab/Simulink platform. The
Furthermore, in [6] a methodology of fast voltage balancing
presented model can be simply extended to any number of control based on average comparison and a fast numerical
levels where the switching frequency can be as low as the simulation model for MMC has been introduced. In [11], a
fundamental frequency. A 9-level MMC is modelled and new modulation method is based on selective virtual loop
simulated using half bridge topology where the switches are mapping in order to achieve dynamic capacitor voltage
controlled using phase disposition carrier-based pulse width balance without the need for an external compensation signal.
modulation (PD-PWM) scheme to validate the proposed However, in [12] an improved phase disposition pulse width
concept. modulation (PWM) for MMCs based on the selective loop
bias mapping method is proposed for balancing the capacitor
1 Introduction voltages. Furthermore, in [13] a stable voltage control method
to realize both averaging and balancing controls of floating
Multilevel converters have attracted significant interest in capacitors. A combination of averaging and balancing
the last three decades, particularly in high power applications. controls allows the MMC to achieve voltage balancing
With off-the-shelf semiconductor devices, multilevel without external circuit, but using PI controllers, is presented
converters have a higher voltage capability when compared in [14]. In addition, an internal and external voltage balancing
with conventional two-level converters, avoiding series method characterized for large scale MMCs is proposed in
connection of semiconductor devices’ problems (static and [15]. This proposed technique is beneficial for large scale
dynamic voltage sharing), introducing lower dv/dt, and MMC modeling as each arm is divided into valve groups
enhanced harmonic performance with reduced switching (VG) each of N SMs. The internal voltage balancing
frequency [1],[2]. However, increasing the number of levels technique is responsible for balancing the SMs within each
increases the control complexity and introduces voltage VG. However, the external voltage balancing is responsible
unbalance problems in most of multilevel converter types. for balancing the average SM voltages of each VG within the
The main types of the multilevel converters are diode- arm. In [16], the SMs of the MMC are modulated
clamped [3], flying capacitors [4], cascaded H-bridge [4], [5], independently as they are controlled using phase shifted
and modular multilevel converter (MMC) [6],[7]. The carriers PWM (PSC-PWM), hence, the voltage balancing of
aforementioned multilevel converters have pros and cons the capacitors can be attained by adjusting the reference
when considering the requirements of semiconductor devices signal of each SM. In [17] a sorting algorithm is presented in
and passive elements, the required isolated DC supplies, order to reduce the switching commutations of each SM also
modularity, and capacitor voltages’ balancing. However, the for voltage balancing control, in which a practical and
MMC shown in Figure 1 has become one of the most effective mitigation measure is integrated to keep the energy
attractive and promising multilevel converter topologies balance while avoiding the undesired switching stresses. In
especially for high voltage direct current (HVDC) [18], an analytical discussion of the voltage balancing control
transmission systems and high-power motor drives [6]. Due approach with rotation of switching angles is presented. In
to its scalability, modularity, and fault ride through capability, [19], a novel modulation and capacitor voltage control
the MMC has been addressed for various applications in method for the MMC. Using this approach, the SMs can be
literature as grid connection of renewable energy sources [8] self-balanced by periodically swapping the pulse patterns.

1
 Typically, the complexity of capacitor voltage balancing ‫ܫ‬௖௜௥௖௝ is the circulating current of one leg where ݅௖௜௥௖௝ can be
increases as the number of levels increases. In this paper, a expressed as:
generalized voltage balancing technique for MMCs is ‫ݑ݆ܫ‬൅‫݈݆ܫ‬
modelled using Matlab/Simulink platform. The presented
‫ܫ‬௖௜௥௖௝ = ଶ
(5)
model can be simply extended to any number of levels. As Furthermore, the voltage relationship of the MMC based on
well as the modelled approach has been tested for different the Kirchhoff’s voltage law can be described as [21]:
switching frequencies (modulation frequency ratios) ݀‫݈݆ܫ‬ ݀‫ݑ݆ܫ‬
ܸௗ௖ ൌ ൬ܸ௝௟ ൅ ‫ܮ‬ ൰ ൅ ൬ܸ௝௨ ൅ ‫ܮ‬ ൰
downward to the fundamental switching frequency. MMCs ݀‫ݐ‬ ݀‫ݐ‬
can be controlled using several PWM switching schemes as ݀ሺ‫ ݑ݆ܫ‬൅ ‫݈݆ܫ‬ሻ
carrier-based PWM [20], [21], space vector modulation [22], ܸௗ௖ ൌ ൫ܸ௝௟ ൅  ܸ௝௨ ൯ ൅ ‫ܮ‬
݀‫ݐ‬
selective harmonic elimination [23], and nearest level control
(NLC) [24]. Carrier-based PWM can be classified according ݀‫݆ܿݎ݅ܿܫ‬
ܸௗ௖ ൌ ൫ܸ௝௟ ൅  ܸ௝௨ ൯ ൅ ʹ‫ܮ‬ (6)
to the carrier type as phase disposition (PD) [21], phase ݀‫ݐ‬
opposition disposition (POD) [21], alternative phase ௗூ௖௜௥௖௝ ଵ
opposition disposition (APOD) [21], and PSC-PWM [20]. A ‫ܮ‬ ൌ  ሺܸௗ௖ - ܸ௝௨ െ ܸ௝௟ )
ௗ௧ ଶ (7)
9-level MMC is modeled and simulated using half bridge SM
ଵ
where the switches are controlled using PD-PWM scheme to e = ሺܸ௝௟ െ ܸ௝௨ )
validate the proposed concept.
ଶ (8)
ௗூ௖௜௥௖௝ ଵ
ܸܿ݅‫ ݆ܿݎ‬ൌ ‫ܮ‬ ൌ  ሺܸௗ௖ - ܸ௝௨ െ ܸ௝௟ )
2 Modular Multilevel Converter (MMC) ௗ௧ ଶ (9)

2.1. MMC topology and operation ଵ

The typical structure of an MMC is shown in Figure 1, and
the configuration of the SM is presented with details in
Figures 1and 2, where the half-bridge SM has been used to
model the MMC. Each SM is a simple chopper cell
composed of two semiconductor devices S1 and S2, two anti-
parallel diodes D1 and D2, and a capacitor C. Also, each
phase or leg has upper and lower arms, each arm is
constructed by a number N-1 of SMs connected in series for
N-level MMC. Every arm has an inductor to protect the
switches from the inrush current caused by the capacitors as
well as it limits the circulating current during normal
operation [18]. In general, the number of cells in an MMC is
dependent on the DC link voltage and the ratings for each cell.
The working states of the SM are shown in Table 1, where
every SM has two states ON and OFF, based on that the
corresponding output voltage ܸௌெ is ܸ௖ or 0 depending on the
switches’ status [25]. The charging and the discharging of
the capacitor voltages basically depend on the direction of the
current flowing in the SMs. If the current flows in the
positive direction (into the SM), then the capacitors are
charged, whereas the capacitors are discharged if the current
flows in the inverse direction (out of the SM) as illustrated in
Figure 2.
2.2. MMC Mathematical Model
According to [20],[21] and Figure 1, the arm currents in the
MMC can be described as:
ଵ ௗூ௝௟ ଵ ௗூ௝௨
ܸ௝ = ቂܸ௝௟ ൅ ‫ܮ‬ ቃ െ  ቂܸ௝௨ ൅ ‫ܮ‬ ቃ (1)
ଶ ௗ௧ ଶ ௗ௧
ௗሺூ௝௟ିூ௝௨ሻ
ʹܸ௝ = (ܸ௝௟ െ ܸ௝௨ )+ ‫ܮ‬ (2)
ௗ௧
‫ܫ‬௝ ൌ ‫ ݑ݆ܫ‬െ ‫݈݆ܫ‬ (3)
ʹܸ௝ = (ܸ௝௟ െ ܸ௝௨ ) - ‫ܮ‬
ௗூೕ
(4)
ௗ௧
where ‫ܫ‬௝௨ and ‫ܫ‬௝௟ are the upper and lower arm currents of
phase j ( j=a,b,c) respectively, ‫ܫ‬௝ is the current of phase j and
ܸ௝௨ = ܸௗ௖ െ ݁ െ ܸܿ݅‫݆ܿݎ‬
ଶ
(10)
ଵ
ܸ௝௟ = ܸௗ௖ + ݁ െ ܸܿ݅‫݆ܿݎ‬
ଶ
where ܸௗ௖ is the input DC voltage. ܸ௝௨ and ܸ௝௟ are the total
upper and lower SMs voltages as shown in figure 1.
2.3. Modulation Technique
MMCs can be controlled using different carrier-based
PWM schemes. Generally, PD-PWM is not preferred for
MMC as it causes uneven power distribution between the
SMs [26]. However, it is used for HVDC applications as it
allows the operation of MMCs at low frequency modulation.
In contrast, PSC-PWM is a commonly used modulation
technique in MMCs as the stresses on the switches and the
power handled by each SM are evenly distributed [26].
Therefore, the balancing of the capacitor voltages can be
easily achieved. PSC-PWM might not operate at a very low
frequency modulation frequency ratio as ݉௙ = 2, but it can
operate at low ݉௙ that would be equivalent to the PD-PWM.
Nevertheless, both techniques allow the operation at high ݉௙
for low voltage applications, where ݉௙ is defined as.
݂௖௔௥௥௜௘௥
݉௙  ൌ  (6)
݂௙௨௡ௗ௔௠௘௡௧௔௟
Hence, PD-PWM has been applied in this paper for the
MMC control. In an N-level MMC, each arm with (N-1) SMs
requires (N-1) triangular carrier waves with a switching
frequency of fs. The basic concept of PD-PWM applied in this
paper is illustrated in Figure 3. This triangular carrier is then
compared with a sinusoidal reference signal in order to
generate pulses that controls the IGBTs. The modulating
signals in the upper and lower arms can be expressed as:
ͳ
݊௨ ൌ  ሺͳ െ ݉௔ •‹ሺ߱‫ݐ‬ሻሻ
ʹ
ͳ (7)
݊௟ ൌ  ሺͳ ൅ ݉௔ •‹ሺ߱‫ݐ‬ሻሻ
ʹ
where ݉௔ is the modulation index.

2
 3 Capacitor Voltage Balancing Technique
One of the main technical challenges associated with the
control of the MMC is to keep the SM capacitor voltages
balanced at their nominal values. Hence, several voltage
balancing approaches have been presented as mentioned
previously. A Matlab/Simulink model for capacitor voltage
balancing of MMC is presented in this paper. The presented
balancing technique is mainly based on measuring the
capacitor voltages and sorting them in either ascending or
descending order. Then, based on the direction of the arm
currents and the number of required state of the SMs within
each control period, a number of SMs are inserted/bypassed
[25]. The balancing technique consists of a sorting algorithm
as shown in Figure 4(a), de-multiplexer blocks to switch the
modulation control signals between the half-bridge cells in
each arm and an adder block that links the chopper cells with
the different de-mux outputs as shown in Figure 4 (b).
In this technique, the PD-PWM control signals are always
in swapping mode to charge the less capacitor voltage in case
of positive arm current (‫ܫ‬௔௥௠ ൐ Ͳ), where in this case the
capacitor voltages are sorted in ascending order. In contrast,
PD-PWM control signals are used to discharge the capacitor
with the higher voltage value in case of negative arm current
(‫ܫ‬௔௥௠ ൏ Ͳ). In this case the capacitor voltages are sorted in
descending order. Each de-mux used has one input, N outputs,
and control signals depending on a number of levels.
The input for each de-mux is the PD-PWM signals. The
Figure 1. Circuit diagram of half bridge MMC output is then decided based on control signals which are the
indices generated from the sorting block used in
MATLAB/SIMULINK as shown in the appendix. These
indices (ܸ௜௡ௗ௘௫ ) are numbers from 0-7 (in nine level MMC)
that points out the voltage arrangement, however, this is then
converted into binary in order to control the de-mux.

4 Simulation Results
The proposed general voltage balancing technique shown in
Figure 2: (a) Direct current flow (charging) (b) Inverse current flow Figure 4 has been applied to a 9-level MMC. The modeled
(discharging) MMC consists of 8 SMs in each arm, so a total of 16 SMs per
phase has been used. The simulation has been conducted for
Phase disposition technique applied
݉௙ = 2, and for ݉௙ > 2 to validate the effectiveness of the
1
modulation method used to control the MMC at a switching
0.8
frequency equal to the fundamental frequency 50Hz, and at
3kHz. Furthermore, the voltage balancing technique proposed
Amplitude (P.U)

0.6
has been also studied when subjected to an extra load at time
0.4
t=2.35s.
0.2

0 4.1 Fundamental switching frequency

0 0.005 0.01 0.015 0.02 0.025 0.03 0.035 0.04
Time(s) The parameters used in this simulation at ݂௦ ൌ ͷͲ‫ ݖܪ‬are
Figure 3. PD-PWM technigue (at fundamental switching frequency) shown in Table 2. Figure 5 represents a zoomed-in scale of
phase (a) capacitor voltages when balanced at their nominal
value which is 1.25 kV in this case as the DC link is 10 kV.
S1 S2 ࢂࡿࡹ ࡵࡿࡹ SM Capacitor This indicates the effectiveness of the proposed general
state voltage balancing technique. Figure 6 illustrates the output
ON OFF ܸ௖ ൐Ͳ ON Charging
line voltageܸ௔௕ . Whereas, Figure 7 shows the three phase
ON OFF ܸ௖ ൏Ͳ ON Discharging
OFF ON 0 OFF Unchanged
output voltage. In addition, Figure 8 represents the three
൐Ͳ
OFF ON 0 ൏Ͳ OFF Unchanged phase output current. The system has been also studied when
Table 1: Half-bridge submodule working states
adding extra three phase load to the system at t= 2.35s..

3
 Line voltage Vab
10

Voltage (kV)
0

-5

-10
2.3 2.31 2.32 2.33 2.34 2.35 2.36 2.37 2.38 2.39 2.4
Time (s)

Figure 6: MMC Line voltage ࢂࢇ࢈

Three phase output voltage

10
8

Voltage (kV)
0

-4

-8
-10
2.3 2.31 2.32 2.33 2.34 2.35 2.36 2.37 2.38 2.39 2.4
Time (s)

Figure 7: Three phase output voltage

Three phase output current

500
Current (A)

-500
2.3 2.31 2.32 2.33 2.34 2.35 2.36 2.37 2.38 2.39 2.4
Time (s)

Figure 8: Three phase output currents

Figure 4: Proposed balancing technique (a) sorting approach (b)
modulation strategy 1.32
SMs capacitor voltages of phase (a) for load change at t=2.35s

1.3

Phase (a) SMs capacitor voltages 1.28

Voltage (kV)

1270
1.26
1260
1.24
1250
Voltage (V)

1.22
1240
1.2
1230 2.25 2.3 2.35 2.4 2.45 2.5
Time (s)

1220 Figure 9: SMs capacitor voltages of phase (a) in case of load change
1210
2.3 2.31 2.32 2.33 2.34 2.35 2.36 2.37 2.38 2.39 2.4
Time (s) Three phase output current for load change at t=2.35s

Figure 5: Zoomed-in scale of the capacitor voltages of phase (a) 800

600

400

200
Current (A)

The ripples in the SMs capacitor voltages have increased 0

-200
slightly, but still balanced at the nominal value as shown in -400

Figure 9. In this case the three phase output voltage was not -600

affected by the sudden change in load as in Figure 10. -800

2.3 2.31 2.32 2.33 2.34 2.35 2.36 2.37 2.38 2.39 2.4
However, the output current has been increased by adding the Time (s)

Figure 10: Three phase currents with load change

extra load as illustrated in Figure 10.

4.2 3kHz switching frequency

Parameter Value
L 5 mH
The parameters used in this simulation at ݂௦ ൌ ͵݇‫ ݖܪ‬are
C 20 ݉‫ܨ‬ shown in Table 3. The same strategy has been applied for݂௦ ൌ
R (load) 10 Ω ͵݇‫ݖܪ‬. As shown in Figure11 that represents a zoomed-in
L(load) 5 mH scale of the capacitor voltages of phase a, when balanced at
ࢌ࢙ 50Hz their nominal value which is also 1.25 kV. Figure 12
ࢂࢊࢉ 10kV illustrates the output line voltage ܸ௔௕ . Whereas, Figure13
࢓ࢇ 0.9 shows the three phase output voltage. In addition to, Figure
Table 2: component parameters at ݂௦ ൌ ͷͲ‫ݖܪ‬

4
14 that represents the three phase output current. Again an
Line voltage Vab
10

extra load has been added to study the effect of a sudden

5
increase in the load demand. The ripples in the SMs capacitor

Voltage (kV)
voltages have increased slightly also at this switching 0

frequency, but still balanced at the nominal value as shown in

Figure 15. However, the output current has been increased by -5

adding the extra load as shown in Figure 16. -10

2.3 2.31 2.32 2.33 2.34 2.35 2.36 2.37 2.38 2.39 2.4
The results generated from the different switching Time (s)

frequencies proves the efficiency of the modulation technique Figure 12: Line voltage ࢂࢇ࢈
Three phase output voltage

used PD-PWM as it allows the operation of the MMC at 10

different switching frequencies starting from the fundamental 5

switching frequency ݂௦ ൌ ͷͲ‫ ݖܪ‬and at several modulation

Voltage (kV)
indices. It is expected to have some low order harmonics 0

using the PD-PWM technique with a small number of levels, -5

therefore, selective harmonic elimination (SHE) could be
used instead. Also, subjecting the system to a sudden change -10
2.3 2.31 2.32 2.33 2.34 2.35 2.36 2.37 2.38 2.39 2.4

in the load did not affect the behavior of the voltage Time(s)

Figure 13: Three phase output voltage

balancing technique which proves the effectiveness of the Three phase output current

sorting algorithm used. 500

Current (A)

Parameter Value 0

L 2500 ߤH
C 1 ݉‫ܨ‬
R (load) 10 Ω -500
2.3 2.31 2.32 2.33 2.34 2.35 2.36 2.37 2.38 2.39 2.4
L(load) 5 mH Time(s)

ࢌ࢙ 3kHz Figure 14: Three phase output currents

ࢂࢊࢉ 10kV 1.3
SMs capacitor voltages of phase (a) for load change at t=2.35s

࢓ࢇ 0.9
1.28
Table 3: component parameters at ݂௦ ൌ ͵݇‫ݖܪ‬
1.26
Voltage (kV)

5 Conclusion 1.24

In conclusion, a generalized MATLAB/Simulink model for 1.22

the capacitor voltages’ balancing in MMC has been presented 1.2

in this paper. This balancing strategy simply measures the 1.18

2.25 2.3 2.35 2.4 2.45
Time (s)
SMs capacitor voltages and sort them in either ascending or Figure 15: SMs capacitor voltages of phase (a) in case of load
descending order according to the arm current polarity. Based change
on this, a swapping technique has been developed to switch Three phase output current for load change at t=2.35s

the modulation signals between the half bridge cells in order 800

to maintain the capacitor voltages at their nominal value. A 9- 600

400
level MMC has been modeled and simulated using MATLAB 200
Current (A)

/Simulink in which PD-PWM modulation technique was 0

applied to control the switches. The presented balancing -200

-400
technique has been applied to the modeled MMC to verify its -600

functionality. The system has been tested at the fundamental -800

2.3 2.31 2.32 2.33 2.34 2.35 2.36 2.37 2.38 2.39 2.4
switching frequency and at a higher switching frequency. For Time (s)

both cases a sudden change in the load has been added to Figure 16: Three phase output current in case of load change
check the validity of the sorting algorithm used. The results
obtained in the earlier shows the effectiveness of the used Appendix:
voltage balancing technique.
Phase (a) SMs capacitor voltages at 3kHz
1.27

1.265

1.26
Voltage (kV)

1.255

1.25

1.245

1.24

1.235

1.23
2.3 2.31 2.32 2.33 2.34 2.35 2.36 2.37 2.38 2.39 2.4
Times (s)

Figure 11: SMs capacitor voltages of phase (a) Figure 17: Voltage balancing technique Simulink blocks.

5
Where, m is the number of cells per arm and j is the phase
(a,b, and c).
References:
[1] Rodriguez, J.; Jih-Sheng Lai; Fang Zheng Peng, "Multilevel
inverters: a survey of topologies, controls, and
applications," Industrial Electronics, IEEE Transactions on ,
vol.49, no.4, pp.724,738, Aug 2002.
[2] Jih-Sheng Lai; Fang Zheng Peng, "Multilevel converters-a new
breed of power converters," Industry Applications, IEEE
Transactions on , vol.32, no.3, pp.509,517, May/Jun 1996
[3] A. Nabae, I. Takahashi, and H. Akagi, “A new neutral-point
clamped PWM inverter,” IEEE Trans. Ind. Applicat., vol. IA-
17, pp. 518–523, Sept./Oct. 1981.
[4] Pulikanti, S.R.; Agelidis, V.G., "Hybrid Flying-Capacitor-Based
Active-Neutral-Point-Clamped Five-Level Converter Operated
With SHE-PWM," Industrial Electronics, IEEE Transactions
on, vol.58, no.10, pp.4643,4653, Oct. 2011
[5] Massoud, A.M.; Ahmed, S.; Enjeti, P.N.; Williams, B.W.,
"Evaluation of a Multilevel Cascaded-Type Dynamic Voltage
Restorer Employing Discontinuous Space Vector
Modulation," Industrial Electronics, IEEE Transactions on ,
vol.57, no.7, pp.2398,2410, July 2010
[6] Jiangchao Qin; Saeedifard, M., "Reduced Switching-Frequency
Voltage-Balancing Strategies for Modular Multilevel HVDC
Converters," Power Delivery, IEEE Transactions on , vol.28,
no.4, pp.2403,2410, Oct. 2013
[7] Ajaei, F.B.; Iravani, R., "Enhanced Equivalent Model of the
Modular Multilevel Converter," Power Delivery, IEEE
Transactions on , vol.PP, no.99, pp.1,1
[8] Nami, A.; Jiaqi Liang; Dijkhuizen, F.; Demetriades, G.D.,
"Modular Multilevel Converters for HVDC Applications:
Review on Converter Cells and Functionalities," Power
Electronics, IEEE Transactions on , vol.30, no.1, pp.18,36, Jan.
2015
[9] Ilves, K.; Harnefors, L.; Norrga, S.; Nee, H.-P., "Predictive
sorting algorithm for modular multilevel converters minimizing
the spread in the submodule capacitor voltages," ECCE Asia
Downunder (ECCE Asia), 2013 IEEE , vol., no., pp.325,331, 3-
6 June 2013
[10] Jiangchao Qin; Saeedifard, M., "Predictive Control of a
Modular Multilevel Converter for a Back-to-Back HVDC
System," Power Delivery, IEEE Transactions on , vol.27, no.3,
pp.1538,1547, July 2012
[11] Jun Mei; Bailu Xiao; Ke Shen; Tolbert, L.M.; Jian Yong Zheng,
"Modular Multilevel Inverter with New Modulation Method
and Its Application to Photovoltaic Grid-Connected
Generator," Power Electronics, IEEE Transactions on , vol.28,
no.11, pp.5063,5073, Nov. 2013
[12] Jun Mei; Ke Shen; Bailu Xiao; Tolbert, L.M.; Jianyong Zheng,
"A New Selective Loop Bias Mapping Phase Disposition PWM
With Dynamic Voltage Balance Capability for Modular
Multilevel Converter," Industrial Electronics, IEEE
Transactions on , vol.61, no.2, pp.798,807, Feb. 2014
[13] Kui Wang; Yongdong Li; Zedong Zheng; Lie Xu, "Voltage
Balancing and Fluctuation-Suppression Methods of Floating
Capacitors in a New Modular Multilevel Converter," Industrial
Electronics, IEEE Transactions on , vol.60, no.5, pp.1943,1954,
May 2013
[14] Hagiwara, M.; Akagi, H., "Control and Experiment of
Pulsewidth-Modulated Modular Multilevel Converters," Power
Electronics, IEEE Transactions on , vol.24, no.7, pp.1737,1746,
July 2009
[15] Yuebin Zhou; Daozhuo Jiang; Pengfei Hu; Jie Guo; Yiqiao
Liang; Zhiyong Lin, "A Prototype of Modular Multilevel
Converters," Power Electronics, IEEE Transactions on , vol.29,
no.7, pp.3267,3278, July 2014
[16] Binbin Li; Rongfeng Yang; Dandan Xu; Gaolin Wang; Wei
Wang; Dianguo Xu, "Analysis of the Phase-Shifted Carrier
Modulation for Modular Multilevel Converters," Power
Electronics, IEEE Transactions on , vol.30, no.1, pp.297,310,
Jan. 2015
[17] Gum Tae Son; Hee-Jin Lee; Tae Sik Nam; Yong-Ho Chung;
Uk-Hwa Lee; Seung-Taek Baek; Kyeon Hur; Jung-Wook Park,
"Design and Control of a Modular Multilevel HVDC Converter
With Redundant Power Modules for Noninterruptible Energy
Transfer," Power Delivery, IEEE Transactions on , vol.27, no.3,
pp.1611,1619, July 2012
[18] Ke Shen; Dan Zhao; Jun Mei; Tolbert, L.M.; Jianze Wang;
Mingfei Ban; Yanchao Ji; Xingguo Cai, "Elimination of
Harmonics in a Modular Multilevel Converter Using Particle
Swarm Optimization-Based Staircase Modulation
Strategy," Industrial Electronics, IEEE Transactions on ,
vol.61, no.10, pp.5311,5322, Oct. 2014
[19] Sixing Du; Jinjun Liu; Teng Liu, "Modulation and Closed-
Loop-Based DC Capacitor Voltage Control for MMC With
Fundamental Switching Frequency," Power Electronics, IEEE
Transactions on , vol.30, no.1, pp.327,338, Jan. 2015
[20] Fujin Deng; Zhe Chen, "A Control Method for Voltage
Balancing in Modular Multilevel Converters," Power
Electronics, IEEE Transactions on , vol.29, no.1, pp.66,76, Jan.
2014
[21] Jun Mei; Bailu Xiao; Ke Shen; Tolbert, L.M.; Jian Yong Zheng,
"Modular Multilevel Inverter with New Modulation Method
and Its Application to Photovoltaic Grid-Connected
Generator," Power Electronics, IEEE Transactions on , vol.28,
no.11, pp.5063,5073, Nov. 2013
[22] Yi Deng; Yebin Wang; Koon Hoo Teo; Harley, R.G., "Space
vector modulation method for modular multilevel
converters," Industrial Electronics Society, IECON 2014 - 40th
Annual Conference of the IEEE , vol., no., pp.4715,4721, Oct.
29 2014-Nov. 1 2014
[23] Baroni, B.R.; Mendes, M.A.S.; Cortizo, P.C.; Lisboa, A.C.;
Saldanha, R.R., "Application of modular multilevel converter
for HVDC transmission with selective harmonics," Industrial
Electronics Society, IECON 2013 - 39th Annual Conference of
the IEEE , vol., no., pp.6195,6200, 10-13 Nov. 2013.
[24] Meshram, P.M.; Borghate, V.B., "A Simplified Nearest Level
Control (NLC) Voltage Balancing Method for Modular
Multilevel Converter (MMC)," Power Electronics, IEEE
Transactions on , vol.30, no.1, pp.450,462, Jan. 2015
[25] Yu, F.; Lin, W.; Wang, X.; Xie, D., "Fast Voltage-
Balancing Control and Fast Numerical Simulation Model for
the Modular Multilevel Converter," Power Delivery, IEEE
Transactions on , vol.PP, no.99, pp.1,1
[26] S. Kouro, M. Malinowski, K. Gopakumar, J. Pou, L. G.
Franquelo, B.Wu, J. Rodriguez, M. A. Perez, and J. I. Leon,
“Recent advances and industrial applications of multilevel
converters,” IEEE Trans. Ind. Electron., vol. 57, no. 8, pp.
2553–2580, Aug. 2010.