Professional Documents
Culture Documents
Logic
CS270
Max Luttrell, Spring 2017
sequential logic
• combinational logic: output is a function of
present input only
A B
Stabilizes to A=B'
set-reset latch
(SR latch)
S R Q Q'
0 0
S Q′ 0 1
1 0
1 1
Q R x
0
y
0
or nor
0 1
0 1 1 0
1 0 1 0
1 1 1 0
set-reset latch
(SR latch)
Q′
S R Q Q'
S 0 0 Q Q'
0 1 0 1
1 0 1 0
Q R 1 1 ? ?
0 0 Q Q' hold
S Q′ 0 1 0 1 reset
1 0 1 0 set
not
1 1 ? ?
allowed
Q R
D latch
(unclocked)
D Q Q'
S 0
D Q′
1
R
Q
x y or nor
0 0 0 1
D S Q
0 1 1 0
R Q’
1 0 1 0
1 1 1 0
D latch
(unclocked)
D Q Q'
S 0 0 1
D Q′
1 1 0
R
Q
x y or nor
0 0 0 1
D S Q
0 1 1 0
R Q’
1 0 1 0
1 1 1 0
clocks
• clocks are used to coordinate state changes
1
0
clock
period clock
low
D latch
(clocked)
clk D Q Q'
D S Q 0 0
0 1
clk R Q’ 1 0
1 1
D latch
(clocked)
D S Q clk D Q Q'
0 0 Q Q'
clk R Q’
0 1 Q Q'
1 0 0 1
clk 1 1 1 0
D
Q
time
edge-triggered D flip flop
(clocked)
1 0 0 clk D Q Q'
D D Q X D Q Q 0 0 Q Q'
0 Q 1 Q Q 0 1 Q Q'
clk L Q' c L Q' Q'
1 0 0 1
c
1 1 1 0
clk
D
X
Q
time
edge-triggered D flip flop
(clocked)
• data captured when
1 0 0 clock is high
D D Q X D Q Q
0 Q 1 Q Q
clk L Q' c L Q' Q' • output only changes
on falling clock
c
edge
clk
D
X
Q
time
register
D0
• D flip flops in parallel
with a shared clock
D1
• could add a "write
enable (WE)" input
D2 (only allow writes if
WE==1)
D3
clk
4 bit register
summary
• Set-Reset (SR) Latch can store one bit, and we can
change its value. But, it has a forbidden state.
current next
state state
Q1 Q0 D1 D0
0 0
0 1
1 0
1 1
counter
• a 2-bit counter cycles through numbers: 00, 01,
10, 11
1 1 0 0
•
counter with ROM
instead of combinational logic, we could also use a 4x2 ROM to
implement our counter. recall: a 4x2 ROM:
4x2 ROM
2 bit address contents
register
>clk 00 01
01 10
10 11
11 00
ROM outputs
finite state machine
• a finite state machine has:
• an internal state
• inputs
• current state
finite state machine
(Mealy Machine)
Current
Registers
Bravado
• inputs Dining
Hall
• traffic sensors: TA, LB
TB (1 if car on
LA TB
sensor, 0 if not) LA
Academic TA TA Ave.
• outputs
Labs TB LB Dorms
• lights: LA, LB
Blvd.
Fields
finite state machine
example: traffic light controller
• inputs
CLK
• traffic sensors: TA,
TB (1 if car on
sensor, 0 if not)
TA Traffic LA
Light
• reset TB Controller LB
• clock
• outputs Reset
• lights: LA, LB
traffic rules
• when reset is 1, LA is
green and LB is red
• as long as traffic on
Bravado
Dining
Academic Ave (TA is 1), Hall
keep LA green LB
LA TB
• when TA goes low, LA
Blvd.
Bravado Fields
Bravado
Dining
Hall
LB
S0 LA TB
LA
LA: green
LB: red Academic TA TA Ave.
Labs TB LB Dorms
Blvd.
Fields
state transition diagram
• outputs are shown in the
state
TA
Reset
• states: circles TA
S0 S1
LA: green LA: yellow
• transitions: arcs LB: red LB: red
Bravado
Dining
Hall
LB
LA TB S3 S2
LA
LA: red LA: red
Academic TA TA Ave. LB: yellow LB: green
TB
Labs TB LB Dorms TB
Blvd.
Fields
state transition table
Current Next
Inputs TA
state state Reset
S0 TA S1
S TA TB S+
LA: green LA: yellow
S0 0 X S1 LB: red LB: red
S0 1 X S0
S1 X X S2
S2 X 0 S3 S3 S2
LA: red LA: red
S2 X 1 S2 LB: yellow LB: green
TB
S3 X X S0 TB
encoded state
transition table
State Encoding
S0 00
TA
S1 01 Reset
S0 TA S1
S2 10
LA: green LA: yellow
S3 11 LB: red LB: red
Bravado
Dining
Output Encoding Hall
LB
green 00
LA TB
LA
yellow 01
Academic TA TA Ave.
red 10 TB LB Dorms
Labs
Blvd.
Current State Outputs Fields
Sa1 Sb0 LA1 LA0 LB1 LB0
0 0 0 0 1 0
LA1 = a
0 1 0 1 1 0 LA0 = a'b
1 0 1 0 0 0 LB1 = a'
1 1 1 0 0 1 LB0 = ab
state table with inputs and
outputs
Current
Inputs Next state Outputs
state
a b TA TB a+ b+ LA1 LA0 LB1 LB0
0 0 0 X 0 1 0 0 1 0
0 0 1 X 0 0 0 0 1 0
0 1 X X 1 0 0 1 1 0
Bravado
Dining
1 0 X 0 1 1 1 0 0 0 Hall
1 0 X 1 1 0 1 0 0 0 LB
1 1 X X 0 0 1 0 0 1 LA TB
LA
Academic TA TA Ave.
Labs TB LB Dorms
Blvd.
Fields
state register
CLK
a+
S'1 a
S1
b+
S'0 b
S0
r
Reset
state register
TA b+
S' 0
b0
S
r
TB Reset
Sa1 b0
S
TA b+
S'0 b0
S
LB1
r
TB Reset
Sa1 S
b0 LB0