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UNIT- IV PART B
1.Explain distributed memory architecture with neat diagram. NOV/DEC2016, APR/MAY
2017(ECE,CSE)
2.Explain the architecture of symmetric shared memory with a neat sketch.
3.Describe the features of synchronization.
4.What are the models of memory consistency. Explain. NOV/DEC2016, APR/MAY
2017(ECE,CSE)
5.Explain the features of i7 processor with neat diagram. APR/MAY 2017(CSE)
6.Explain the features of SMT & CMP processors with a neat sketch. APR/MAY 2017(CSE)
7.Explain snooping protocol with a state diagram.
8.Explain the directory based protocol with a state diagram.
9.How is multithreading used to exploit thread level parallelism within a processor?
10.Describe the basic structure of a centralized shared memory multiprocessor in detail.
11.Describe the implementation of directory based cache coherence protocol.
12.Describe sequential and relaxed consistency model.
13.Explain about synchronization techniques used in multiprocessor system. APR/MAY 2017
UNIT-V PART-A
1.What is memory?
Memory is a device used to store and data and instructions required for any operation.
2.What is bandwidth?
The maximum amount of information that can be transferred to or from the memory per
unit time is called bandwidth.
3.Define cache.
It’s a small fast intermediate memory between the processor and the main memory.
4.Give the mapping techniques of cache.
Direct mapping
Fully associative
Set associative
5.What is write stall?
When the processor must wait for writes to complete during write through, the processor
caches is said to write stall.
6.Define mapping functions.
The correspondence of memory blocks in cache with the memory blocks in the main
memory is called as mapping functions.
7.What is address translation?
The conversion of virtual address to physical address is called as address translation.
8.What is seek time?
The average time to move a arm to the desired track is called seek time.
9.Define rotational latency.
The time taken to move the read writes head to a particular sector.
10.Define page fault.
If the processor access for the particular page in main memory and if the page is not
present there then it is known as page fault.
11.Define cache hit.
When the CPU refers to memory and finds a required word in cache it is called as cache
hit.
12.Define hit ratio.
The ratio of the number of hits divided by the total CPU references to memory is the hit
ratio.
13.Define miss.
When the CPU refers to memory and if the required word is not found in cache, is called
as miss.
14.Write a formula for average memory access time.
Average memory access time = hit time + miss rate × miss penalty
15.List the method to improve the cache performance.
Reduce the miss rate
Reduce the miss penalty
Reduce the time to hit in the cache
16.What is cylinder?
It is used to all the tracks under the arms at a given points on all surfaces.
17.What is transfer time?
It is the time it takes to transfer a block of bits, typically a sector under read/write head
18.What is called pages?
The address pages is usually broken into fixed-size blocks, called pages. each page
resides either in main memory or on disk.
19.What are the categories of cache miss?
Capacity, compulsory, conflict
20.Define RAID.
RAID is Redundant Array of Independent Disks. It is a way of storing the same data in
different places on multiple hard disks.
21.What is write back?
If the write is deferred until the cache line is flushed from the cache, is called as write
back.
22.Compare software and hardware RAID.
Parameters software RAID hardware RAID
Write back caching no yes
Disk hot swapping no yes
Boot partition no yes
23.What is temporal locality? APR/MAY 2017(CSE)
Recently referenced items are likely to be referenced again in the near future. This is
often caused by special program constructs such as iterative loops, process stacks, temporary
variables or subroutines
24.Define spatial locality. APR/MAY 2017(CSE)
It refers to the tendency for a process to access items whose addresses are near one
another.
25.what is miss penalty?
The number of stall cycles depends on both the number of misses and the cost per miss,
which is called the miss penalty.
26.What is memory stall cycles?
The number of cycles during which the CPU is stalled waiting for a memory access is
called memory stall cycles.
27.What is synchronous bus?
It includes a clock in the control lines and a fixed protocol for sending address and data
relative to the clock.
28.Explain the difference between latency and throughput.
Latency is defined as the time required processing a single instruction, while throughput
is defined as the number of instructions processed per second.
29.What are the techniques to reduce hit time?
Small and simple cache: direct mapped
Avoid address translation during indexing of the cache
Pipelined cache access
Trace cache
30.How are the conflicts misses divided?
Eight way: conflict misses due to going from fully associative to eight way associative
Four way: conflict misses due to going from eight way associative to four way
Associative
Two way: conflict misses due to going from four way associative to two way associative
One way: conflict misses due to going from two way associative to one way associative
31.List the six basic optimizations techniques of cache. NOV/DEC 2016
32.What are the types of storage devices? NOV/DEC 2016
33.What are the similarities and differences between SCSI and IDE? APR/MAY 2017
34.Explain the need to implement memory as a hierarchy. APR/MAY 2017(ECE,CSE)
UNIT-V PART B
1.What are the cache measures. Explain./Describe various cache optimization techniques with
example. APR/MAY 2017(ECE,CSE)
2.Explain four memory hierarchies with an example.
3.How to reduce cache miss penalty? Explain.
4.How to reduce hit time. Explain.
5.Explain briefly about main memory with its performances.
6.Explain memory technology with its types.
7.Explain in detail about buses and its standards.
8.What is RAID. Explain its levels with neat sketch. NOV/DEC2016, APR/MAY
2017(ECE,CSE)
9.Write short note on
a)Reliability
b)Availability
c)Dependability
10.Mention performance measures of I/O system. NOV/DEC2016, APR/MAY
2017(ECE,CSE)
11.What are the techniques are used to reduce miss rate? Explain.
12.Define Virtual memory. Explain the techniques for fast address translation.
13.What are the types of storage devices? Explain.
14.Describe the design and standards of a bus with a neat diagram.
15.Explain the categories of misses and how will you reduce cache miss rate. NOV/DEC2016
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